1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/export.h>
3 #include <linux/bitops.h>
4 #include <linux/elf.h>
5 #include <linux/mm.h>
6
7 #include <linux/io.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/random.h>
11 #include <linux/topology.h>
12 #include <asm/processor.h>
13 #include <asm/apic.h>
14 #include <asm/cacheinfo.h>
15 #include <asm/cpu.h>
16 #include <asm/spec-ctrl.h>
17 #include <asm/smp.h>
18 #include <asm/pci-direct.h>
19 #include <asm/delay.h>
20 #include <asm/debugreg.h>
21
22 #ifdef CONFIG_X86_64
23 # include <asm/mmconfig.h>
24 # include <asm/set_memory.h>
25 #endif
26
27 #include "cpu.h"
28
29 /*
30 * nodes_per_socket: Stores the number of nodes per socket.
31 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
32 * Node Identifiers[10:8]
33 */
34 static u32 nodes_per_socket = 1;
35
36 /*
37 * AMD errata checking
38 *
39 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
40 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
41 * have an OSVW id assigned, which it takes as first argument. Both take a
42 * variable number of family-specific model-stepping ranges created by
43 * AMD_MODEL_RANGE().
44 *
45 * Example:
46 *
47 * const int amd_erratum_319[] =
48 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
49 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
50 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
51 */
52
53 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
54 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
55 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
56 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
57 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
58 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
59 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
60
61 static const int amd_erratum_400[] =
62 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
63 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
64
65 static const int amd_erratum_383[] =
66 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
67
68 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */
69 static const int amd_erratum_1054[] =
70 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
71
72 static const int amd_zenbleed[] =
73 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
74 AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
75 AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
76 AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
77
78 static const int amd_erratum_1485[] =
79 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
80 AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
81
cpu_has_amd_erratum(struct cpuinfo_x86 * cpu,const int * erratum)82 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
83 {
84 int osvw_id = *erratum++;
85 u32 range;
86 u32 ms;
87
88 if (osvw_id >= 0 && osvw_id < 65536 &&
89 cpu_has(cpu, X86_FEATURE_OSVW)) {
90 u64 osvw_len;
91
92 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
93 if (osvw_id < osvw_len) {
94 u64 osvw_bits;
95
96 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
97 osvw_bits);
98 return osvw_bits & (1ULL << (osvw_id & 0x3f));
99 }
100 }
101
102 /* OSVW unavailable or ID unknown, match family-model-stepping range */
103 ms = (cpu->x86_model << 4) | cpu->x86_stepping;
104 while ((range = *erratum++))
105 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
106 (ms >= AMD_MODEL_RANGE_START(range)) &&
107 (ms <= AMD_MODEL_RANGE_END(range)))
108 return true;
109
110 return false;
111 }
112
rdmsrl_amd_safe(unsigned msr,unsigned long long * p)113 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
114 {
115 u32 gprs[8] = { 0 };
116 int err;
117
118 WARN_ONCE((boot_cpu_data.x86 != 0xf),
119 "%s should only be used on K8!\n", __func__);
120
121 gprs[1] = msr;
122 gprs[7] = 0x9c5a203a;
123
124 err = rdmsr_safe_regs(gprs);
125
126 *p = gprs[0] | ((u64)gprs[2] << 32);
127
128 return err;
129 }
130
wrmsrl_amd_safe(unsigned msr,unsigned long long val)131 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
132 {
133 u32 gprs[8] = { 0 };
134
135 WARN_ONCE((boot_cpu_data.x86 != 0xf),
136 "%s should only be used on K8!\n", __func__);
137
138 gprs[0] = (u32)val;
139 gprs[1] = msr;
140 gprs[2] = val >> 32;
141 gprs[7] = 0x9c5a203a;
142
143 return wrmsr_safe_regs(gprs);
144 }
145
146 /*
147 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
148 * misexecution of code under Linux. Owners of such processors should
149 * contact AMD for precise details and a CPU swap.
150 *
151 * See http://www.multimania.com/poulot/k6bug.html
152 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
153 * (Publication # 21266 Issue Date: August 1998)
154 *
155 * The following test is erm.. interesting. AMD neglected to up
156 * the chip setting when fixing the bug but they also tweaked some
157 * performance at the same time..
158 */
159
160 #ifdef CONFIG_X86_32
161 extern __visible void vide(void);
162 __asm__(".text\n"
163 ".globl vide\n"
164 ".type vide, @function\n"
165 ".align 4\n"
166 "vide: ret\n");
167 #endif
168
init_amd_k5(struct cpuinfo_x86 * c)169 static void init_amd_k5(struct cpuinfo_x86 *c)
170 {
171 #ifdef CONFIG_X86_32
172 /*
173 * General Systems BIOSen alias the cpu frequency registers
174 * of the Elan at 0x000df000. Unfortunately, one of the Linux
175 * drivers subsequently pokes it, and changes the CPU speed.
176 * Workaround : Remove the unneeded alias.
177 */
178 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
179 #define CBAR_ENB (0x80000000)
180 #define CBAR_KEY (0X000000CB)
181 if (c->x86_model == 9 || c->x86_model == 10) {
182 if (inl(CBAR) & CBAR_ENB)
183 outl(0 | CBAR_KEY, CBAR);
184 }
185 #endif
186 }
187
init_amd_k6(struct cpuinfo_x86 * c)188 static void init_amd_k6(struct cpuinfo_x86 *c)
189 {
190 #ifdef CONFIG_X86_32
191 u32 l, h;
192 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
193
194 if (c->x86_model < 6) {
195 /* Based on AMD doc 20734R - June 2000 */
196 if (c->x86_model == 0) {
197 clear_cpu_cap(c, X86_FEATURE_APIC);
198 set_cpu_cap(c, X86_FEATURE_PGE);
199 }
200 return;
201 }
202
203 if (c->x86_model == 6 && c->x86_stepping == 1) {
204 const int K6_BUG_LOOP = 1000000;
205 int n;
206 void (*f_vide)(void);
207 u64 d, d2;
208
209 pr_info("AMD K6 stepping B detected - ");
210
211 /*
212 * It looks like AMD fixed the 2.6.2 bug and improved indirect
213 * calls at the same time.
214 */
215
216 n = K6_BUG_LOOP;
217 f_vide = vide;
218 OPTIMIZER_HIDE_VAR(f_vide);
219 d = rdtsc();
220 while (n--)
221 f_vide();
222 d2 = rdtsc();
223 d = d2-d;
224
225 if (d > 20*K6_BUG_LOOP)
226 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
227 else
228 pr_cont("probably OK (after B9730xxxx).\n");
229 }
230
231 /* K6 with old style WHCR */
232 if (c->x86_model < 8 ||
233 (c->x86_model == 8 && c->x86_stepping < 8)) {
234 /* We can only write allocate on the low 508Mb */
235 if (mbytes > 508)
236 mbytes = 508;
237
238 rdmsr(MSR_K6_WHCR, l, h);
239 if ((l&0x0000FFFF) == 0) {
240 unsigned long flags;
241 l = (1<<0)|((mbytes/4)<<1);
242 local_irq_save(flags);
243 wbinvd();
244 wrmsr(MSR_K6_WHCR, l, h);
245 local_irq_restore(flags);
246 pr_info("Enabling old style K6 write allocation for %d Mb\n",
247 mbytes);
248 }
249 return;
250 }
251
252 if ((c->x86_model == 8 && c->x86_stepping > 7) ||
253 c->x86_model == 9 || c->x86_model == 13) {
254 /* The more serious chips .. */
255
256 if (mbytes > 4092)
257 mbytes = 4092;
258
259 rdmsr(MSR_K6_WHCR, l, h);
260 if ((l&0xFFFF0000) == 0) {
261 unsigned long flags;
262 l = ((mbytes>>2)<<22)|(1<<16);
263 local_irq_save(flags);
264 wbinvd();
265 wrmsr(MSR_K6_WHCR, l, h);
266 local_irq_restore(flags);
267 pr_info("Enabling new style K6 write allocation for %d Mb\n",
268 mbytes);
269 }
270
271 return;
272 }
273
274 if (c->x86_model == 10) {
275 /* AMD Geode LX is model 10 */
276 /* placeholder for any needed mods */
277 return;
278 }
279 #endif
280 }
281
init_amd_k7(struct cpuinfo_x86 * c)282 static void init_amd_k7(struct cpuinfo_x86 *c)
283 {
284 #ifdef CONFIG_X86_32
285 u32 l, h;
286
287 /*
288 * Bit 15 of Athlon specific MSR 15, needs to be 0
289 * to enable SSE on Palomino/Morgan/Barton CPU's.
290 * If the BIOS didn't enable it already, enable it here.
291 */
292 if (c->x86_model >= 6 && c->x86_model <= 10) {
293 if (!cpu_has(c, X86_FEATURE_XMM)) {
294 pr_info("Enabling disabled K7/SSE Support.\n");
295 msr_clear_bit(MSR_K7_HWCR, 15);
296 set_cpu_cap(c, X86_FEATURE_XMM);
297 }
298 }
299
300 /*
301 * It's been determined by AMD that Athlons since model 8 stepping 1
302 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
303 * As per AMD technical note 27212 0.2
304 */
305 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
306 rdmsr(MSR_K7_CLK_CTL, l, h);
307 if ((l & 0xfff00000) != 0x20000000) {
308 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
309 l, ((l & 0x000fffff)|0x20000000));
310 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
311 }
312 }
313
314 /* calling is from identify_secondary_cpu() ? */
315 if (!c->cpu_index)
316 return;
317
318 /*
319 * Certain Athlons might work (for various values of 'work') in SMP
320 * but they are not certified as MP capable.
321 */
322 /* Athlon 660/661 is valid. */
323 if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
324 (c->x86_stepping == 1)))
325 return;
326
327 /* Duron 670 is valid */
328 if ((c->x86_model == 7) && (c->x86_stepping == 0))
329 return;
330
331 /*
332 * Athlon 662, Duron 671, and Athlon >model 7 have capability
333 * bit. It's worth noting that the A5 stepping (662) of some
334 * Athlon XP's have the MP bit set.
335 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
336 * more.
337 */
338 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
339 ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
340 (c->x86_model > 7))
341 if (cpu_has(c, X86_FEATURE_MP))
342 return;
343
344 /* If we get here, not a certified SMP capable AMD system. */
345
346 /*
347 * Don't taint if we are running SMP kernel on a single non-MP
348 * approved Athlon
349 */
350 WARN_ONCE(1, "WARNING: This combination of AMD"
351 " processors is not suitable for SMP.\n");
352 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
353 #endif
354 }
355
356 #ifdef CONFIG_NUMA
357 /*
358 * To workaround broken NUMA config. Read the comment in
359 * srat_detect_node().
360 */
nearby_node(int apicid)361 static int nearby_node(int apicid)
362 {
363 int i, node;
364
365 for (i = apicid - 1; i >= 0; i--) {
366 node = __apicid_to_node[i];
367 if (node != NUMA_NO_NODE && node_online(node))
368 return node;
369 }
370 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
371 node = __apicid_to_node[i];
372 if (node != NUMA_NO_NODE && node_online(node))
373 return node;
374 }
375 return first_node(node_online_map); /* Shouldn't happen */
376 }
377 #endif
378
379 /*
380 * Fix up cpu_core_id for pre-F17h systems to be in the
381 * [0 .. cores_per_node - 1] range. Not really needed but
382 * kept so as not to break existing setups.
383 */
legacy_fixup_core_id(struct cpuinfo_x86 * c)384 static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
385 {
386 u32 cus_per_node;
387
388 if (c->x86 >= 0x17)
389 return;
390
391 cus_per_node = c->x86_max_cores / nodes_per_socket;
392 c->cpu_core_id %= cus_per_node;
393 }
394
395
amd_get_topology_early(struct cpuinfo_x86 * c)396 static void amd_get_topology_early(struct cpuinfo_x86 *c)
397 {
398 if (cpu_has(c, X86_FEATURE_TOPOEXT))
399 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
400 }
401
402 /*
403 * Fixup core topology information for
404 * (1) AMD multi-node processors
405 * Assumption: Number of cores in each internal node is the same.
406 * (2) AMD processors supporting compute units
407 */
amd_get_topology(struct cpuinfo_x86 * c)408 static void amd_get_topology(struct cpuinfo_x86 *c)
409 {
410 int cpu = smp_processor_id();
411
412 /* get information required for multi-node processors */
413 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
414 int err;
415 u32 eax, ebx, ecx, edx;
416
417 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
418
419 c->cpu_die_id = ecx & 0xff;
420
421 if (c->x86 == 0x15)
422 c->cu_id = ebx & 0xff;
423
424 if (c->x86 >= 0x17) {
425 c->cpu_core_id = ebx & 0xff;
426
427 if (smp_num_siblings > 1)
428 c->x86_max_cores /= smp_num_siblings;
429 }
430
431 /*
432 * In case leaf B is available, use it to derive
433 * topology information.
434 */
435 err = detect_extended_topology(c);
436 if (!err)
437 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
438
439 cacheinfo_amd_init_llc_id(c, cpu);
440
441 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
442 u64 value;
443
444 rdmsrl(MSR_FAM10H_NODE_ID, value);
445 c->cpu_die_id = value & 7;
446
447 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
448 } else
449 return;
450
451 if (nodes_per_socket > 1) {
452 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
453 legacy_fixup_core_id(c);
454 }
455 }
456
457 /*
458 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
459 * Assumes number of cores is a power of two.
460 */
amd_detect_cmp(struct cpuinfo_x86 * c)461 static void amd_detect_cmp(struct cpuinfo_x86 *c)
462 {
463 unsigned bits;
464 int cpu = smp_processor_id();
465
466 bits = c->x86_coreid_bits;
467 /* Low order bits define the core id (index of core in socket) */
468 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
469 /* Convert the initial APIC ID into the socket ID */
470 c->phys_proc_id = c->initial_apicid >> bits;
471 /* use socket ID also for last level cache */
472 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
473 }
474
amd_get_nb_id(int cpu)475 u16 amd_get_nb_id(int cpu)
476 {
477 return per_cpu(cpu_llc_id, cpu);
478 }
479 EXPORT_SYMBOL_GPL(amd_get_nb_id);
480
amd_get_nodes_per_socket(void)481 u32 amd_get_nodes_per_socket(void)
482 {
483 return nodes_per_socket;
484 }
485 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
486
srat_detect_node(struct cpuinfo_x86 * c)487 static void srat_detect_node(struct cpuinfo_x86 *c)
488 {
489 #ifdef CONFIG_NUMA
490 int cpu = smp_processor_id();
491 int node;
492 unsigned apicid = c->apicid;
493
494 node = numa_cpu_node(cpu);
495 if (node == NUMA_NO_NODE)
496 node = per_cpu(cpu_llc_id, cpu);
497
498 /*
499 * On multi-fabric platform (e.g. Numascale NumaChip) a
500 * platform-specific handler needs to be called to fixup some
501 * IDs of the CPU.
502 */
503 if (x86_cpuinit.fixup_cpu_id)
504 x86_cpuinit.fixup_cpu_id(c, node);
505
506 if (!node_online(node)) {
507 /*
508 * Two possibilities here:
509 *
510 * - The CPU is missing memory and no node was created. In
511 * that case try picking one from a nearby CPU.
512 *
513 * - The APIC IDs differ from the HyperTransport node IDs
514 * which the K8 northbridge parsing fills in. Assume
515 * they are all increased by a constant offset, but in
516 * the same order as the HT nodeids. If that doesn't
517 * result in a usable node fall back to the path for the
518 * previous case.
519 *
520 * This workaround operates directly on the mapping between
521 * APIC ID and NUMA node, assuming certain relationship
522 * between APIC ID, HT node ID and NUMA topology. As going
523 * through CPU mapping may alter the outcome, directly
524 * access __apicid_to_node[].
525 */
526 int ht_nodeid = c->initial_apicid;
527
528 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
529 node = __apicid_to_node[ht_nodeid];
530 /* Pick a nearby node */
531 if (!node_online(node))
532 node = nearby_node(apicid);
533 }
534 numa_set_node(cpu, node);
535 #endif
536 }
537
early_init_amd_mc(struct cpuinfo_x86 * c)538 static void early_init_amd_mc(struct cpuinfo_x86 *c)
539 {
540 #ifdef CONFIG_SMP
541 unsigned bits, ecx;
542
543 /* Multi core CPU? */
544 if (c->extended_cpuid_level < 0x80000008)
545 return;
546
547 ecx = cpuid_ecx(0x80000008);
548
549 c->x86_max_cores = (ecx & 0xff) + 1;
550
551 /* CPU telling us the core id bits shift? */
552 bits = (ecx >> 12) & 0xF;
553
554 /* Otherwise recompute */
555 if (bits == 0) {
556 while ((1 << bits) < c->x86_max_cores)
557 bits++;
558 }
559
560 c->x86_coreid_bits = bits;
561 #endif
562 }
563
bsp_init_amd(struct cpuinfo_x86 * c)564 static void bsp_init_amd(struct cpuinfo_x86 *c)
565 {
566
567 #ifdef CONFIG_X86_64
568 if (c->x86 >= 0xf) {
569 unsigned long long tseg;
570
571 /*
572 * Split up direct mapping around the TSEG SMM area.
573 * Don't do it for gbpages because there seems very little
574 * benefit in doing so.
575 */
576 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
577 unsigned long pfn = tseg >> PAGE_SHIFT;
578
579 pr_debug("tseg: %010llx\n", tseg);
580 if (pfn_range_is_mapped(pfn, pfn + 1))
581 set_memory_4k((unsigned long)__va(tseg), 1);
582 }
583 }
584 #endif
585
586 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
587
588 if (c->x86 > 0x10 ||
589 (c->x86 == 0x10 && c->x86_model >= 0x2)) {
590 u64 val;
591
592 rdmsrl(MSR_K7_HWCR, val);
593 if (!(val & BIT(24)))
594 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
595 }
596 }
597
598 if (c->x86 == 0x15) {
599 unsigned long upperbit;
600 u32 cpuid, assoc;
601
602 cpuid = cpuid_edx(0x80000005);
603 assoc = cpuid >> 16 & 0xff;
604 upperbit = ((cpuid >> 24) << 10) / assoc;
605
606 va_align.mask = (upperbit - 1) & PAGE_MASK;
607 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
608
609 /* A random value per boot for bit slice [12:upper_bit) */
610 va_align.bits = get_random_int() & va_align.mask;
611 }
612
613 if (cpu_has(c, X86_FEATURE_MWAITX))
614 use_mwaitx_delay();
615
616 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
617 u32 ecx;
618
619 ecx = cpuid_ecx(0x8000001e);
620 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
621 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
622 u64 value;
623
624 rdmsrl(MSR_FAM10H_NODE_ID, value);
625 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
626 }
627
628 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
629 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
630 c->x86 >= 0x15 && c->x86 <= 0x17) {
631 unsigned int bit;
632
633 switch (c->x86) {
634 case 0x15: bit = 54; break;
635 case 0x16: bit = 33; break;
636 case 0x17: bit = 10; break;
637 default: return;
638 }
639 /*
640 * Try to cache the base value so further operations can
641 * avoid RMW. If that faults, do not enable SSBD.
642 */
643 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
644 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
645 setup_force_cpu_cap(X86_FEATURE_SSBD);
646 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
647 }
648 }
649 }
650
early_detect_mem_encrypt(struct cpuinfo_x86 * c)651 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
652 {
653 u64 msr;
654
655 /*
656 * BIOS support is required for SME and SEV.
657 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
658 * the SME physical address space reduction value.
659 * If BIOS has not enabled SME then don't advertise the
660 * SME feature (set in scattered.c).
661 * For SEV: If BIOS has not enabled SEV then don't advertise the
662 * SEV and SEV_ES feature (set in scattered.c).
663 *
664 * In all cases, since support for SME and SEV requires long mode,
665 * don't advertise the feature under CONFIG_X86_32.
666 */
667 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
668 /* Check if memory encryption is enabled */
669 rdmsrl(MSR_K8_SYSCFG, msr);
670 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
671 goto clear_all;
672
673 /*
674 * Always adjust physical address bits. Even though this
675 * will be a value above 32-bits this is still done for
676 * CONFIG_X86_32 so that accurate values are reported.
677 */
678 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
679
680 if (IS_ENABLED(CONFIG_X86_32))
681 goto clear_all;
682
683 rdmsrl(MSR_K7_HWCR, msr);
684 if (!(msr & MSR_K7_HWCR_SMMLOCK))
685 goto clear_sev;
686
687 return;
688
689 clear_all:
690 setup_clear_cpu_cap(X86_FEATURE_SME);
691 clear_sev:
692 setup_clear_cpu_cap(X86_FEATURE_SEV);
693 setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
694 }
695 }
696
early_init_amd(struct cpuinfo_x86 * c)697 static void early_init_amd(struct cpuinfo_x86 *c)
698 {
699 u64 value;
700 u32 dummy;
701
702 early_init_amd_mc(c);
703
704 #ifdef CONFIG_X86_32
705 if (c->x86 == 6)
706 set_cpu_cap(c, X86_FEATURE_K7);
707 #endif
708
709 if (c->x86 >= 0xf)
710 set_cpu_cap(c, X86_FEATURE_K8);
711
712 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
713
714 /*
715 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
716 * with P/T states and does not stop in deep C-states
717 */
718 if (c->x86_power & (1 << 8)) {
719 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
720 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
721 }
722
723 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
724 if (c->x86_power & BIT(12))
725 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
726
727 #ifdef CONFIG_X86_64
728 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
729 #else
730 /* Set MTRR capability flag if appropriate */
731 if (c->x86 == 5)
732 if (c->x86_model == 13 || c->x86_model == 9 ||
733 (c->x86_model == 8 && c->x86_stepping >= 8))
734 set_cpu_cap(c, X86_FEATURE_K6_MTRR);
735 #endif
736 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
737 /*
738 * ApicID can always be treated as an 8-bit value for AMD APIC versions
739 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
740 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
741 * after 16h.
742 */
743 if (boot_cpu_has(X86_FEATURE_APIC)) {
744 if (c->x86 > 0x16)
745 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
746 else if (c->x86 >= 0xf) {
747 /* check CPU config space for extended APIC ID */
748 unsigned int val;
749
750 val = read_pci_config(0, 24, 0, 0x68);
751 if ((val >> 17 & 0x3) == 0x3)
752 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
753 }
754 }
755 #endif
756
757 /*
758 * This is only needed to tell the kernel whether to use VMCALL
759 * and VMMCALL. VMMCALL is never executed except under virt, so
760 * we can set it unconditionally.
761 */
762 set_cpu_cap(c, X86_FEATURE_VMMCALL);
763
764 /* F16h erratum 793, CVE-2013-6885 */
765 if (c->x86 == 0x16 && c->x86_model <= 0xf)
766 msr_set_bit(MSR_AMD64_LS_CFG, 15);
767
768 /*
769 * Check whether the machine is affected by erratum 400. This is
770 * used to select the proper idle routine and to enable the check
771 * whether the machine is affected in arch_post_acpi_init(), which
772 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
773 */
774 if (cpu_has_amd_erratum(c, amd_erratum_400))
775 set_cpu_bug(c, X86_BUG_AMD_E400);
776
777 early_detect_mem_encrypt(c);
778
779 /* Re-enable TopologyExtensions if switched off by BIOS */
780 if (c->x86 == 0x15 &&
781 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
782 !cpu_has(c, X86_FEATURE_TOPOEXT)) {
783
784 if (msr_set_bit(0xc0011005, 54) > 0) {
785 rdmsrl(0xc0011005, value);
786 if (value & BIT_64(54)) {
787 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
788 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
789 }
790 }
791 }
792
793 amd_get_topology_early(c);
794 }
795
init_amd_k8(struct cpuinfo_x86 * c)796 static void init_amd_k8(struct cpuinfo_x86 *c)
797 {
798 u32 level;
799 u64 value;
800
801 /* On C+ stepping K8 rep microcode works well for copy/memset */
802 level = cpuid_eax(1);
803 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
804 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
805
806 /*
807 * Some BIOSes incorrectly force this feature, but only K8 revision D
808 * (model = 0x14) and later actually support it.
809 * (AMD Erratum #110, docId: 25759).
810 */
811 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
812 clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
813 if (!rdmsrl_amd_safe(0xc001100d, &value)) {
814 value &= ~BIT_64(32);
815 wrmsrl_amd_safe(0xc001100d, value);
816 }
817 }
818
819 if (!c->x86_model_id[0])
820 strcpy(c->x86_model_id, "Hammer");
821
822 #ifdef CONFIG_SMP
823 /*
824 * Disable TLB flush filter by setting HWCR.FFDIS on K8
825 * bit 6 of msr C001_0015
826 *
827 * Errata 63 for SH-B3 steppings
828 * Errata 122 for all steppings (F+ have it disabled by default)
829 */
830 msr_set_bit(MSR_K7_HWCR, 6);
831 #endif
832 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
833 }
834
init_amd_gh(struct cpuinfo_x86 * c)835 static void init_amd_gh(struct cpuinfo_x86 *c)
836 {
837 #ifdef CONFIG_MMCONF_FAM10H
838 /* do this for boot cpu */
839 if (c == &boot_cpu_data)
840 check_enable_amd_mmconf_dmi();
841
842 fam10h_check_enable_mmcfg();
843 #endif
844
845 /*
846 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
847 * is always needed when GART is enabled, even in a kernel which has no
848 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
849 * If it doesn't, we do it here as suggested by the BKDG.
850 *
851 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
852 */
853 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
854
855 /*
856 * On family 10h BIOS may not have properly enabled WC+ support, causing
857 * it to be converted to CD memtype. This may result in performance
858 * degradation for certain nested-paging guests. Prevent this conversion
859 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
860 *
861 * NOTE: we want to use the _safe accessors so as not to #GP kvm
862 * guests on older kvm hosts.
863 */
864 msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
865
866 if (cpu_has_amd_erratum(c, amd_erratum_383))
867 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
868 }
869
init_amd_ln(struct cpuinfo_x86 * c)870 static void init_amd_ln(struct cpuinfo_x86 *c)
871 {
872 /*
873 * Apply erratum 665 fix unconditionally so machines without a BIOS
874 * fix work.
875 */
876 msr_set_bit(MSR_AMD64_DE_CFG, 31);
877 }
878
879 static bool rdrand_force;
880
rdrand_cmdline(char * str)881 static int __init rdrand_cmdline(char *str)
882 {
883 if (!str)
884 return -EINVAL;
885
886 if (!strcmp(str, "force"))
887 rdrand_force = true;
888 else
889 return -EINVAL;
890
891 return 0;
892 }
893 early_param("rdrand", rdrand_cmdline);
894
clear_rdrand_cpuid_bit(struct cpuinfo_x86 * c)895 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
896 {
897 /*
898 * Saving of the MSR used to hide the RDRAND support during
899 * suspend/resume is done by arch/x86/power/cpu.c, which is
900 * dependent on CONFIG_PM_SLEEP.
901 */
902 if (!IS_ENABLED(CONFIG_PM_SLEEP))
903 return;
904
905 /*
906 * The nordrand option can clear X86_FEATURE_RDRAND, so check for
907 * RDRAND support using the CPUID function directly.
908 */
909 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
910 return;
911
912 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
913
914 /*
915 * Verify that the CPUID change has occurred in case the kernel is
916 * running virtualized and the hypervisor doesn't support the MSR.
917 */
918 if (cpuid_ecx(1) & BIT(30)) {
919 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
920 return;
921 }
922
923 clear_cpu_cap(c, X86_FEATURE_RDRAND);
924 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
925 }
926
init_amd_jg(struct cpuinfo_x86 * c)927 static void init_amd_jg(struct cpuinfo_x86 *c)
928 {
929 /*
930 * Some BIOS implementations do not restore proper RDRAND support
931 * across suspend and resume. Check on whether to hide the RDRAND
932 * instruction support via CPUID.
933 */
934 clear_rdrand_cpuid_bit(c);
935 }
936
init_amd_bd(struct cpuinfo_x86 * c)937 static void init_amd_bd(struct cpuinfo_x86 *c)
938 {
939 u64 value;
940
941 /*
942 * The way access filter has a performance penalty on some workloads.
943 * Disable it on the affected CPUs.
944 */
945 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
946 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
947 value |= 0x1E;
948 wrmsrl_safe(MSR_F15H_IC_CFG, value);
949 }
950 }
951
952 /*
953 * Some BIOS implementations do not restore proper RDRAND support
954 * across suspend and resume. Check on whether to hide the RDRAND
955 * instruction support via CPUID.
956 */
957 clear_rdrand_cpuid_bit(c);
958 }
959
init_amd_zn(struct cpuinfo_x86 * c)960 static void init_amd_zn(struct cpuinfo_x86 *c)
961 {
962 set_cpu_cap(c, X86_FEATURE_ZEN);
963
964 #ifdef CONFIG_NUMA
965 node_reclaim_distance = 32;
966 #endif
967
968 /* Fix up CPUID bits, but only if not virtualised. */
969 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
970
971 /* Erratum 1076: CPB feature bit not being set in CPUID. */
972 if (!cpu_has(c, X86_FEATURE_CPB))
973 set_cpu_cap(c, X86_FEATURE_CPB);
974
975 /*
976 * Zen3 (Fam19 model < 0x10) parts are not susceptible to
977 * Branch Type Confusion, but predate the allocation of the
978 * BTC_NO bit.
979 */
980 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO))
981 set_cpu_cap(c, X86_FEATURE_BTC_NO);
982 }
983
984 /*
985 * Work around Erratum 1386. The XSAVES instruction malfunctions in
986 * certain circumstances on Zen1/2 uarch, and not all parts have had
987 * updated microcode at the time of writing (March 2023).
988 *
989 * Affected parts all have no supervisor XSAVE states, meaning that
990 * the XSAVEC instruction (which works fine) is equivalent.
991 */
992 if (c->x86 == 0x17)
993 clear_cpu_cap(c, X86_FEATURE_XSAVES);
994 }
995
cpu_has_zenbleed_microcode(void)996 static bool cpu_has_zenbleed_microcode(void)
997 {
998 u32 good_rev = 0;
999
1000 switch (boot_cpu_data.x86_model) {
1001 case 0x30 ... 0x3f: good_rev = 0x0830107b; break;
1002 case 0x60 ... 0x67: good_rev = 0x0860010c; break;
1003 case 0x68 ... 0x6f: good_rev = 0x08608107; break;
1004 case 0x70 ... 0x7f: good_rev = 0x08701033; break;
1005 case 0xa0 ... 0xaf: good_rev = 0x08a00009; break;
1006
1007 default:
1008 return false;
1009 break;
1010 }
1011
1012 if (boot_cpu_data.microcode < good_rev)
1013 return false;
1014
1015 return true;
1016 }
1017
zenbleed_check(struct cpuinfo_x86 * c)1018 static void zenbleed_check(struct cpuinfo_x86 *c)
1019 {
1020 if (!cpu_has_amd_erratum(c, amd_zenbleed))
1021 return;
1022
1023 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
1024 return;
1025
1026 if (!cpu_has(c, X86_FEATURE_AVX))
1027 return;
1028
1029 if (!cpu_has_zenbleed_microcode()) {
1030 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
1031 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1032 } else {
1033 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
1034 }
1035 }
1036
init_amd(struct cpuinfo_x86 * c)1037 static void init_amd(struct cpuinfo_x86 *c)
1038 {
1039 early_init_amd(c);
1040
1041 /*
1042 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
1043 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
1044 */
1045 clear_cpu_cap(c, 0*32+31);
1046
1047 if (c->x86 >= 0x10)
1048 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
1049
1050 /* get apicid instead of initial apic id from cpuid */
1051 c->apicid = hard_smp_processor_id();
1052
1053 /* K6s reports MCEs but don't actually have all the MSRs */
1054 if (c->x86 < 6)
1055 clear_cpu_cap(c, X86_FEATURE_MCE);
1056
1057 switch (c->x86) {
1058 case 4: init_amd_k5(c); break;
1059 case 5: init_amd_k6(c); break;
1060 case 6: init_amd_k7(c); break;
1061 case 0xf: init_amd_k8(c); break;
1062 case 0x10: init_amd_gh(c); break;
1063 case 0x12: init_amd_ln(c); break;
1064 case 0x15: init_amd_bd(c); break;
1065 case 0x16: init_amd_jg(c); break;
1066 case 0x17: init_amd_zn(c); break;
1067 }
1068
1069 /*
1070 * Enable workaround for FXSAVE leak on CPUs
1071 * without a XSaveErPtr feature
1072 */
1073 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
1074 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
1075
1076 cpu_detect_cache_sizes(c);
1077
1078 amd_detect_cmp(c);
1079 amd_get_topology(c);
1080 srat_detect_node(c);
1081
1082 init_amd_cacheinfo(c);
1083
1084 if (cpu_has(c, X86_FEATURE_XMM2)) {
1085 /*
1086 * Use LFENCE for execution serialization. On families which
1087 * don't have that MSR, LFENCE is already serializing.
1088 * msr_set_bit() uses the safe accessors, too, even if the MSR
1089 * is not present.
1090 */
1091 msr_set_bit(MSR_AMD64_DE_CFG,
1092 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
1093
1094 /* A serializing LFENCE stops RDTSC speculation */
1095 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
1096 }
1097
1098 /*
1099 * Family 0x12 and above processors have APIC timer
1100 * running in deep C states.
1101 */
1102 if (c->x86 > 0x11)
1103 set_cpu_cap(c, X86_FEATURE_ARAT);
1104
1105 /* 3DNow or LM implies PREFETCHW */
1106 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
1107 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
1108 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
1109
1110 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
1111 if (!cpu_has(c, X86_FEATURE_XENPV))
1112 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1113
1114 /*
1115 * Turn on the Instructions Retired free counter on machines not
1116 * susceptible to erratum #1054 "Instructions Retired Performance
1117 * Counter May Be Inaccurate".
1118 */
1119 if (cpu_has(c, X86_FEATURE_IRPERF) &&
1120 !cpu_has_amd_erratum(c, amd_erratum_1054))
1121 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
1122
1123 check_null_seg_clears_base(c);
1124
1125 zenbleed_check(c);
1126
1127 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
1128 cpu_has_amd_erratum(c, amd_erratum_1485))
1129 msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
1130 }
1131
1132 #ifdef CONFIG_X86_32
amd_size_cache(struct cpuinfo_x86 * c,unsigned int size)1133 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1134 {
1135 /* AMD errata T13 (order #21922) */
1136 if (c->x86 == 6) {
1137 /* Duron Rev A0 */
1138 if (c->x86_model == 3 && c->x86_stepping == 0)
1139 size = 64;
1140 /* Tbird rev A1/A2 */
1141 if (c->x86_model == 4 &&
1142 (c->x86_stepping == 0 || c->x86_stepping == 1))
1143 size = 256;
1144 }
1145 return size;
1146 }
1147 #endif
1148
cpu_detect_tlb_amd(struct cpuinfo_x86 * c)1149 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
1150 {
1151 u32 ebx, eax, ecx, edx;
1152 u16 mask = 0xfff;
1153
1154 if (c->x86 < 0xf)
1155 return;
1156
1157 if (c->extended_cpuid_level < 0x80000006)
1158 return;
1159
1160 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
1161
1162 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
1163 tlb_lli_4k[ENTRIES] = ebx & mask;
1164
1165 /*
1166 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
1167 * characteristics from the CPUID function 0x80000005 instead.
1168 */
1169 if (c->x86 == 0xf) {
1170 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1171 mask = 0xff;
1172 }
1173
1174 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1175 if (!((eax >> 16) & mask))
1176 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
1177 else
1178 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
1179
1180 /* a 4M entry uses two 2M entries */
1181 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
1182
1183 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
1184 if (!(eax & mask)) {
1185 /* Erratum 658 */
1186 if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
1187 tlb_lli_2m[ENTRIES] = 1024;
1188 } else {
1189 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
1190 tlb_lli_2m[ENTRIES] = eax & 0xff;
1191 }
1192 } else
1193 tlb_lli_2m[ENTRIES] = eax & mask;
1194
1195 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
1196 }
1197
1198 static const struct cpu_dev amd_cpu_dev = {
1199 .c_vendor = "AMD",
1200 .c_ident = { "AuthenticAMD" },
1201 #ifdef CONFIG_X86_32
1202 .legacy_models = {
1203 { .family = 4, .model_names =
1204 {
1205 [3] = "486 DX/2",
1206 [7] = "486 DX/2-WB",
1207 [8] = "486 DX/4",
1208 [9] = "486 DX/4-WB",
1209 [14] = "Am5x86-WT",
1210 [15] = "Am5x86-WB"
1211 }
1212 },
1213 },
1214 .legacy_cache_size = amd_size_cache,
1215 #endif
1216 .c_early_init = early_init_amd,
1217 .c_detect_tlb = cpu_detect_tlb_amd,
1218 .c_bsp_init = bsp_init_amd,
1219 .c_init = init_amd,
1220 .c_x86_vendor = X86_VENDOR_AMD,
1221 };
1222
1223 cpu_dev_register(amd_cpu_dev);
1224
set_dr_addr_mask(unsigned long mask,int dr)1225 void set_dr_addr_mask(unsigned long mask, int dr)
1226 {
1227 if (!boot_cpu_has(X86_FEATURE_BPEXT))
1228 return;
1229
1230 switch (dr) {
1231 case 0:
1232 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
1233 break;
1234 case 1:
1235 case 2:
1236 case 3:
1237 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
1238 break;
1239 default:
1240 break;
1241 }
1242 }
1243
zenbleed_check_cpu(void * unused)1244 static void zenbleed_check_cpu(void *unused)
1245 {
1246 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
1247
1248 zenbleed_check(c);
1249 }
1250
amd_check_microcode(void)1251 void amd_check_microcode(void)
1252 {
1253 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
1254 return;
1255
1256 on_each_cpu(zenbleed_check_cpu, NULL, 1);
1257 }
1258