1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Hygon Processor Support for Linux
4 *
5 * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd.
6 *
7 * Author: Pu Wen <puwen@hygon.cn>
8 */
9 #include <linux/io.h>
10
11 #include <asm/cpu.h>
12 #include <asm/smp.h>
13 #include <asm/cacheinfo.h>
14 #include <asm/spec-ctrl.h>
15 #include <asm/delay.h>
16 #ifdef CONFIG_X86_64
17 # include <asm/set_memory.h>
18 #endif
19
20 #include "cpu.h"
21
22 #define APICID_SOCKET_ID_BIT 6
23
24 /*
25 * nodes_per_socket: Stores the number of nodes per socket.
26 * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8]
27 */
28 static u32 nodes_per_socket = 1;
29
30 #ifdef CONFIG_NUMA
31 /*
32 * To workaround broken NUMA config. Read the comment in
33 * srat_detect_node().
34 */
nearby_node(int apicid)35 static int nearby_node(int apicid)
36 {
37 int i, node;
38
39 for (i = apicid - 1; i >= 0; i--) {
40 node = __apicid_to_node[i];
41 if (node != NUMA_NO_NODE && node_online(node))
42 return node;
43 }
44 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
45 node = __apicid_to_node[i];
46 if (node != NUMA_NO_NODE && node_online(node))
47 return node;
48 }
49 return first_node(node_online_map); /* Shouldn't happen */
50 }
51 #endif
52
hygon_get_topology_early(struct cpuinfo_x86 * c)53 static void hygon_get_topology_early(struct cpuinfo_x86 *c)
54 {
55 if (cpu_has(c, X86_FEATURE_TOPOEXT))
56 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
57 }
58
59 /*
60 * Fixup core topology information for
61 * (1) Hygon multi-node processors
62 * Assumption: Number of cores in each internal node is the same.
63 * (2) Hygon processors supporting compute units
64 */
hygon_get_topology(struct cpuinfo_x86 * c)65 static void hygon_get_topology(struct cpuinfo_x86 *c)
66 {
67 int cpu = smp_processor_id();
68
69 /* get information required for multi-node processors */
70 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
71 int err;
72 u32 eax, ebx, ecx, edx;
73
74 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
75
76 c->cpu_die_id = ecx & 0xff;
77
78 c->cpu_core_id = ebx & 0xff;
79
80 if (smp_num_siblings > 1)
81 c->x86_max_cores /= smp_num_siblings;
82
83 /*
84 * In case leaf B is available, use it to derive
85 * topology information.
86 */
87 err = detect_extended_topology(c);
88 if (!err)
89 c->x86_coreid_bits = get_count_order(c->x86_max_cores);
90
91 /*
92 * Socket ID is ApicId[6] for the processors with model <= 0x3
93 * when running on host.
94 */
95 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) && c->x86_model <= 0x3)
96 c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
97
98 cacheinfo_hygon_init_llc_id(c, cpu);
99 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
100 u64 value;
101
102 rdmsrl(MSR_FAM10H_NODE_ID, value);
103 c->cpu_die_id = value & 7;
104
105 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
106 } else
107 return;
108
109 if (nodes_per_socket > 1)
110 set_cpu_cap(c, X86_FEATURE_AMD_DCM);
111 }
112
113 /*
114 * On Hygon setup the lower bits of the APIC id distinguish the cores.
115 * Assumes number of cores is a power of two.
116 */
hygon_detect_cmp(struct cpuinfo_x86 * c)117 static void hygon_detect_cmp(struct cpuinfo_x86 *c)
118 {
119 unsigned int bits;
120 int cpu = smp_processor_id();
121
122 bits = c->x86_coreid_bits;
123 /* Low order bits define the core id (index of core in socket) */
124 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
125 /* Convert the initial APIC ID into the socket ID */
126 c->phys_proc_id = c->initial_apicid >> bits;
127 /* use socket ID also for last level cache */
128 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
129 }
130
srat_detect_node(struct cpuinfo_x86 * c)131 static void srat_detect_node(struct cpuinfo_x86 *c)
132 {
133 #ifdef CONFIG_NUMA
134 int cpu = smp_processor_id();
135 int node;
136 unsigned int apicid = c->apicid;
137
138 node = numa_cpu_node(cpu);
139 if (node == NUMA_NO_NODE)
140 node = per_cpu(cpu_llc_id, cpu);
141
142 /*
143 * On multi-fabric platform (e.g. Numascale NumaChip) a
144 * platform-specific handler needs to be called to fixup some
145 * IDs of the CPU.
146 */
147 if (x86_cpuinit.fixup_cpu_id)
148 x86_cpuinit.fixup_cpu_id(c, node);
149
150 if (!node_online(node)) {
151 /*
152 * Two possibilities here:
153 *
154 * - The CPU is missing memory and no node was created. In
155 * that case try picking one from a nearby CPU.
156 *
157 * - The APIC IDs differ from the HyperTransport node IDs.
158 * Assume they are all increased by a constant offset, but
159 * in the same order as the HT nodeids. If that doesn't
160 * result in a usable node fall back to the path for the
161 * previous case.
162 *
163 * This workaround operates directly on the mapping between
164 * APIC ID and NUMA node, assuming certain relationship
165 * between APIC ID, HT node ID and NUMA topology. As going
166 * through CPU mapping may alter the outcome, directly
167 * access __apicid_to_node[].
168 */
169 int ht_nodeid = c->initial_apicid;
170
171 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
172 node = __apicid_to_node[ht_nodeid];
173 /* Pick a nearby node */
174 if (!node_online(node))
175 node = nearby_node(apicid);
176 }
177 numa_set_node(cpu, node);
178 #endif
179 }
180
early_init_hygon_mc(struct cpuinfo_x86 * c)181 static void early_init_hygon_mc(struct cpuinfo_x86 *c)
182 {
183 #ifdef CONFIG_SMP
184 unsigned int bits, ecx;
185
186 /* Multi core CPU? */
187 if (c->extended_cpuid_level < 0x80000008)
188 return;
189
190 ecx = cpuid_ecx(0x80000008);
191
192 c->x86_max_cores = (ecx & 0xff) + 1;
193
194 /* CPU telling us the core id bits shift? */
195 bits = (ecx >> 12) & 0xF;
196
197 /* Otherwise recompute */
198 if (bits == 0) {
199 while ((1 << bits) < c->x86_max_cores)
200 bits++;
201 }
202
203 c->x86_coreid_bits = bits;
204 #endif
205 }
206
bsp_init_hygon(struct cpuinfo_x86 * c)207 static void bsp_init_hygon(struct cpuinfo_x86 *c)
208 {
209 #ifdef CONFIG_X86_64
210 unsigned long long tseg;
211
212 /*
213 * Split up direct mapping around the TSEG SMM area.
214 * Don't do it for gbpages because there seems very little
215 * benefit in doing so.
216 */
217 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
218 unsigned long pfn = tseg >> PAGE_SHIFT;
219
220 pr_debug("tseg: %010llx\n", tseg);
221 if (pfn_range_is_mapped(pfn, pfn + 1))
222 set_memory_4k((unsigned long)__va(tseg), 1);
223 }
224 #endif
225
226 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
227 u64 val;
228
229 rdmsrl(MSR_K7_HWCR, val);
230 if (!(val & BIT(24)))
231 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
232 }
233
234 if (cpu_has(c, X86_FEATURE_MWAITX))
235 use_mwaitx_delay();
236
237 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
238 u32 ecx;
239
240 ecx = cpuid_ecx(0x8000001e);
241 nodes_per_socket = ((ecx >> 8) & 7) + 1;
242 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
243 u64 value;
244
245 rdmsrl(MSR_FAM10H_NODE_ID, value);
246 nodes_per_socket = ((value >> 3) & 7) + 1;
247 }
248
249 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
250 !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) {
251 /*
252 * Try to cache the base value so further operations can
253 * avoid RMW. If that faults, do not enable SSBD.
254 */
255 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
256 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
257 setup_force_cpu_cap(X86_FEATURE_SSBD);
258 x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
259 }
260 }
261 }
262
early_init_hygon(struct cpuinfo_x86 * c)263 static void early_init_hygon(struct cpuinfo_x86 *c)
264 {
265 u32 dummy;
266
267 early_init_hygon_mc(c);
268
269 set_cpu_cap(c, X86_FEATURE_K8);
270
271 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
272
273 /*
274 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
275 * with P/T states and does not stop in deep C-states
276 */
277 if (c->x86_power & (1 << 8)) {
278 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
279 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
280 }
281
282 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
283 if (c->x86_power & BIT(12))
284 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
285
286 #ifdef CONFIG_X86_64
287 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
288 #endif
289
290 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
291 /*
292 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we
293 * can safely set X86_FEATURE_EXTD_APICID unconditionally.
294 */
295 if (boot_cpu_has(X86_FEATURE_APIC))
296 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
297 #endif
298
299 /*
300 * This is only needed to tell the kernel whether to use VMCALL
301 * and VMMCALL. VMMCALL is never executed except under virt, so
302 * we can set it unconditionally.
303 */
304 set_cpu_cap(c, X86_FEATURE_VMMCALL);
305
306 hygon_get_topology_early(c);
307 }
308
init_hygon(struct cpuinfo_x86 * c)309 static void init_hygon(struct cpuinfo_x86 *c)
310 {
311 early_init_hygon(c);
312
313 /*
314 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
315 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
316 */
317 clear_cpu_cap(c, 0*32+31);
318
319 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
320
321 /* get apicid instead of initial apic id from cpuid */
322 c->apicid = hard_smp_processor_id();
323
324 set_cpu_cap(c, X86_FEATURE_ZEN);
325 set_cpu_cap(c, X86_FEATURE_CPB);
326
327 cpu_detect_cache_sizes(c);
328
329 hygon_detect_cmp(c);
330 hygon_get_topology(c);
331 srat_detect_node(c);
332
333 init_hygon_cacheinfo(c);
334
335 if (cpu_has(c, X86_FEATURE_XMM2)) {
336 /*
337 * Use LFENCE for execution serialization. On families which
338 * don't have that MSR, LFENCE is already serializing.
339 * msr_set_bit() uses the safe accessors, too, even if the MSR
340 * is not present.
341 */
342 msr_set_bit(MSR_AMD64_DE_CFG,
343 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
344
345 /* A serializing LFENCE stops RDTSC speculation */
346 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
347 }
348
349 /*
350 * Hygon processors have APIC timer running in deep C states.
351 */
352 set_cpu_cap(c, X86_FEATURE_ARAT);
353
354 /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */
355 if (!cpu_has(c, X86_FEATURE_XENPV))
356 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
357
358 check_null_seg_clears_base(c);
359 }
360
cpu_detect_tlb_hygon(struct cpuinfo_x86 * c)361 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
362 {
363 u32 ebx, eax, ecx, edx;
364 u16 mask = 0xfff;
365
366 if (c->extended_cpuid_level < 0x80000006)
367 return;
368
369 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
370
371 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
372 tlb_lli_4k[ENTRIES] = ebx & mask;
373
374 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
375 if (!((eax >> 16) & mask))
376 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
377 else
378 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
379
380 /* a 4M entry uses two 2M entries */
381 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
382
383 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
384 if (!(eax & mask)) {
385 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
386 tlb_lli_2m[ENTRIES] = eax & 0xff;
387 } else
388 tlb_lli_2m[ENTRIES] = eax & mask;
389
390 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
391 }
392
393 static const struct cpu_dev hygon_cpu_dev = {
394 .c_vendor = "Hygon",
395 .c_ident = { "HygonGenuine" },
396 .c_early_init = early_init_hygon,
397 .c_detect_tlb = cpu_detect_tlb_hygon,
398 .c_bsp_init = bsp_init_hygon,
399 .c_init = init_hygon,
400 .c_x86_vendor = X86_VENDOR_HYGON,
401 };
402
403 cpu_dev_register(hygon_cpu_dev);
404