1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3
4 #include <linux/string.h>
5 #include <linux/bitops.h>
6 #include <linux/smp.h>
7 #include <linux/sched.h>
8 #include <linux/sched/clock.h>
9 #include <linux/thread_info.h>
10 #include <linux/init.h>
11 #include <linux/uaccess.h>
12
13 #include <asm/cpufeature.h>
14 #include <asm/pgtable.h>
15 #include <asm/msr.h>
16 #include <asm/bugs.h>
17 #include <asm/cpu.h>
18 #include <asm/intel-family.h>
19 #include <asm/microcode_intel.h>
20 #include <asm/hwcap2.h>
21 #include <asm/elf.h>
22
23 #ifdef CONFIG_X86_64
24 #include <linux/topology.h>
25 #endif
26
27 #include "cpu.h"
28
29 #ifdef CONFIG_X86_LOCAL_APIC
30 #include <asm/mpspec.h>
31 #include <asm/apic.h>
32 #endif
33
34 /*
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
37 */
38 static int forcempx;
39
forcempx_setup(char * __unused)40 static int __init forcempx_setup(char *__unused)
41 {
42 forcempx = 1;
43
44 return 1;
45 }
46 __setup("intel-skd-046-workaround=disable", forcempx_setup);
47
check_mpx_erratum(struct cpuinfo_x86 * c)48 void check_mpx_erratum(struct cpuinfo_x86 *c)
49 {
50 if (forcempx)
51 return;
52 /*
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
55 *
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
58 *
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
62 */
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
66 }
67 }
68
69 /*
70 * Processors which have self-snooping capability can handle conflicting
71 * memory type across CPUs by snooping its own cache. However, there exists
72 * CPU models in which having conflicting memory types still leads to
73 * unpredictable behavior, machine check errors, or hangs. Clear this
74 * feature to prevent its use on machines with known erratas.
75 */
check_memory_type_self_snoop_errata(struct cpuinfo_x86 * c)76 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
77 {
78 switch (c->x86_model) {
79 case INTEL_FAM6_CORE_YONAH:
80 case INTEL_FAM6_CORE2_MEROM:
81 case INTEL_FAM6_CORE2_MEROM_L:
82 case INTEL_FAM6_CORE2_PENRYN:
83 case INTEL_FAM6_CORE2_DUNNINGTON:
84 case INTEL_FAM6_NEHALEM:
85 case INTEL_FAM6_NEHALEM_G:
86 case INTEL_FAM6_NEHALEM_EP:
87 case INTEL_FAM6_NEHALEM_EX:
88 case INTEL_FAM6_WESTMERE:
89 case INTEL_FAM6_WESTMERE_EP:
90 case INTEL_FAM6_SANDYBRIDGE:
91 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
92 }
93 }
94
95 static bool ring3mwait_disabled __read_mostly;
96
ring3mwait_disable(char * __unused)97 static int __init ring3mwait_disable(char *__unused)
98 {
99 ring3mwait_disabled = true;
100 return 1;
101 }
102 __setup("ring3mwait=disable", ring3mwait_disable);
103
probe_xeon_phi_r3mwait(struct cpuinfo_x86 * c)104 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
105 {
106 /*
107 * Ring 3 MONITOR/MWAIT feature cannot be detected without
108 * cpu model and family comparison.
109 */
110 if (c->x86 != 6)
111 return;
112 switch (c->x86_model) {
113 case INTEL_FAM6_XEON_PHI_KNL:
114 case INTEL_FAM6_XEON_PHI_KNM:
115 break;
116 default:
117 return;
118 }
119
120 if (ring3mwait_disabled)
121 return;
122
123 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
124 this_cpu_or(msr_misc_features_shadow,
125 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
126
127 if (c == &boot_cpu_data)
128 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
129 }
130
131 /*
132 * Early microcode releases for the Spectre v2 mitigation were broken.
133 * Information taken from;
134 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
135 * - https://kb.vmware.com/s/article/52345
136 * - Microcode revisions observed in the wild
137 * - Release note from 20180108 microcode release
138 */
139 struct sku_microcode {
140 u8 model;
141 u8 stepping;
142 u32 microcode;
143 };
144 static const struct sku_microcode spectre_bad_microcodes[] = {
145 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
146 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
147 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
148 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
149 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
150 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
151 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
152 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
153 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
154 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
155 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
156 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
157 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
158 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
159 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
160 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
161 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
162 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
163 /* Observed in the wild */
164 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
165 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
166 };
167
bad_spectre_microcode(struct cpuinfo_x86 * c)168 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
169 {
170 int i;
171
172 /*
173 * We know that the hypervisor lie to us on the microcode version so
174 * we may as well hope that it is running the correct version.
175 */
176 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
177 return false;
178
179 if (c->x86 != 6)
180 return false;
181
182 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
183 if (c->x86_model == spectre_bad_microcodes[i].model &&
184 c->x86_stepping == spectre_bad_microcodes[i].stepping)
185 return (c->microcode <= spectre_bad_microcodes[i].microcode);
186 }
187 return false;
188 }
189
190 #define MSR_IA32_TME_ACTIVATE 0x982
191
192 /* Helpers to access TME_ACTIVATE MSR */
193 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
194 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
195
196 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
197 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
198
199 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
200
201 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
202 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
203
204 /* Values for mktme_status (SW only construct) */
205 #define MKTME_ENABLED 0
206 #define MKTME_DISABLED 1
207 #define MKTME_UNINITIALIZED 2
208 static int mktme_status = MKTME_UNINITIALIZED;
209
detect_tme_early(struct cpuinfo_x86 * c)210 static void detect_tme_early(struct cpuinfo_x86 *c)
211 {
212 u64 tme_activate, tme_policy, tme_crypto_algs;
213 int keyid_bits = 0, nr_keyids = 0;
214 static u64 tme_activate_cpu0 = 0;
215
216 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
217
218 if (mktme_status != MKTME_UNINITIALIZED) {
219 if (tme_activate != tme_activate_cpu0) {
220 /* Broken BIOS? */
221 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
222 pr_err_once("x86/tme: MKTME is not usable\n");
223 mktme_status = MKTME_DISABLED;
224
225 /* Proceed. We may need to exclude bits from x86_phys_bits. */
226 }
227 } else {
228 tme_activate_cpu0 = tme_activate;
229 }
230
231 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
232 pr_info_once("x86/tme: not enabled by BIOS\n");
233 mktme_status = MKTME_DISABLED;
234 return;
235 }
236
237 if (mktme_status != MKTME_UNINITIALIZED)
238 goto detect_keyid_bits;
239
240 pr_info("x86/tme: enabled by BIOS\n");
241
242 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
243 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
244 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
245
246 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
247 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
248 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
249 tme_crypto_algs);
250 mktme_status = MKTME_DISABLED;
251 }
252 detect_keyid_bits:
253 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
254 nr_keyids = (1UL << keyid_bits) - 1;
255 if (nr_keyids) {
256 pr_info_once("x86/mktme: enabled by BIOS\n");
257 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
258 } else {
259 pr_info_once("x86/mktme: disabled by BIOS\n");
260 }
261
262 if (mktme_status == MKTME_UNINITIALIZED) {
263 /* MKTME is usable */
264 mktme_status = MKTME_ENABLED;
265 }
266
267 /*
268 * KeyID bits effectively lower the number of physical address
269 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
270 */
271 c->x86_phys_bits -= keyid_bits;
272 }
273
early_init_intel(struct cpuinfo_x86 * c)274 static void early_init_intel(struct cpuinfo_x86 *c)
275 {
276 u64 misc_enable;
277
278 /* Unmask CPUID levels if masked: */
279 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
280 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
281 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
282 c->cpuid_level = cpuid_eax(0);
283 get_cpu_cap(c);
284 }
285 }
286
287 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
288 (c->x86 == 0x6 && c->x86_model >= 0x0e))
289 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
290
291 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
292 c->microcode = intel_get_microcode_revision();
293
294 /* Now if any of them are set, check the blacklist and clear the lot */
295 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
296 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
297 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
298 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
299 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
300 setup_clear_cpu_cap(X86_FEATURE_IBRS);
301 setup_clear_cpu_cap(X86_FEATURE_IBPB);
302 setup_clear_cpu_cap(X86_FEATURE_STIBP);
303 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
304 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
305 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
306 setup_clear_cpu_cap(X86_FEATURE_SSBD);
307 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
308 }
309
310 /*
311 * Atom erratum AAE44/AAF40/AAG38/AAH41:
312 *
313 * A race condition between speculative fetches and invalidating
314 * a large page. This is worked around in microcode, but we
315 * need the microcode to have already been loaded... so if it is
316 * not, recommend a BIOS update and disable large pages.
317 */
318 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
319 c->microcode < 0x20e) {
320 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
321 clear_cpu_cap(c, X86_FEATURE_PSE);
322 }
323
324 #ifdef CONFIG_X86_64
325 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
326 #else
327 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
328 if (c->x86 == 15 && c->x86_cache_alignment == 64)
329 c->x86_cache_alignment = 128;
330 #endif
331
332 /* CPUID workaround for 0F33/0F34 CPU */
333 if (c->x86 == 0xF && c->x86_model == 0x3
334 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
335 c->x86_phys_bits = 36;
336
337 /*
338 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
339 * with P/T states and does not stop in deep C-states.
340 *
341 * It is also reliable across cores and sockets. (but not across
342 * cabinets - we turn it off in that case explicitly.)
343 */
344 if (c->x86_power & (1 << 8)) {
345 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
346 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
347 }
348
349 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
350 if (c->x86 == 6) {
351 switch (c->x86_model) {
352 case INTEL_FAM6_ATOM_SALTWELL_MID:
353 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
354 case INTEL_FAM6_ATOM_SILVERMONT_MID:
355 case INTEL_FAM6_ATOM_AIRMONT_NP:
356 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
357 break;
358 default:
359 break;
360 }
361 }
362
363 /*
364 * There is a known erratum on Pentium III and Core Solo
365 * and Core Duo CPUs.
366 * " Page with PAT set to WC while associated MTRR is UC
367 * may consolidate to UC "
368 * Because of this erratum, it is better to stick with
369 * setting WC in MTRR rather than using PAT on these CPUs.
370 *
371 * Enable PAT WC only on P4, Core 2 or later CPUs.
372 */
373 if (c->x86 == 6 && c->x86_model < 15)
374 clear_cpu_cap(c, X86_FEATURE_PAT);
375
376 /*
377 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
378 * clear the fast string and enhanced fast string CPU capabilities.
379 */
380 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
381 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
382 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
383 pr_info("Disabled fast string operations\n");
384 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
385 setup_clear_cpu_cap(X86_FEATURE_ERMS);
386 }
387 }
388
389 /*
390 * Intel Quark Core DevMan_001.pdf section 6.4.11
391 * "The operating system also is required to invalidate (i.e., flush)
392 * the TLB when any changes are made to any of the page table entries.
393 * The operating system must reload CR3 to cause the TLB to be flushed"
394 *
395 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
396 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
397 * to be modified.
398 */
399 if (c->x86 == 5 && c->x86_model == 9) {
400 pr_info("Disabling PGE capability bit\n");
401 setup_clear_cpu_cap(X86_FEATURE_PGE);
402 }
403
404 if (c->cpuid_level >= 0x00000001) {
405 u32 eax, ebx, ecx, edx;
406
407 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
408 /*
409 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
410 * apicids which are reserved per package. Store the resulting
411 * shift value for the package management code.
412 */
413 if (edx & (1U << 28))
414 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
415 }
416
417 check_mpx_erratum(c);
418 check_memory_type_self_snoop_errata(c);
419
420 /*
421 * Get the number of SMT siblings early from the extended topology
422 * leaf, if available. Otherwise try the legacy SMT detection.
423 */
424 if (detect_extended_topology_early(c) < 0)
425 detect_ht_early(c);
426
427 /*
428 * Adjust the number of physical bits early because it affects the
429 * valid bits of the MTRR mask registers.
430 */
431 if (cpu_has(c, X86_FEATURE_TME))
432 detect_tme_early(c);
433 }
434
435 #ifdef CONFIG_X86_32
436 /*
437 * Early probe support logic for ppro memory erratum #50
438 *
439 * This is called before we do cpu ident work
440 */
441
ppro_with_ram_bug(void)442 int ppro_with_ram_bug(void)
443 {
444 /* Uses data from early_cpu_detect now */
445 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
446 boot_cpu_data.x86 == 6 &&
447 boot_cpu_data.x86_model == 1 &&
448 boot_cpu_data.x86_stepping < 8) {
449 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
450 return 1;
451 }
452 return 0;
453 }
454
intel_smp_check(struct cpuinfo_x86 * c)455 static void intel_smp_check(struct cpuinfo_x86 *c)
456 {
457 /* calling is from identify_secondary_cpu() ? */
458 if (!c->cpu_index)
459 return;
460
461 /*
462 * Mask B, Pentium, but not Pentium MMX
463 */
464 if (c->x86 == 5 &&
465 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
466 c->x86_model <= 3) {
467 /*
468 * Remember we have B step Pentia with bugs
469 */
470 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
471 "with B stepping processors.\n");
472 }
473 }
474
475 static int forcepae;
forcepae_setup(char * __unused)476 static int __init forcepae_setup(char *__unused)
477 {
478 forcepae = 1;
479 return 1;
480 }
481 __setup("forcepae", forcepae_setup);
482
intel_workarounds(struct cpuinfo_x86 * c)483 static void intel_workarounds(struct cpuinfo_x86 *c)
484 {
485 #ifdef CONFIG_X86_F00F_BUG
486 /*
487 * All models of Pentium and Pentium with MMX technology CPUs
488 * have the F0 0F bug, which lets nonprivileged users lock up the
489 * system. Announce that the fault handler will be checking for it.
490 * The Quark is also family 5, but does not have the same bug.
491 */
492 clear_cpu_bug(c, X86_BUG_F00F);
493 if (c->x86 == 5 && c->x86_model < 9) {
494 static int f00f_workaround_enabled;
495
496 set_cpu_bug(c, X86_BUG_F00F);
497 if (!f00f_workaround_enabled) {
498 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
499 f00f_workaround_enabled = 1;
500 }
501 }
502 #endif
503
504 /*
505 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
506 * model 3 mask 3
507 */
508 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
509 clear_cpu_cap(c, X86_FEATURE_SEP);
510
511 /*
512 * PAE CPUID issue: many Pentium M report no PAE but may have a
513 * functionally usable PAE implementation.
514 * Forcefully enable PAE if kernel parameter "forcepae" is present.
515 */
516 if (forcepae) {
517 pr_warn("PAE forced!\n");
518 set_cpu_cap(c, X86_FEATURE_PAE);
519 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
520 }
521
522 /*
523 * P4 Xeon erratum 037 workaround.
524 * Hardware prefetcher may cause stale data to be loaded into the cache.
525 */
526 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
527 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
528 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
529 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
530 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
531 }
532 }
533
534 /*
535 * See if we have a good local APIC by checking for buggy Pentia,
536 * i.e. all B steppings and the C2 stepping of P54C when using their
537 * integrated APIC (see 11AP erratum in "Pentium Processor
538 * Specification Update").
539 */
540 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
541 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
542 set_cpu_bug(c, X86_BUG_11AP);
543
544
545 #ifdef CONFIG_X86_INTEL_USERCOPY
546 /*
547 * Set up the preferred alignment for movsl bulk memory moves
548 */
549 switch (c->x86) {
550 case 4: /* 486: untested */
551 break;
552 case 5: /* Old Pentia: untested */
553 break;
554 case 6: /* PII/PIII only like movsl with 8-byte alignment */
555 movsl_mask.mask = 7;
556 break;
557 case 15: /* P4 is OK down to 8-byte alignment */
558 movsl_mask.mask = 7;
559 break;
560 }
561 #endif
562
563 intel_smp_check(c);
564 }
565 #else
intel_workarounds(struct cpuinfo_x86 * c)566 static void intel_workarounds(struct cpuinfo_x86 *c)
567 {
568 }
569 #endif
570
srat_detect_node(struct cpuinfo_x86 * c)571 static void srat_detect_node(struct cpuinfo_x86 *c)
572 {
573 #ifdef CONFIG_NUMA
574 unsigned node;
575 int cpu = smp_processor_id();
576
577 /* Don't do the funky fallback heuristics the AMD version employs
578 for now. */
579 node = numa_cpu_node(cpu);
580 if (node == NUMA_NO_NODE || !node_online(node)) {
581 /* reuse the value from init_cpu_to_node() */
582 node = cpu_to_node(cpu);
583 }
584 numa_set_node(cpu, node);
585 #endif
586 }
587
detect_vmx_virtcap(struct cpuinfo_x86 * c)588 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
589 {
590 /* Intel VMX MSR indicated features */
591 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
592 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
593 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
594 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
595 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
596 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
597 #define x86_VMX_FEATURE_EPT_CAP_AD 0x00200000
598
599 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
600 u32 msr_vpid_cap, msr_ept_cap;
601
602 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
603 clear_cpu_cap(c, X86_FEATURE_VNMI);
604 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
605 clear_cpu_cap(c, X86_FEATURE_EPT);
606 clear_cpu_cap(c, X86_FEATURE_VPID);
607 clear_cpu_cap(c, X86_FEATURE_EPT_AD);
608
609 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
610 msr_ctl = vmx_msr_high | vmx_msr_low;
611 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
612 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
613 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
614 set_cpu_cap(c, X86_FEATURE_VNMI);
615 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
616 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
617 vmx_msr_low, vmx_msr_high);
618 msr_ctl2 = vmx_msr_high | vmx_msr_low;
619 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
620 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
621 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
622 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) {
623 set_cpu_cap(c, X86_FEATURE_EPT);
624 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
625 msr_ept_cap, msr_vpid_cap);
626 if (msr_ept_cap & x86_VMX_FEATURE_EPT_CAP_AD)
627 set_cpu_cap(c, X86_FEATURE_EPT_AD);
628 }
629 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
630 set_cpu_cap(c, X86_FEATURE_VPID);
631 }
632 }
633
init_cpuid_fault(struct cpuinfo_x86 * c)634 static void init_cpuid_fault(struct cpuinfo_x86 *c)
635 {
636 u64 msr;
637
638 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
639 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
640 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
641 }
642 }
643
init_intel_misc_features(struct cpuinfo_x86 * c)644 static void init_intel_misc_features(struct cpuinfo_x86 *c)
645 {
646 u64 msr;
647
648 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
649 return;
650
651 /* Clear all MISC features */
652 this_cpu_write(msr_misc_features_shadow, 0);
653
654 /* Check features and update capabilities and shadow control bits */
655 init_cpuid_fault(c);
656 probe_xeon_phi_r3mwait(c);
657
658 msr = this_cpu_read(msr_misc_features_shadow);
659 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
660 }
661
init_intel(struct cpuinfo_x86 * c)662 static void init_intel(struct cpuinfo_x86 *c)
663 {
664 early_init_intel(c);
665
666 intel_workarounds(c);
667
668 /*
669 * Detect the extended topology information if available. This
670 * will reinitialise the initial_apicid which will be used
671 * in init_intel_cacheinfo()
672 */
673 detect_extended_topology(c);
674
675 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
676 /*
677 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
678 * detection.
679 */
680 detect_num_cpu_cores(c);
681 #ifdef CONFIG_X86_32
682 detect_ht(c);
683 #endif
684 }
685
686 init_intel_cacheinfo(c);
687
688 if (c->cpuid_level > 9) {
689 unsigned eax = cpuid_eax(10);
690 /* Check for version and the number of counters */
691 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
692 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
693 }
694
695 if (cpu_has(c, X86_FEATURE_XMM2))
696 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
697
698 if (boot_cpu_has(X86_FEATURE_DS)) {
699 unsigned int l1, l2;
700
701 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
702 if (!(l1 & (1<<11)))
703 set_cpu_cap(c, X86_FEATURE_BTS);
704 if (!(l1 & (1<<12)))
705 set_cpu_cap(c, X86_FEATURE_PEBS);
706 }
707
708 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
709 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
710 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
711
712 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
713 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
714 set_cpu_bug(c, X86_BUG_MONITOR);
715
716 #ifdef CONFIG_X86_64
717 if (c->x86 == 15)
718 c->x86_cache_alignment = c->x86_clflush_size * 2;
719 if (c->x86 == 6)
720 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
721 #else
722 /*
723 * Names for the Pentium II/Celeron processors
724 * detectable only by also checking the cache size.
725 * Dixon is NOT a Celeron.
726 */
727 if (c->x86 == 6) {
728 unsigned int l2 = c->x86_cache_size;
729 char *p = NULL;
730
731 switch (c->x86_model) {
732 case 5:
733 if (l2 == 0)
734 p = "Celeron (Covington)";
735 else if (l2 == 256)
736 p = "Mobile Pentium II (Dixon)";
737 break;
738
739 case 6:
740 if (l2 == 128)
741 p = "Celeron (Mendocino)";
742 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
743 p = "Celeron-A";
744 break;
745
746 case 8:
747 if (l2 == 128)
748 p = "Celeron (Coppermine)";
749 break;
750 }
751
752 if (p)
753 strcpy(c->x86_model_id, p);
754 }
755
756 if (c->x86 == 15)
757 set_cpu_cap(c, X86_FEATURE_P4);
758 if (c->x86 == 6)
759 set_cpu_cap(c, X86_FEATURE_P3);
760 #endif
761
762 /* Work around errata */
763 srat_detect_node(c);
764
765 if (cpu_has(c, X86_FEATURE_VMX))
766 detect_vmx_virtcap(c);
767
768 init_intel_misc_features(c);
769
770 if (tsx_ctrl_state == TSX_CTRL_ENABLE)
771 tsx_enable();
772 if (tsx_ctrl_state == TSX_CTRL_DISABLE)
773 tsx_disable();
774 }
775
776 #ifdef CONFIG_X86_32
intel_size_cache(struct cpuinfo_x86 * c,unsigned int size)777 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
778 {
779 /*
780 * Intel PIII Tualatin. This comes in two flavours.
781 * One has 256kb of cache, the other 512. We have no way
782 * to determine which, so we use a boottime override
783 * for the 512kb model, and assume 256 otherwise.
784 */
785 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
786 size = 256;
787
788 /*
789 * Intel Quark SoC X1000 contains a 4-way set associative
790 * 16K cache with a 16 byte cache line and 256 lines per tag
791 */
792 if ((c->x86 == 5) && (c->x86_model == 9))
793 size = 16;
794 return size;
795 }
796 #endif
797
798 #define TLB_INST_4K 0x01
799 #define TLB_INST_4M 0x02
800 #define TLB_INST_2M_4M 0x03
801
802 #define TLB_INST_ALL 0x05
803 #define TLB_INST_1G 0x06
804
805 #define TLB_DATA_4K 0x11
806 #define TLB_DATA_4M 0x12
807 #define TLB_DATA_2M_4M 0x13
808 #define TLB_DATA_4K_4M 0x14
809
810 #define TLB_DATA_1G 0x16
811
812 #define TLB_DATA0_4K 0x21
813 #define TLB_DATA0_4M 0x22
814 #define TLB_DATA0_2M_4M 0x23
815
816 #define STLB_4K 0x41
817 #define STLB_4K_2M 0x42
818
819 static const struct _tlb_table intel_tlb_table[] = {
820 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
821 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
822 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
823 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
824 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
825 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
826 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
827 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
828 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
829 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
830 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
831 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
832 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
833 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
834 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
835 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
836 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
837 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
838 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
839 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
840 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
841 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
842 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
843 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
844 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
845 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
846 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
847 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
848 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
849 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
850 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
851 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
852 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
853 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
854 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
855 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
856 { 0x00, 0, 0 }
857 };
858
intel_tlb_lookup(const unsigned char desc)859 static void intel_tlb_lookup(const unsigned char desc)
860 {
861 unsigned char k;
862 if (desc == 0)
863 return;
864
865 /* look up this descriptor in the table */
866 for (k = 0; intel_tlb_table[k].descriptor != desc && \
867 intel_tlb_table[k].descriptor != 0; k++)
868 ;
869
870 if (intel_tlb_table[k].tlb_type == 0)
871 return;
872
873 switch (intel_tlb_table[k].tlb_type) {
874 case STLB_4K:
875 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
876 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
877 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
878 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
879 break;
880 case STLB_4K_2M:
881 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
882 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
883 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
884 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
885 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
886 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
887 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
888 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
889 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
890 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
891 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
892 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
893 break;
894 case TLB_INST_ALL:
895 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
896 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
897 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
898 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
899 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
900 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
901 break;
902 case TLB_INST_4K:
903 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
904 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
905 break;
906 case TLB_INST_4M:
907 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
908 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
909 break;
910 case TLB_INST_2M_4M:
911 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
912 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
913 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
914 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
915 break;
916 case TLB_DATA_4K:
917 case TLB_DATA0_4K:
918 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
919 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
920 break;
921 case TLB_DATA_4M:
922 case TLB_DATA0_4M:
923 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
924 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
925 break;
926 case TLB_DATA_2M_4M:
927 case TLB_DATA0_2M_4M:
928 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
929 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
930 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
931 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
932 break;
933 case TLB_DATA_4K_4M:
934 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
935 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
936 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
937 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
938 break;
939 case TLB_DATA_1G:
940 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
941 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
942 break;
943 }
944 }
945
intel_detect_tlb(struct cpuinfo_x86 * c)946 static void intel_detect_tlb(struct cpuinfo_x86 *c)
947 {
948 int i, j, n;
949 unsigned int regs[4];
950 unsigned char *desc = (unsigned char *)regs;
951
952 if (c->cpuid_level < 2)
953 return;
954
955 /* Number of times to iterate */
956 n = cpuid_eax(2) & 0xFF;
957
958 for (i = 0 ; i < n ; i++) {
959 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
960
961 /* If bit 31 is set, this is an unknown format */
962 for (j = 0 ; j < 3 ; j++)
963 if (regs[j] & (1 << 31))
964 regs[j] = 0;
965
966 /* Byte 0 is level count, not a descriptor */
967 for (j = 1 ; j < 16 ; j++)
968 intel_tlb_lookup(desc[j]);
969 }
970 }
971
972 static const struct cpu_dev intel_cpu_dev = {
973 .c_vendor = "Intel",
974 .c_ident = { "GenuineIntel" },
975 #ifdef CONFIG_X86_32
976 .legacy_models = {
977 { .family = 4, .model_names =
978 {
979 [0] = "486 DX-25/33",
980 [1] = "486 DX-50",
981 [2] = "486 SX",
982 [3] = "486 DX/2",
983 [4] = "486 SL",
984 [5] = "486 SX/2",
985 [7] = "486 DX/2-WB",
986 [8] = "486 DX/4",
987 [9] = "486 DX/4-WB"
988 }
989 },
990 { .family = 5, .model_names =
991 {
992 [0] = "Pentium 60/66 A-step",
993 [1] = "Pentium 60/66",
994 [2] = "Pentium 75 - 200",
995 [3] = "OverDrive PODP5V83",
996 [4] = "Pentium MMX",
997 [7] = "Mobile Pentium 75 - 200",
998 [8] = "Mobile Pentium MMX",
999 [9] = "Quark SoC X1000",
1000 }
1001 },
1002 { .family = 6, .model_names =
1003 {
1004 [0] = "Pentium Pro A-step",
1005 [1] = "Pentium Pro",
1006 [3] = "Pentium II (Klamath)",
1007 [4] = "Pentium II (Deschutes)",
1008 [5] = "Pentium II (Deschutes)",
1009 [6] = "Mobile Pentium II",
1010 [7] = "Pentium III (Katmai)",
1011 [8] = "Pentium III (Coppermine)",
1012 [10] = "Pentium III (Cascades)",
1013 [11] = "Pentium III (Tualatin)",
1014 }
1015 },
1016 { .family = 15, .model_names =
1017 {
1018 [0] = "Pentium 4 (Unknown)",
1019 [1] = "Pentium 4 (Willamette)",
1020 [2] = "Pentium 4 (Northwood)",
1021 [4] = "Pentium 4 (Foster)",
1022 [5] = "Pentium 4 (Foster)",
1023 }
1024 },
1025 },
1026 .legacy_cache_size = intel_size_cache,
1027 #endif
1028 .c_detect_tlb = intel_detect_tlb,
1029 .c_early_init = early_init_intel,
1030 .c_init = init_intel,
1031 .c_x86_vendor = X86_VENDOR_INTEL,
1032 };
1033
1034 cpu_dev_register(intel_cpu_dev);
1035