1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
7 *
8 * MMU support
9 *
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 *
13 * Authors:
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
16 */
17
18 /*
19 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
20 * so the code in this file is compiled twice, once per pte size.
21 */
22
23 #if PTTYPE == 64
24 #define pt_element_t u64
25 #define guest_walker guest_walker64
26 #define FNAME(name) paging##64_##name
27 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
28 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
29 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
30 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
31 #define PT_LEVEL_BITS PT64_LEVEL_BITS
32 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
33 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
34 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
37 #define CMPXCHG "cmpxchgq"
38 #else
39 #define PT_MAX_FULL_LEVELS 2
40 #endif
41 #elif PTTYPE == 32
42 #define pt_element_t u32
43 #define guest_walker guest_walker32
44 #define FNAME(name) paging##32_##name
45 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
46 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
47 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
48 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
49 #define PT_LEVEL_BITS PT32_LEVEL_BITS
50 #define PT_MAX_FULL_LEVELS 2
51 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
52 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
53 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
54 #define CMPXCHG "cmpxchgl"
55 #elif PTTYPE == PTTYPE_EPT
56 #define pt_element_t u64
57 #define guest_walker guest_walkerEPT
58 #define FNAME(name) ept_##name
59 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
60 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
61 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
62 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
63 #define PT_LEVEL_BITS PT64_LEVEL_BITS
64 #define PT_GUEST_DIRTY_SHIFT 9
65 #define PT_GUEST_ACCESSED_SHIFT 8
66 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
67 #define PT_MAX_FULL_LEVELS 4
68 #ifdef CONFIG_X86_64
69 #define CMPXCHG "cmpxchgq"
70 #endif
71 #else
72 #error Invalid PTTYPE value
73 #endif
74
75 #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
76 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
77
78 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
79 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
80
81 /*
82 * The guest_walker structure emulates the behavior of the hardware page
83 * table walker.
84 */
85 struct guest_walker {
86 int level;
87 unsigned max_level;
88 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
89 pt_element_t ptes[PT_MAX_FULL_LEVELS];
90 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
91 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
92 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
93 bool pte_writable[PT_MAX_FULL_LEVELS];
94 unsigned int pt_access[PT_MAX_FULL_LEVELS];
95 unsigned int pte_access;
96 gfn_t gfn;
97 struct x86_exception fault;
98 };
99
gpte_to_gfn_lvl(pt_element_t gpte,int lvl)100 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
101 {
102 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
103 }
104
FNAME(protect_clean_gpte)105 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
106 unsigned gpte)
107 {
108 unsigned mask;
109
110 /* dirty bit is not supported, so no need to track it */
111 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
112 return;
113
114 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
115
116 mask = (unsigned)~ACC_WRITE_MASK;
117 /* Allow write access to dirty gptes */
118 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
119 PT_WRITABLE_MASK;
120 *access &= mask;
121 }
122
FNAME(is_present_gpte)123 static inline int FNAME(is_present_gpte)(unsigned long pte)
124 {
125 #if PTTYPE != PTTYPE_EPT
126 return pte & PT_PRESENT_MASK;
127 #else
128 return pte & 7;
129 #endif
130 }
131
FNAME(cmpxchg_gpte)132 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
133 pt_element_t __user *ptep_user, unsigned index,
134 pt_element_t orig_pte, pt_element_t new_pte)
135 {
136 int r = -EFAULT;
137
138 if (!user_access_begin(ptep_user, sizeof(pt_element_t)))
139 return -EFAULT;
140
141 #ifdef CMPXCHG
142 asm volatile("1:" LOCK_PREFIX CMPXCHG " %[new], %[ptr]\n"
143 "mov $0, %[r]\n"
144 "setnz %b[r]\n"
145 "2:"
146 _ASM_EXTABLE_UA(1b, 2b)
147 : [ptr] "+m" (*ptep_user),
148 [old] "+a" (orig_pte),
149 [r] "+q" (r)
150 : [new] "r" (new_pte)
151 : "memory");
152 #else
153 asm volatile("1:" LOCK_PREFIX "cmpxchg8b %[ptr]\n"
154 "movl $0, %[r]\n"
155 "jz 2f\n"
156 "incl %[r]\n"
157 "2:"
158 _ASM_EXTABLE_UA(1b, 2b)
159 : [ptr] "+m" (*ptep_user),
160 [old] "+A" (orig_pte),
161 [r] "+rm" (r)
162 : [new_lo] "b" ((u32)new_pte),
163 [new_hi] "c" ((u32)(new_pte >> 32))
164 : "memory");
165 #endif
166
167 user_access_end();
168 return r;
169 }
170
FNAME(prefetch_invalid_gpte)171 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
172 struct kvm_mmu_page *sp, u64 *spte,
173 u64 gpte)
174 {
175 if (is_rsvd_bits_set(vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
176 goto no_present;
177
178 if (!FNAME(is_present_gpte)(gpte))
179 goto no_present;
180
181 /* if accessed bit is not supported prefetch non accessed gpte */
182 if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) &&
183 !(gpte & PT_GUEST_ACCESSED_MASK))
184 goto no_present;
185
186 return false;
187
188 no_present:
189 drop_spte(vcpu->kvm, spte);
190 return true;
191 }
192
193 /*
194 * For PTTYPE_EPT, a page table can be executable but not readable
195 * on supported processors. Therefore, set_spte does not automatically
196 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
197 * to signify readability since it isn't used in the EPT case
198 */
FNAME(gpte_access)199 static inline unsigned FNAME(gpte_access)(u64 gpte)
200 {
201 unsigned access;
202 #if PTTYPE == PTTYPE_EPT
203 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
204 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
205 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
206 #else
207 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
208 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
209 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
210 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
211 access ^= (gpte >> PT64_NX_SHIFT);
212 #endif
213
214 return access;
215 }
216
FNAME(update_accessed_dirty_bits)217 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
218 struct kvm_mmu *mmu,
219 struct guest_walker *walker,
220 gpa_t addr, int write_fault)
221 {
222 unsigned level, index;
223 pt_element_t pte, orig_pte;
224 pt_element_t __user *ptep_user;
225 gfn_t table_gfn;
226 int ret;
227
228 /* dirty/accessed bits are not supported, so no need to update them */
229 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
230 return 0;
231
232 for (level = walker->max_level; level >= walker->level; --level) {
233 pte = orig_pte = walker->ptes[level - 1];
234 table_gfn = walker->table_gfn[level - 1];
235 ptep_user = walker->ptep_user[level - 1];
236 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
237 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
238 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
239 pte |= PT_GUEST_ACCESSED_MASK;
240 }
241 if (level == walker->level && write_fault &&
242 !(pte & PT_GUEST_DIRTY_MASK)) {
243 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
244 #if PTTYPE == PTTYPE_EPT
245 if (kvm_arch_write_log_dirty(vcpu, addr))
246 return -EINVAL;
247 #endif
248 pte |= PT_GUEST_DIRTY_MASK;
249 }
250 if (pte == orig_pte)
251 continue;
252
253 /*
254 * If the slot is read-only, simply do not process the accessed
255 * and dirty bits. This is the correct thing to do if the slot
256 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
257 * are only supported if the accessed and dirty bits are already
258 * set in the ROM (so that MMIO writes are never needed).
259 *
260 * Note that NPT does not allow this at all and faults, since
261 * it always wants nested page table entries for the guest
262 * page tables to be writable. And EPT works but will simply
263 * overwrite the read-only memory to set the accessed and dirty
264 * bits.
265 */
266 if (unlikely(!walker->pte_writable[level - 1]))
267 continue;
268
269 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
270 if (ret)
271 return ret;
272
273 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
274 walker->ptes[level - 1] = pte;
275 }
276 return 0;
277 }
278
FNAME(gpte_pkeys)279 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
280 {
281 unsigned pkeys = 0;
282 #if PTTYPE == 64
283 pte_t pte = {.pte = gpte};
284
285 pkeys = pte_flags_pkey(pte_flags(pte));
286 #endif
287 return pkeys;
288 }
289
290 /*
291 * Fetch a guest pte for a guest virtual address, or for an L2's GPA.
292 */
FNAME(walk_addr_generic)293 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
294 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
295 gpa_t addr, u32 access)
296 {
297 int ret;
298 pt_element_t pte;
299 pt_element_t __user *uninitialized_var(ptep_user);
300 gfn_t table_gfn;
301 u64 pt_access, pte_access;
302 unsigned index, accessed_dirty, pte_pkey;
303 unsigned nested_access;
304 gpa_t pte_gpa;
305 bool have_ad;
306 int offset;
307 u64 walk_nx_mask = 0;
308 const int write_fault = access & PFERR_WRITE_MASK;
309 const int user_fault = access & PFERR_USER_MASK;
310 const int fetch_fault = access & PFERR_FETCH_MASK;
311 u16 errcode = 0;
312 gpa_t real_gpa;
313 gfn_t gfn;
314
315 trace_kvm_mmu_pagetable_walk(addr, access);
316 retry_walk:
317 walker->level = mmu->root_level;
318 pte = mmu->get_cr3(vcpu);
319 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
320
321 #if PTTYPE == 64
322 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
323 if (walker->level == PT32E_ROOT_LEVEL) {
324 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
325 trace_kvm_mmu_paging_element(pte, walker->level);
326 if (!FNAME(is_present_gpte)(pte))
327 goto error;
328 --walker->level;
329 }
330 #endif
331 walker->max_level = walker->level;
332 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
333
334 /*
335 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
336 * by the MOV to CR instruction are treated as reads and do not cause the
337 * processor to set the dirty flag in any EPT paging-structure entry.
338 */
339 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
340
341 pte_access = ~0;
342 ++walker->level;
343
344 do {
345 gfn_t real_gfn;
346 unsigned long host_addr;
347
348 pt_access = pte_access;
349 --walker->level;
350
351 index = PT_INDEX(addr, walker->level);
352 table_gfn = gpte_to_gfn(pte);
353 offset = index * sizeof(pt_element_t);
354 pte_gpa = gfn_to_gpa(table_gfn) + offset;
355
356 BUG_ON(walker->level < 1);
357 walker->table_gfn[walker->level - 1] = table_gfn;
358 walker->pte_gpa[walker->level - 1] = pte_gpa;
359
360 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
361 nested_access,
362 &walker->fault);
363
364 /*
365 * FIXME: This can happen if emulation (for of an INS/OUTS
366 * instruction) triggers a nested page fault. The exit
367 * qualification / exit info field will incorrectly have
368 * "guest page access" as the nested page fault's cause,
369 * instead of "guest page structure access". To fix this,
370 * the x86_exception struct should be augmented with enough
371 * information to fix the exit_qualification or exit_info_1
372 * fields.
373 */
374 if (unlikely(real_gfn == UNMAPPED_GVA))
375 return 0;
376
377 real_gfn = gpa_to_gfn(real_gfn);
378
379 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
380 &walker->pte_writable[walker->level - 1]);
381 if (unlikely(kvm_is_error_hva(host_addr)))
382 goto error;
383
384 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
385 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
386 goto error;
387 walker->ptep_user[walker->level - 1] = ptep_user;
388
389 trace_kvm_mmu_paging_element(pte, walker->level);
390
391 /*
392 * Inverting the NX it lets us AND it like other
393 * permission bits.
394 */
395 pte_access = pt_access & (pte ^ walk_nx_mask);
396
397 if (unlikely(!FNAME(is_present_gpte)(pte)))
398 goto error;
399
400 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
401 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
402 goto error;
403 }
404
405 walker->ptes[walker->level - 1] = pte;
406
407 /* Convert to ACC_*_MASK flags for struct guest_walker. */
408 walker->pt_access[walker->level - 1] = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
409 } while (!is_last_gpte(mmu, walker->level, pte));
410
411 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
412 accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
413
414 /* Convert to ACC_*_MASK flags for struct guest_walker. */
415 walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
416 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
417 if (unlikely(errcode))
418 goto error;
419
420 gfn = gpte_to_gfn_lvl(pte, walker->level);
421 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
422
423 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
424 gfn += pse36_gfn_delta(pte);
425
426 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
427 if (real_gpa == UNMAPPED_GVA)
428 return 0;
429
430 walker->gfn = real_gpa >> PAGE_SHIFT;
431
432 if (!write_fault)
433 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
434 else
435 /*
436 * On a write fault, fold the dirty bit into accessed_dirty.
437 * For modes without A/D bits support accessed_dirty will be
438 * always clear.
439 */
440 accessed_dirty &= pte >>
441 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
442
443 if (unlikely(!accessed_dirty)) {
444 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker,
445 addr, write_fault);
446 if (unlikely(ret < 0))
447 goto error;
448 else if (ret)
449 goto retry_walk;
450 }
451
452 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
453 __func__, (u64)pte, walker->pte_access,
454 walker->pt_access[walker->level - 1]);
455 return 1;
456
457 error:
458 errcode |= write_fault | user_fault;
459 if (fetch_fault && (mmu->nx ||
460 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
461 errcode |= PFERR_FETCH_MASK;
462
463 walker->fault.vector = PF_VECTOR;
464 walker->fault.error_code_valid = true;
465 walker->fault.error_code = errcode;
466
467 #if PTTYPE == PTTYPE_EPT
468 /*
469 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
470 * misconfiguration requires to be injected. The detection is
471 * done by is_rsvd_bits_set() above.
472 *
473 * We set up the value of exit_qualification to inject:
474 * [2:0] - Derive from the access bits. The exit_qualification might be
475 * out of date if it is serving an EPT misconfiguration.
476 * [5:3] - Calculated by the page walk of the guest EPT page tables
477 * [7:8] - Derived from [7:8] of real exit_qualification
478 *
479 * The other bits are set to 0.
480 */
481 if (!(errcode & PFERR_RSVD_MASK)) {
482 vcpu->arch.exit_qualification &= 0x180;
483 if (write_fault)
484 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
485 if (user_fault)
486 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
487 if (fetch_fault)
488 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
489 vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
490 }
491 #endif
492 walker->fault.address = addr;
493 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
494
495 trace_kvm_mmu_walker_error(walker->fault.error_code);
496 return 0;
497 }
498
FNAME(walk_addr)499 static int FNAME(walk_addr)(struct guest_walker *walker,
500 struct kvm_vcpu *vcpu, gpa_t addr, u32 access)
501 {
502 return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr,
503 access);
504 }
505
506 #if PTTYPE != PTTYPE_EPT
FNAME(walk_addr_nested)507 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
508 struct kvm_vcpu *vcpu, gva_t addr,
509 u32 access)
510 {
511 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
512 addr, access);
513 }
514 #endif
515
516 static bool
FNAME(prefetch_gpte)517 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
518 u64 *spte, pt_element_t gpte, bool no_dirty_log)
519 {
520 unsigned pte_access;
521 gfn_t gfn;
522 kvm_pfn_t pfn;
523
524 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
525 return false;
526
527 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
528
529 gfn = gpte_to_gfn(gpte);
530 pte_access = sp->role.access & FNAME(gpte_access)(gpte);
531 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
532 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
533 no_dirty_log && (pte_access & ACC_WRITE_MASK));
534 if (is_error_pfn(pfn))
535 return false;
536
537 /*
538 * we call mmu_set_spte() with host_writable = true because
539 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
540 */
541 mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
542 true, true);
543
544 kvm_release_pfn_clean(pfn);
545 return true;
546 }
547
FNAME(update_pte)548 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
549 u64 *spte, const void *pte)
550 {
551 pt_element_t gpte = *(const pt_element_t *)pte;
552
553 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
554 }
555
FNAME(gpte_changed)556 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
557 struct guest_walker *gw, int level)
558 {
559 pt_element_t curr_pte;
560 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
561 u64 mask;
562 int r, index;
563
564 if (level == PT_PAGE_TABLE_LEVEL) {
565 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
566 base_gpa = pte_gpa & ~mask;
567 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
568
569 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
570 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
571 curr_pte = gw->prefetch_ptes[index];
572 } else
573 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
574 &curr_pte, sizeof(curr_pte));
575
576 return r || curr_pte != gw->ptes[level - 1];
577 }
578
FNAME(pte_prefetch)579 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
580 u64 *sptep)
581 {
582 struct kvm_mmu_page *sp;
583 pt_element_t *gptep = gw->prefetch_ptes;
584 u64 *spte;
585 int i;
586
587 sp = page_header(__pa(sptep));
588
589 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
590 return;
591
592 if (sp->role.direct)
593 return __direct_pte_prefetch(vcpu, sp, sptep);
594
595 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
596 spte = sp->spt + i;
597
598 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
599 if (spte == sptep)
600 continue;
601
602 if (is_shadow_present_pte(*spte))
603 continue;
604
605 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
606 break;
607 }
608 }
609
610 /*
611 * Fetch a shadow pte for a specific level in the paging hierarchy.
612 * If the guest tries to write a write-protected page, we need to
613 * emulate this operation, return 1 to indicate this case.
614 */
FNAME(fetch)615 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr,
616 struct guest_walker *gw,
617 int write_fault, int hlevel,
618 kvm_pfn_t pfn, bool map_writable, bool prefault,
619 bool lpage_disallowed)
620 {
621 struct kvm_mmu_page *sp = NULL;
622 struct kvm_shadow_walk_iterator it;
623 unsigned int direct_access, access;
624 int top_level, ret;
625 gfn_t gfn, base_gfn;
626
627 direct_access = gw->pte_access;
628
629 top_level = vcpu->arch.mmu->root_level;
630 if (top_level == PT32E_ROOT_LEVEL)
631 top_level = PT32_ROOT_LEVEL;
632 /*
633 * Verify that the top-level gpte is still there. Since the page
634 * is a root page, it is either write protected (and cannot be
635 * changed from now on) or it is invalid (in which case, we don't
636 * really care if it changes underneath us after this point).
637 */
638 if (FNAME(gpte_changed)(vcpu, gw, top_level))
639 goto out_gpte_changed;
640
641 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
642 goto out_gpte_changed;
643
644 for (shadow_walk_init(&it, vcpu, addr);
645 shadow_walk_okay(&it) && it.level > gw->level;
646 shadow_walk_next(&it)) {
647 gfn_t table_gfn;
648
649 clear_sp_write_flooding_count(it.sptep);
650 drop_large_spte(vcpu, it.sptep);
651
652 sp = NULL;
653 if (!is_shadow_present_pte(*it.sptep)) {
654 table_gfn = gw->table_gfn[it.level - 2];
655 access = gw->pt_access[it.level - 2];
656 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
657 false, access);
658 }
659
660 /*
661 * Verify that the gpte in the page we've just write
662 * protected is still there.
663 */
664 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
665 goto out_gpte_changed;
666
667 if (sp)
668 link_shadow_page(vcpu, it.sptep, sp);
669 }
670
671 /*
672 * FNAME(page_fault) might have clobbered the bottom bits of
673 * gw->gfn, restore them from the virtual address.
674 */
675 gfn = gw->gfn | ((addr & PT_LVL_OFFSET_MASK(gw->level)) >> PAGE_SHIFT);
676 base_gfn = gfn;
677
678 trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
679
680 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
681 clear_sp_write_flooding_count(it.sptep);
682
683 /*
684 * We cannot overwrite existing page tables with an NX
685 * large page, as the leaf could be executable.
686 */
687 disallowed_hugepage_adjust(it, gfn, &pfn, &hlevel);
688
689 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
690 if (it.level == hlevel)
691 break;
692
693 validate_direct_spte(vcpu, it.sptep, direct_access);
694
695 drop_large_spte(vcpu, it.sptep);
696
697 if (!is_shadow_present_pte(*it.sptep)) {
698 sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
699 it.level - 1, true, direct_access);
700 link_shadow_page(vcpu, it.sptep, sp);
701 if (lpage_disallowed)
702 account_huge_nx_page(vcpu->kvm, sp);
703 }
704 }
705
706 ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
707 it.level, base_gfn, pfn, prefault, map_writable);
708 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
709 ++vcpu->stat.pf_fixed;
710 return ret;
711
712 out_gpte_changed:
713 return RET_PF_RETRY;
714 }
715
716 /*
717 * To see whether the mapped gfn can write its page table in the current
718 * mapping.
719 *
720 * It is the helper function of FNAME(page_fault). When guest uses large page
721 * size to map the writable gfn which is used as current page table, we should
722 * force kvm to use small page size to map it because new shadow page will be
723 * created when kvm establishes shadow page table that stop kvm using large
724 * page size. Do it early can avoid unnecessary #PF and emulation.
725 *
726 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
727 * currently used as its page table.
728 *
729 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
730 * since the PDPT is always shadowed, that means, we can not use large page
731 * size to map the gfn which is used as PDPT.
732 */
733 static bool
FNAME(is_self_change_mapping)734 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
735 struct guest_walker *walker, int user_fault,
736 bool *write_fault_to_shadow_pgtable)
737 {
738 int level;
739 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
740 bool self_changed = false;
741
742 if (!(walker->pte_access & ACC_WRITE_MASK ||
743 (!is_write_protection(vcpu) && !user_fault)))
744 return false;
745
746 for (level = walker->level; level <= walker->max_level; level++) {
747 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
748
749 self_changed |= !(gfn & mask);
750 *write_fault_to_shadow_pgtable |= !gfn;
751 }
752
753 return self_changed;
754 }
755
756 /*
757 * Page fault handler. There are several causes for a page fault:
758 * - there is no shadow pte for the guest pte
759 * - write access through a shadow pte marked read only so that we can set
760 * the dirty bit
761 * - write access to a shadow pte marked read only so we can update the page
762 * dirty bitmap, when userspace requests it
763 * - mmio access; in this case we will never install a present shadow pte
764 * - normal guest page fault due to the guest pte marked not present, not
765 * writable, or not executable
766 *
767 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
768 * a negative value on error.
769 */
FNAME(page_fault)770 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code,
771 bool prefault)
772 {
773 int write_fault = error_code & PFERR_WRITE_MASK;
774 int user_fault = error_code & PFERR_USER_MASK;
775 struct guest_walker walker;
776 int r;
777 kvm_pfn_t pfn;
778 int level = PT_PAGE_TABLE_LEVEL;
779 unsigned long mmu_seq;
780 bool map_writable, is_self_change_mapping;
781 bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) &&
782 is_nx_huge_page_enabled();
783 bool force_pt_level = lpage_disallowed;
784
785 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
786
787 r = mmu_topup_memory_caches(vcpu);
788 if (r)
789 return r;
790
791 /*
792 * If PFEC.RSVD is set, this is a shadow page fault.
793 * The bit needs to be cleared before walking guest page tables.
794 */
795 error_code &= ~PFERR_RSVD_MASK;
796
797 /*
798 * Look up the guest pte for the faulting address.
799 */
800 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
801
802 /*
803 * The page is not mapped by the guest. Let the guest handle it.
804 */
805 if (!r) {
806 pgprintk("%s: guest page fault\n", __func__);
807 if (!prefault)
808 inject_page_fault(vcpu, &walker.fault);
809
810 return RET_PF_RETRY;
811 }
812
813 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
814 shadow_page_table_clear_flood(vcpu, addr);
815 return RET_PF_EMULATE;
816 }
817
818 vcpu->arch.write_fault_to_shadow_pgtable = false;
819
820 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
821 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
822
823 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
824 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
825 if (likely(!force_pt_level)) {
826 level = min(walker.level, level);
827 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
828 }
829 } else
830 force_pt_level = true;
831
832 mmu_seq = vcpu->kvm->mmu_notifier_seq;
833 smp_rmb();
834
835 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
836 &map_writable))
837 return RET_PF_RETRY;
838
839 if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r))
840 return r;
841
842 /*
843 * Do not change pte_access if the pfn is a mmio page, otherwise
844 * we will cache the incorrect access into mmio spte.
845 */
846 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
847 !is_write_protection(vcpu) && !user_fault &&
848 !is_noslot_pfn(pfn)) {
849 walker.pte_access |= ACC_WRITE_MASK;
850 walker.pte_access &= ~ACC_USER_MASK;
851
852 /*
853 * If we converted a user page to a kernel page,
854 * so that the kernel can write to it when cr0.wp=0,
855 * then we should prevent the kernel from executing it
856 * if SMEP is enabled.
857 */
858 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
859 walker.pte_access &= ~ACC_EXEC_MASK;
860 }
861
862 r = RET_PF_RETRY;
863 spin_lock(&vcpu->kvm->mmu_lock);
864 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
865 goto out_unlock;
866
867 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
868 if (make_mmu_pages_available(vcpu) < 0)
869 goto out_unlock;
870 if (!force_pt_level)
871 transparent_hugepage_adjust(vcpu, walker.gfn, &pfn, &level);
872 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
873 level, pfn, map_writable, prefault, lpage_disallowed);
874 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
875
876 out_unlock:
877 spin_unlock(&vcpu->kvm->mmu_lock);
878 kvm_release_pfn_clean(pfn);
879 return r;
880 }
881
FNAME(get_level1_sp_gpa)882 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
883 {
884 int offset = 0;
885
886 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
887
888 if (PTTYPE == 32)
889 offset = sp->role.quadrant << PT64_LEVEL_BITS;
890
891 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
892 }
893
FNAME(invlpg)894 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa)
895 {
896 struct kvm_shadow_walk_iterator iterator;
897 struct kvm_mmu_page *sp;
898 int level;
899 u64 *sptep;
900
901 vcpu_clear_mmio_info(vcpu, gva);
902
903 /*
904 * No need to check return value here, rmap_can_add() can
905 * help us to skip pte prefetch later.
906 */
907 mmu_topup_memory_caches(vcpu);
908
909 if (!VALID_PAGE(root_hpa)) {
910 WARN_ON(1);
911 return;
912 }
913
914 spin_lock(&vcpu->kvm->mmu_lock);
915 for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) {
916 level = iterator.level;
917 sptep = iterator.sptep;
918
919 sp = page_header(__pa(sptep));
920 if (is_last_spte(*sptep, level)) {
921 pt_element_t gpte;
922 gpa_t pte_gpa;
923
924 if (!sp->unsync)
925 break;
926
927 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
928 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
929
930 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
931 kvm_flush_remote_tlbs_with_address(vcpu->kvm,
932 sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
933
934 if (!rmap_can_add(vcpu))
935 break;
936
937 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
938 sizeof(pt_element_t)))
939 break;
940
941 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
942 }
943
944 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
945 break;
946 }
947 spin_unlock(&vcpu->kvm->mmu_lock);
948 }
949
950 /* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */
FNAME(gva_to_gpa)951 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access,
952 struct x86_exception *exception)
953 {
954 struct guest_walker walker;
955 gpa_t gpa = UNMAPPED_GVA;
956 int r;
957
958 r = FNAME(walk_addr)(&walker, vcpu, addr, access);
959
960 if (r) {
961 gpa = gfn_to_gpa(walker.gfn);
962 gpa |= addr & ~PAGE_MASK;
963 } else if (exception)
964 *exception = walker.fault;
965
966 return gpa;
967 }
968
969 #if PTTYPE != PTTYPE_EPT
970 /* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */
FNAME(gva_to_gpa_nested)971 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr,
972 u32 access,
973 struct x86_exception *exception)
974 {
975 struct guest_walker walker;
976 gpa_t gpa = UNMAPPED_GVA;
977 int r;
978
979 #ifndef CONFIG_X86_64
980 /* A 64-bit GVA should be impossible on 32-bit KVM. */
981 WARN_ON_ONCE(vaddr >> 32);
982 #endif
983
984 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
985
986 if (r) {
987 gpa = gfn_to_gpa(walker.gfn);
988 gpa |= vaddr & ~PAGE_MASK;
989 } else if (exception)
990 *exception = walker.fault;
991
992 return gpa;
993 }
994 #endif
995
996 /*
997 * Using the cached information from sp->gfns is safe because:
998 * - The spte has a reference to the struct page, so the pfn for a given gfn
999 * can't change unless all sptes pointing to it are nuked first.
1000 *
1001 * Note:
1002 * We should flush all tlbs if spte is dropped even though guest is
1003 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
1004 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
1005 * used by guest then tlbs are not flushed, so guest is allowed to access the
1006 * freed pages.
1007 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
1008 */
FNAME(sync_page)1009 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1010 {
1011 int i, nr_present = 0;
1012 bool host_writable;
1013 gpa_t first_pte_gpa;
1014 int set_spte_ret = 0;
1015
1016 /* direct kvm_mmu_page can not be unsync. */
1017 BUG_ON(sp->role.direct);
1018
1019 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
1020
1021 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
1022 unsigned pte_access;
1023 pt_element_t gpte;
1024 gpa_t pte_gpa;
1025 gfn_t gfn;
1026
1027 if (!sp->spt[i])
1028 continue;
1029
1030 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1031
1032 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1033 sizeof(pt_element_t)))
1034 return 0;
1035
1036 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1037 /*
1038 * Update spte before increasing tlbs_dirty to make
1039 * sure no tlb flush is lost after spte is zapped; see
1040 * the comments in kvm_flush_remote_tlbs().
1041 */
1042 smp_wmb();
1043 vcpu->kvm->tlbs_dirty++;
1044 continue;
1045 }
1046
1047 gfn = gpte_to_gfn(gpte);
1048 pte_access = sp->role.access;
1049 pte_access &= FNAME(gpte_access)(gpte);
1050 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
1051
1052 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1053 &nr_present))
1054 continue;
1055
1056 if (gfn != sp->gfns[i]) {
1057 drop_spte(vcpu->kvm, &sp->spt[i]);
1058 /*
1059 * The same as above where we are doing
1060 * prefetch_invalid_gpte().
1061 */
1062 smp_wmb();
1063 vcpu->kvm->tlbs_dirty++;
1064 continue;
1065 }
1066
1067 nr_present++;
1068
1069 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1070
1071 set_spte_ret |= set_spte(vcpu, &sp->spt[i],
1072 pte_access, PT_PAGE_TABLE_LEVEL,
1073 gfn, spte_to_pfn(sp->spt[i]),
1074 true, false, host_writable);
1075 }
1076
1077 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH)
1078 kvm_flush_remote_tlbs(vcpu->kvm);
1079
1080 return nr_present;
1081 }
1082
1083 #undef pt_element_t
1084 #undef guest_walker
1085 #undef FNAME
1086 #undef PT_BASE_ADDR_MASK
1087 #undef PT_INDEX
1088 #undef PT_LVL_ADDR_MASK
1089 #undef PT_LVL_OFFSET_MASK
1090 #undef PT_LEVEL_BITS
1091 #undef PT_MAX_FULL_LEVELS
1092 #undef gpte_to_gfn
1093 #undef gpte_to_gfn_lvl
1094 #undef CMPXCHG
1095 #undef PT_GUEST_ACCESSED_MASK
1096 #undef PT_GUEST_DIRTY_MASK
1097 #undef PT_GUEST_DIRTY_SHIFT
1098 #undef PT_GUEST_ACCESSED_SHIFT
1099 #undef PT_HAVE_ACCESSED_DIRTY
1100