1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2015 Atmel Corporation,
4 * Nicolas Ferre <nicolas.ferre@atmel.com>
5 *
6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk/at91_pmc.h>
13 #include <linux/of.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/regmap.h>
16
17 #include "pmc.h"
18
19 #define GENERATED_MAX_DIV 255
20
21 struct clk_generated {
22 struct clk_hw hw;
23 struct regmap *regmap;
24 struct clk_range range;
25 spinlock_t *lock;
26 u32 id;
27 u32 gckdiv;
28 const struct clk_pcr_layout *layout;
29 u8 parent_id;
30 int chg_pid;
31 };
32
33 #define to_clk_generated(hw) \
34 container_of(hw, struct clk_generated, hw)
35
clk_generated_enable(struct clk_hw * hw)36 static int clk_generated_enable(struct clk_hw *hw)
37 {
38 struct clk_generated *gck = to_clk_generated(hw);
39 unsigned long flags;
40
41 pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
42 __func__, gck->gckdiv, gck->parent_id);
43
44 spin_lock_irqsave(gck->lock, flags);
45 regmap_write(gck->regmap, gck->layout->offset,
46 (gck->id & gck->layout->pid_mask));
47 regmap_update_bits(gck->regmap, gck->layout->offset,
48 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
49 gck->layout->cmd | AT91_PMC_PCR_GCKEN,
50 field_prep(gck->layout->gckcss_mask, gck->parent_id) |
51 gck->layout->cmd |
52 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
53 AT91_PMC_PCR_GCKEN);
54 spin_unlock_irqrestore(gck->lock, flags);
55 return 0;
56 }
57
clk_generated_disable(struct clk_hw * hw)58 static void clk_generated_disable(struct clk_hw *hw)
59 {
60 struct clk_generated *gck = to_clk_generated(hw);
61 unsigned long flags;
62
63 spin_lock_irqsave(gck->lock, flags);
64 regmap_write(gck->regmap, gck->layout->offset,
65 (gck->id & gck->layout->pid_mask));
66 regmap_update_bits(gck->regmap, gck->layout->offset,
67 gck->layout->cmd | AT91_PMC_PCR_GCKEN,
68 gck->layout->cmd);
69 spin_unlock_irqrestore(gck->lock, flags);
70 }
71
clk_generated_is_enabled(struct clk_hw * hw)72 static int clk_generated_is_enabled(struct clk_hw *hw)
73 {
74 struct clk_generated *gck = to_clk_generated(hw);
75 unsigned long flags;
76 unsigned int status;
77
78 spin_lock_irqsave(gck->lock, flags);
79 regmap_write(gck->regmap, gck->layout->offset,
80 (gck->id & gck->layout->pid_mask));
81 regmap_read(gck->regmap, gck->layout->offset, &status);
82 spin_unlock_irqrestore(gck->lock, flags);
83
84 return status & AT91_PMC_PCR_GCKEN ? 1 : 0;
85 }
86
87 static unsigned long
clk_generated_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)88 clk_generated_recalc_rate(struct clk_hw *hw,
89 unsigned long parent_rate)
90 {
91 struct clk_generated *gck = to_clk_generated(hw);
92
93 return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
94 }
95
clk_generated_best_diff(struct clk_rate_request * req,struct clk_hw * parent,unsigned long parent_rate,u32 div,int * best_diff,long * best_rate)96 static void clk_generated_best_diff(struct clk_rate_request *req,
97 struct clk_hw *parent,
98 unsigned long parent_rate, u32 div,
99 int *best_diff, long *best_rate)
100 {
101 unsigned long tmp_rate;
102 int tmp_diff;
103
104 if (!div)
105 tmp_rate = parent_rate;
106 else
107 tmp_rate = parent_rate / div;
108
109 if (tmp_rate < req->min_rate || tmp_rate > req->max_rate)
110 return;
111
112 tmp_diff = abs(req->rate - tmp_rate);
113
114 if (*best_diff < 0 || *best_diff >= tmp_diff) {
115 *best_rate = tmp_rate;
116 *best_diff = tmp_diff;
117 req->best_parent_rate = parent_rate;
118 req->best_parent_hw = parent;
119 }
120 }
121
clk_generated_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)122 static int clk_generated_determine_rate(struct clk_hw *hw,
123 struct clk_rate_request *req)
124 {
125 struct clk_generated *gck = to_clk_generated(hw);
126 struct clk_hw *parent = NULL;
127 struct clk_rate_request req_parent = *req;
128 long best_rate = -EINVAL;
129 unsigned long min_rate, parent_rate;
130 int best_diff = -1;
131 int i;
132 u32 div;
133
134 /* do not look for a rate that is outside of our range */
135 if (gck->range.max && req->rate > gck->range.max)
136 req->rate = gck->range.max;
137 if (gck->range.min && req->rate < gck->range.min)
138 req->rate = gck->range.min;
139
140 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
141 if (gck->chg_pid == i)
142 continue;
143
144 parent = clk_hw_get_parent_by_index(hw, i);
145 if (!parent)
146 continue;
147
148 parent_rate = clk_hw_get_rate(parent);
149 min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
150 if (!parent_rate ||
151 (gck->range.max && min_rate > gck->range.max))
152 continue;
153
154 div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
155 if (div > GENERATED_MAX_DIV + 1)
156 div = GENERATED_MAX_DIV + 1;
157
158 clk_generated_best_diff(req, parent, parent_rate, div,
159 &best_diff, &best_rate);
160
161 if (!best_diff)
162 break;
163 }
164
165 /*
166 * The audio_pll rate can be modified, unlike the five others clocks
167 * that should never be altered.
168 * The audio_pll can technically be used by multiple consumers. However,
169 * with the rate locking, the first consumer to enable to clock will be
170 * the one definitely setting the rate of the clock.
171 * Since audio IPs are most likely to request the same rate, we enforce
172 * that the only clks able to modify gck rate are those of audio IPs.
173 */
174
175 if (gck->chg_pid < 0)
176 goto end;
177
178 parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
179 if (!parent)
180 goto end;
181
182 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
183 req_parent.rate = req->rate * div;
184 __clk_determine_rate(parent, &req_parent);
185 clk_generated_best_diff(req, parent, req_parent.rate, div,
186 &best_diff, &best_rate);
187
188 if (!best_diff)
189 break;
190 }
191
192 end:
193 pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
194 __func__, best_rate,
195 __clk_get_name((req->best_parent_hw)->clk),
196 req->best_parent_rate);
197
198 if (best_rate < 0)
199 return best_rate;
200
201 req->rate = best_rate;
202 return 0;
203 }
204
205 /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
clk_generated_set_parent(struct clk_hw * hw,u8 index)206 static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
207 {
208 struct clk_generated *gck = to_clk_generated(hw);
209
210 if (index >= clk_hw_get_num_parents(hw))
211 return -EINVAL;
212
213 gck->parent_id = index;
214 return 0;
215 }
216
clk_generated_get_parent(struct clk_hw * hw)217 static u8 clk_generated_get_parent(struct clk_hw *hw)
218 {
219 struct clk_generated *gck = to_clk_generated(hw);
220
221 return gck->parent_id;
222 }
223
224 /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
clk_generated_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)225 static int clk_generated_set_rate(struct clk_hw *hw,
226 unsigned long rate,
227 unsigned long parent_rate)
228 {
229 struct clk_generated *gck = to_clk_generated(hw);
230 u32 div;
231
232 if (!rate)
233 return -EINVAL;
234
235 if (gck->range.max && rate > gck->range.max)
236 return -EINVAL;
237
238 div = DIV_ROUND_CLOSEST(parent_rate, rate);
239 if (div > GENERATED_MAX_DIV + 1 || !div)
240 return -EINVAL;
241
242 gck->gckdiv = div - 1;
243 return 0;
244 }
245
246 static const struct clk_ops generated_ops = {
247 .enable = clk_generated_enable,
248 .disable = clk_generated_disable,
249 .is_enabled = clk_generated_is_enabled,
250 .recalc_rate = clk_generated_recalc_rate,
251 .determine_rate = clk_generated_determine_rate,
252 .get_parent = clk_generated_get_parent,
253 .set_parent = clk_generated_set_parent,
254 .set_rate = clk_generated_set_rate,
255 };
256
257 /**
258 * clk_generated_startup - Initialize a given clock to its default parent and
259 * divisor parameter.
260 *
261 * @gck: Generated clock to set the startup parameters for.
262 *
263 * Take parameters from the hardware and update local clock configuration
264 * accordingly.
265 */
clk_generated_startup(struct clk_generated * gck)266 static void clk_generated_startup(struct clk_generated *gck)
267 {
268 u32 tmp;
269 unsigned long flags;
270
271 spin_lock_irqsave(gck->lock, flags);
272 regmap_write(gck->regmap, gck->layout->offset,
273 (gck->id & gck->layout->pid_mask));
274 regmap_read(gck->regmap, gck->layout->offset, &tmp);
275 spin_unlock_irqrestore(gck->lock, flags);
276
277 gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
278 gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
279 }
280
281 struct clk_hw * __init
at91_clk_register_generated(struct regmap * regmap,spinlock_t * lock,const struct clk_pcr_layout * layout,const char * name,const char ** parent_names,u8 num_parents,u8 id,const struct clk_range * range,int chg_pid)282 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
283 const struct clk_pcr_layout *layout,
284 const char *name, const char **parent_names,
285 u8 num_parents, u8 id,
286 const struct clk_range *range, int chg_pid)
287 {
288 struct clk_generated *gck;
289 struct clk_init_data init;
290 struct clk_hw *hw;
291 int ret;
292
293 gck = kzalloc(sizeof(*gck), GFP_KERNEL);
294 if (!gck)
295 return ERR_PTR(-ENOMEM);
296
297 init.name = name;
298 init.ops = &generated_ops;
299 init.parent_names = parent_names;
300 init.num_parents = num_parents;
301 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
302 if (chg_pid >= 0)
303 init.flags |= CLK_SET_RATE_PARENT;
304
305 gck->id = id;
306 gck->hw.init = &init;
307 gck->regmap = regmap;
308 gck->lock = lock;
309 gck->range = *range;
310 gck->chg_pid = chg_pid;
311 gck->layout = layout;
312
313 clk_generated_startup(gck);
314 hw = &gck->hw;
315 ret = clk_hw_register(NULL, &gck->hw);
316 if (ret) {
317 kfree(gck);
318 hw = ERR_PTR(ret);
319 } else {
320 pmc_register_id(id);
321 }
322
323 return hw;
324 }
325