1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
4 #include <linux/of.h>
5 #include <linux/mfd/syscon.h>
6 #include <linux/regmap.h>
7 #include <linux/slab.h>
8
9 #include "pmc.h"
10
11 #define MASTER_SOURCE_MAX 4
12
13 #define PERIPHERAL_AT91RM9200 0
14 #define PERIPHERAL_AT91SAM9X5 1
15
16 #define PERIPHERAL_MAX 64
17
18 #define PERIPHERAL_ID_MIN 2
19
20 #define PROG_SOURCE_MAX 5
21 #define PROG_ID_MAX 7
22
23 #define SYSTEM_MAX_ID 31
24
25 #define GCK_INDEX_DT_AUDIO_PLL 5
26
27 #ifdef CONFIG_HAVE_AT91_AUDIO_PLL
of_sama5d2_clk_audio_pll_frac_setup(struct device_node * np)28 static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
29 {
30 struct clk_hw *hw;
31 const char *name = np->name;
32 const char *parent_name;
33 struct regmap *regmap;
34
35 regmap = syscon_node_to_regmap(of_get_parent(np));
36 if (IS_ERR(regmap))
37 return;
38
39 parent_name = of_clk_get_parent_name(np, 0);
40
41 hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
42 if (IS_ERR(hw))
43 return;
44
45 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
46 }
47 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
48 "atmel,sama5d2-clk-audio-pll-frac",
49 of_sama5d2_clk_audio_pll_frac_setup);
50
of_sama5d2_clk_audio_pll_pad_setup(struct device_node * np)51 static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
52 {
53 struct clk_hw *hw;
54 const char *name = np->name;
55 const char *parent_name;
56 struct regmap *regmap;
57
58 regmap = syscon_node_to_regmap(of_get_parent(np));
59 if (IS_ERR(regmap))
60 return;
61
62 parent_name = of_clk_get_parent_name(np, 0);
63
64 hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
65 if (IS_ERR(hw))
66 return;
67
68 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
69 }
70 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
71 "atmel,sama5d2-clk-audio-pll-pad",
72 of_sama5d2_clk_audio_pll_pad_setup);
73
of_sama5d2_clk_audio_pll_pmc_setup(struct device_node * np)74 static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
75 {
76 struct clk_hw *hw;
77 const char *name = np->name;
78 const char *parent_name;
79 struct regmap *regmap;
80
81 regmap = syscon_node_to_regmap(of_get_parent(np));
82 if (IS_ERR(regmap))
83 return;
84
85 parent_name = of_clk_get_parent_name(np, 0);
86
87 hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
88 if (IS_ERR(hw))
89 return;
90
91 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
92 }
93 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
94 "atmel,sama5d2-clk-audio-pll-pmc",
95 of_sama5d2_clk_audio_pll_pmc_setup);
96 #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
97
98 static const struct clk_pcr_layout dt_pcr_layout = {
99 .offset = 0x10c,
100 .cmd = BIT(12),
101 .pid_mask = GENMASK(5, 0),
102 .div_mask = GENMASK(17, 16),
103 .gckcss_mask = GENMASK(10, 8),
104 };
105
106 #ifdef CONFIG_HAVE_AT91_GENERATED_CLK
107 #define GENERATED_SOURCE_MAX 6
108
109 #define GCK_ID_I2S0 54
110 #define GCK_ID_I2S1 55
111 #define GCK_ID_CLASSD 59
112
of_sama5d2_clk_generated_setup(struct device_node * np)113 static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
114 {
115 int num;
116 u32 id;
117 const char *name;
118 struct clk_hw *hw;
119 unsigned int num_parents;
120 const char *parent_names[GENERATED_SOURCE_MAX];
121 struct device_node *gcknp;
122 struct clk_range range = CLK_RANGE(0, 0);
123 struct regmap *regmap;
124
125 num_parents = of_clk_get_parent_count(np);
126 if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
127 return;
128
129 of_clk_parent_fill(np, parent_names, num_parents);
130
131 num = of_get_child_count(np);
132 if (!num || num > PERIPHERAL_MAX)
133 return;
134
135 regmap = syscon_node_to_regmap(of_get_parent(np));
136 if (IS_ERR(regmap))
137 return;
138
139 for_each_child_of_node(np, gcknp) {
140 int chg_pid = INT_MIN;
141
142 if (of_property_read_u32(gcknp, "reg", &id))
143 continue;
144
145 if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
146 continue;
147
148 if (of_property_read_string(np, "clock-output-names", &name))
149 name = gcknp->name;
150
151 of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
152 &range);
153
154 if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
155 (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
156 id == GCK_ID_CLASSD))
157 chg_pid = GCK_INDEX_DT_AUDIO_PLL;
158
159 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
160 &dt_pcr_layout, name,
161 parent_names, num_parents,
162 id, &range, chg_pid);
163 if (IS_ERR(hw))
164 continue;
165
166 of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
167 }
168 }
169 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
170 of_sama5d2_clk_generated_setup);
171 #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
172
173 #ifdef CONFIG_HAVE_AT91_H32MX
of_sama5d4_clk_h32mx_setup(struct device_node * np)174 static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
175 {
176 struct clk_hw *hw;
177 const char *name = np->name;
178 const char *parent_name;
179 struct regmap *regmap;
180
181 regmap = syscon_node_to_regmap(of_get_parent(np));
182 if (IS_ERR(regmap))
183 return;
184
185 parent_name = of_clk_get_parent_name(np, 0);
186
187 hw = at91_clk_register_h32mx(regmap, name, parent_name);
188 if (IS_ERR(hw))
189 return;
190
191 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
192 }
193 CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
194 of_sama5d4_clk_h32mx_setup);
195 #endif /* CONFIG_HAVE_AT91_H32MX */
196
197 #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
198 #define I2S_BUS_NR 2
199
of_sama5d2_clk_i2s_mux_setup(struct device_node * np)200 static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
201 {
202 struct regmap *regmap_sfr;
203 u8 bus_id;
204 const char *parent_names[2];
205 struct device_node *i2s_mux_np;
206 struct clk_hw *hw;
207 int ret;
208
209 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
210 if (IS_ERR(regmap_sfr))
211 return;
212
213 for_each_child_of_node(np, i2s_mux_np) {
214 if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
215 continue;
216
217 if (bus_id > I2S_BUS_NR)
218 continue;
219
220 ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
221 if (ret != 2)
222 continue;
223
224 hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
225 parent_names, 2, bus_id);
226 if (IS_ERR(hw))
227 continue;
228
229 of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
230 }
231 }
232 CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
233 of_sama5d2_clk_i2s_mux_setup);
234 #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
235
of_at91rm9200_clk_main_osc_setup(struct device_node * np)236 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
237 {
238 struct clk_hw *hw;
239 const char *name = np->name;
240 const char *parent_name;
241 struct regmap *regmap;
242 bool bypass;
243
244 of_property_read_string(np, "clock-output-names", &name);
245 bypass = of_property_read_bool(np, "atmel,osc-bypass");
246 parent_name = of_clk_get_parent_name(np, 0);
247
248 regmap = syscon_node_to_regmap(of_get_parent(np));
249 if (IS_ERR(regmap))
250 return;
251
252 hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
253 if (IS_ERR(hw))
254 return;
255
256 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
257 }
258 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
259 of_at91rm9200_clk_main_osc_setup);
260
of_at91sam9x5_clk_main_rc_osc_setup(struct device_node * np)261 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
262 {
263 struct clk_hw *hw;
264 u32 frequency = 0;
265 u32 accuracy = 0;
266 const char *name = np->name;
267 struct regmap *regmap;
268
269 of_property_read_string(np, "clock-output-names", &name);
270 of_property_read_u32(np, "clock-frequency", &frequency);
271 of_property_read_u32(np, "clock-accuracy", &accuracy);
272
273 regmap = syscon_node_to_regmap(of_get_parent(np));
274 if (IS_ERR(regmap))
275 return;
276
277 hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
278 if (IS_ERR(hw))
279 return;
280
281 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
282 }
283 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
284 of_at91sam9x5_clk_main_rc_osc_setup);
285
of_at91rm9200_clk_main_setup(struct device_node * np)286 static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
287 {
288 struct clk_hw *hw;
289 const char *parent_name;
290 const char *name = np->name;
291 struct regmap *regmap;
292
293 parent_name = of_clk_get_parent_name(np, 0);
294 of_property_read_string(np, "clock-output-names", &name);
295
296 regmap = syscon_node_to_regmap(of_get_parent(np));
297 if (IS_ERR(regmap))
298 return;
299
300 hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
301 if (IS_ERR(hw))
302 return;
303
304 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
305 }
306 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
307 of_at91rm9200_clk_main_setup);
308
of_at91sam9x5_clk_main_setup(struct device_node * np)309 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
310 {
311 struct clk_hw *hw;
312 const char *parent_names[2];
313 unsigned int num_parents;
314 const char *name = np->name;
315 struct regmap *regmap;
316
317 num_parents = of_clk_get_parent_count(np);
318 if (num_parents == 0 || num_parents > 2)
319 return;
320
321 of_clk_parent_fill(np, parent_names, num_parents);
322 regmap = syscon_node_to_regmap(of_get_parent(np));
323 if (IS_ERR(regmap))
324 return;
325
326 of_property_read_string(np, "clock-output-names", &name);
327
328 hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
329 num_parents);
330 if (IS_ERR(hw))
331 return;
332
333 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
334 }
335 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
336 of_at91sam9x5_clk_main_setup);
337
338 static struct clk_master_characteristics * __init
of_at91_clk_master_get_characteristics(struct device_node * np)339 of_at91_clk_master_get_characteristics(struct device_node *np)
340 {
341 struct clk_master_characteristics *characteristics;
342
343 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
344 if (!characteristics)
345 return NULL;
346
347 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
348 goto out_free_characteristics;
349
350 of_property_read_u32_array(np, "atmel,clk-divisors",
351 characteristics->divisors, 4);
352
353 characteristics->have_div3_pres =
354 of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
355
356 return characteristics;
357
358 out_free_characteristics:
359 kfree(characteristics);
360 return NULL;
361 }
362
363 static void __init
of_at91_clk_master_setup(struct device_node * np,const struct clk_master_layout * layout)364 of_at91_clk_master_setup(struct device_node *np,
365 const struct clk_master_layout *layout)
366 {
367 struct clk_hw *hw;
368 unsigned int num_parents;
369 const char *parent_names[MASTER_SOURCE_MAX];
370 const char *name = np->name;
371 struct clk_master_characteristics *characteristics;
372 struct regmap *regmap;
373
374 num_parents = of_clk_get_parent_count(np);
375 if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
376 return;
377
378 of_clk_parent_fill(np, parent_names, num_parents);
379
380 of_property_read_string(np, "clock-output-names", &name);
381
382 characteristics = of_at91_clk_master_get_characteristics(np);
383 if (!characteristics)
384 return;
385
386 regmap = syscon_node_to_regmap(of_get_parent(np));
387 if (IS_ERR(regmap))
388 return;
389
390 hw = at91_clk_register_master(regmap, name, num_parents,
391 parent_names, layout,
392 characteristics);
393 if (IS_ERR(hw))
394 goto out_free_characteristics;
395
396 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
397 return;
398
399 out_free_characteristics:
400 kfree(characteristics);
401 }
402
of_at91rm9200_clk_master_setup(struct device_node * np)403 static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
404 {
405 of_at91_clk_master_setup(np, &at91rm9200_master_layout);
406 }
407 CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
408 of_at91rm9200_clk_master_setup);
409
of_at91sam9x5_clk_master_setup(struct device_node * np)410 static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
411 {
412 of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
413 }
414 CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
415 of_at91sam9x5_clk_master_setup);
416
417 static void __init
of_at91_clk_periph_setup(struct device_node * np,u8 type)418 of_at91_clk_periph_setup(struct device_node *np, u8 type)
419 {
420 int num;
421 u32 id;
422 struct clk_hw *hw;
423 const char *parent_name;
424 const char *name;
425 struct device_node *periphclknp;
426 struct regmap *regmap;
427
428 parent_name = of_clk_get_parent_name(np, 0);
429 if (!parent_name)
430 return;
431
432 num = of_get_child_count(np);
433 if (!num || num > PERIPHERAL_MAX)
434 return;
435
436 regmap = syscon_node_to_regmap(of_get_parent(np));
437 if (IS_ERR(regmap))
438 return;
439
440 for_each_child_of_node(np, periphclknp) {
441 if (of_property_read_u32(periphclknp, "reg", &id))
442 continue;
443
444 if (id >= PERIPHERAL_MAX)
445 continue;
446
447 if (of_property_read_string(np, "clock-output-names", &name))
448 name = periphclknp->name;
449
450 if (type == PERIPHERAL_AT91RM9200) {
451 hw = at91_clk_register_peripheral(regmap, name,
452 parent_name, id);
453 } else {
454 struct clk_range range = CLK_RANGE(0, 0);
455
456 of_at91_get_clk_range(periphclknp,
457 "atmel,clk-output-range",
458 &range);
459
460 hw = at91_clk_register_sam9x5_peripheral(regmap,
461 &pmc_pcr_lock,
462 &dt_pcr_layout,
463 name,
464 parent_name,
465 id, &range);
466 }
467
468 if (IS_ERR(hw))
469 continue;
470
471 of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
472 }
473 }
474
of_at91rm9200_clk_periph_setup(struct device_node * np)475 static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
476 {
477 of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
478 }
479 CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
480 of_at91rm9200_clk_periph_setup);
481
of_at91sam9x5_clk_periph_setup(struct device_node * np)482 static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
483 {
484 of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
485 }
486 CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
487 of_at91sam9x5_clk_periph_setup);
488
489 static struct clk_pll_characteristics * __init
of_at91_clk_pll_get_characteristics(struct device_node * np)490 of_at91_clk_pll_get_characteristics(struct device_node *np)
491 {
492 int i;
493 int offset;
494 u32 tmp;
495 int num_output;
496 u32 num_cells;
497 struct clk_range input;
498 struct clk_range *output;
499 u8 *out = NULL;
500 u16 *icpll = NULL;
501 struct clk_pll_characteristics *characteristics;
502
503 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
504 return NULL;
505
506 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
507 &num_cells))
508 return NULL;
509
510 if (num_cells < 2 || num_cells > 4)
511 return NULL;
512
513 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
514 return NULL;
515 num_output = tmp / (sizeof(u32) * num_cells);
516
517 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
518 if (!characteristics)
519 return NULL;
520
521 output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
522 if (!output)
523 goto out_free_characteristics;
524
525 if (num_cells > 2) {
526 out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
527 if (!out)
528 goto out_free_output;
529 }
530
531 if (num_cells > 3) {
532 icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
533 if (!icpll)
534 goto out_free_output;
535 }
536
537 for (i = 0; i < num_output; i++) {
538 offset = i * num_cells;
539 if (of_property_read_u32_index(np,
540 "atmel,pll-clk-output-ranges",
541 offset, &tmp))
542 goto out_free_output;
543 output[i].min = tmp;
544 if (of_property_read_u32_index(np,
545 "atmel,pll-clk-output-ranges",
546 offset + 1, &tmp))
547 goto out_free_output;
548 output[i].max = tmp;
549
550 if (num_cells == 2)
551 continue;
552
553 if (of_property_read_u32_index(np,
554 "atmel,pll-clk-output-ranges",
555 offset + 2, &tmp))
556 goto out_free_output;
557 out[i] = tmp;
558
559 if (num_cells == 3)
560 continue;
561
562 if (of_property_read_u32_index(np,
563 "atmel,pll-clk-output-ranges",
564 offset + 3, &tmp))
565 goto out_free_output;
566 icpll[i] = tmp;
567 }
568
569 characteristics->input = input;
570 characteristics->num_output = num_output;
571 characteristics->output = output;
572 characteristics->out = out;
573 characteristics->icpll = icpll;
574 return characteristics;
575
576 out_free_output:
577 kfree(icpll);
578 kfree(out);
579 kfree(output);
580 out_free_characteristics:
581 kfree(characteristics);
582 return NULL;
583 }
584
585 static void __init
of_at91_clk_pll_setup(struct device_node * np,const struct clk_pll_layout * layout)586 of_at91_clk_pll_setup(struct device_node *np,
587 const struct clk_pll_layout *layout)
588 {
589 u32 id;
590 struct clk_hw *hw;
591 struct regmap *regmap;
592 const char *parent_name;
593 const char *name = np->name;
594 struct clk_pll_characteristics *characteristics;
595
596 if (of_property_read_u32(np, "reg", &id))
597 return;
598
599 parent_name = of_clk_get_parent_name(np, 0);
600
601 of_property_read_string(np, "clock-output-names", &name);
602
603 regmap = syscon_node_to_regmap(of_get_parent(np));
604 if (IS_ERR(regmap))
605 return;
606
607 characteristics = of_at91_clk_pll_get_characteristics(np);
608 if (!characteristics)
609 return;
610
611 hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
612 characteristics);
613 if (IS_ERR(hw))
614 goto out_free_characteristics;
615
616 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
617 return;
618
619 out_free_characteristics:
620 kfree(characteristics);
621 }
622
of_at91rm9200_clk_pll_setup(struct device_node * np)623 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
624 {
625 of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
626 }
627 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
628 of_at91rm9200_clk_pll_setup);
629
of_at91sam9g45_clk_pll_setup(struct device_node * np)630 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
631 {
632 of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
633 }
634 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
635 of_at91sam9g45_clk_pll_setup);
636
of_at91sam9g20_clk_pllb_setup(struct device_node * np)637 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
638 {
639 of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
640 }
641 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
642 of_at91sam9g20_clk_pllb_setup);
643
of_sama5d3_clk_pll_setup(struct device_node * np)644 static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
645 {
646 of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
647 }
648 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
649 of_sama5d3_clk_pll_setup);
650
651 static void __init
of_at91sam9x5_clk_plldiv_setup(struct device_node * np)652 of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
653 {
654 struct clk_hw *hw;
655 const char *parent_name;
656 const char *name = np->name;
657 struct regmap *regmap;
658
659 parent_name = of_clk_get_parent_name(np, 0);
660
661 of_property_read_string(np, "clock-output-names", &name);
662
663 regmap = syscon_node_to_regmap(of_get_parent(np));
664 if (IS_ERR(regmap))
665 return;
666
667 hw = at91_clk_register_plldiv(regmap, name, parent_name);
668 if (IS_ERR(hw))
669 return;
670
671 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
672 }
673 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
674 of_at91sam9x5_clk_plldiv_setup);
675
676 static void __init
of_at91_clk_prog_setup(struct device_node * np,const struct clk_programmable_layout * layout)677 of_at91_clk_prog_setup(struct device_node *np,
678 const struct clk_programmable_layout *layout)
679 {
680 int num;
681 u32 id;
682 struct clk_hw *hw;
683 unsigned int num_parents;
684 const char *parent_names[PROG_SOURCE_MAX];
685 const char *name;
686 struct device_node *progclknp;
687 struct regmap *regmap;
688
689 num_parents = of_clk_get_parent_count(np);
690 if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
691 return;
692
693 of_clk_parent_fill(np, parent_names, num_parents);
694
695 num = of_get_child_count(np);
696 if (!num || num > (PROG_ID_MAX + 1))
697 return;
698
699 regmap = syscon_node_to_regmap(of_get_parent(np));
700 if (IS_ERR(regmap))
701 return;
702
703 for_each_child_of_node(np, progclknp) {
704 if (of_property_read_u32(progclknp, "reg", &id))
705 continue;
706
707 if (of_property_read_string(np, "clock-output-names", &name))
708 name = progclknp->name;
709
710 hw = at91_clk_register_programmable(regmap, name,
711 parent_names, num_parents,
712 id, layout);
713 if (IS_ERR(hw))
714 continue;
715
716 of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
717 }
718 }
719
of_at91rm9200_clk_prog_setup(struct device_node * np)720 static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
721 {
722 of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout);
723 }
724 CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
725 of_at91rm9200_clk_prog_setup);
726
of_at91sam9g45_clk_prog_setup(struct device_node * np)727 static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
728 {
729 of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout);
730 }
731 CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
732 of_at91sam9g45_clk_prog_setup);
733
of_at91sam9x5_clk_prog_setup(struct device_node * np)734 static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
735 {
736 of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout);
737 }
738 CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
739 of_at91sam9x5_clk_prog_setup);
740
of_at91sam9260_clk_slow_setup(struct device_node * np)741 static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
742 {
743 struct clk_hw *hw;
744 const char *parent_names[2];
745 unsigned int num_parents;
746 const char *name = np->name;
747 struct regmap *regmap;
748
749 num_parents = of_clk_get_parent_count(np);
750 if (num_parents != 2)
751 return;
752
753 of_clk_parent_fill(np, parent_names, num_parents);
754 regmap = syscon_node_to_regmap(of_get_parent(np));
755 if (IS_ERR(regmap))
756 return;
757
758 of_property_read_string(np, "clock-output-names", &name);
759
760 hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
761 num_parents);
762 if (IS_ERR(hw))
763 return;
764
765 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
766 }
767 CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
768 of_at91sam9260_clk_slow_setup);
769
770 #ifdef CONFIG_HAVE_AT91_SMD
771 #define SMD_SOURCE_MAX 2
772
of_at91sam9x5_clk_smd_setup(struct device_node * np)773 static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
774 {
775 struct clk_hw *hw;
776 unsigned int num_parents;
777 const char *parent_names[SMD_SOURCE_MAX];
778 const char *name = np->name;
779 struct regmap *regmap;
780
781 num_parents = of_clk_get_parent_count(np);
782 if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
783 return;
784
785 of_clk_parent_fill(np, parent_names, num_parents);
786
787 of_property_read_string(np, "clock-output-names", &name);
788
789 regmap = syscon_node_to_regmap(of_get_parent(np));
790 if (IS_ERR(regmap))
791 return;
792
793 hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
794 num_parents);
795 if (IS_ERR(hw))
796 return;
797
798 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
799 }
800 CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
801 of_at91sam9x5_clk_smd_setup);
802 #endif /* CONFIG_HAVE_AT91_SMD */
803
of_at91rm9200_clk_sys_setup(struct device_node * np)804 static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
805 {
806 int num;
807 u32 id;
808 struct clk_hw *hw;
809 const char *name;
810 struct device_node *sysclknp;
811 const char *parent_name;
812 struct regmap *regmap;
813
814 num = of_get_child_count(np);
815 if (num > (SYSTEM_MAX_ID + 1))
816 return;
817
818 regmap = syscon_node_to_regmap(of_get_parent(np));
819 if (IS_ERR(regmap))
820 return;
821
822 for_each_child_of_node(np, sysclknp) {
823 if (of_property_read_u32(sysclknp, "reg", &id))
824 continue;
825
826 if (of_property_read_string(np, "clock-output-names", &name))
827 name = sysclknp->name;
828
829 parent_name = of_clk_get_parent_name(sysclknp, 0);
830
831 hw = at91_clk_register_system(regmap, name, parent_name, id);
832 if (IS_ERR(hw))
833 continue;
834
835 of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
836 }
837 }
838 CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
839 of_at91rm9200_clk_sys_setup);
840
841 #ifdef CONFIG_HAVE_AT91_USB_CLK
842 #define USB_SOURCE_MAX 2
843
of_at91sam9x5_clk_usb_setup(struct device_node * np)844 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
845 {
846 struct clk_hw *hw;
847 unsigned int num_parents;
848 const char *parent_names[USB_SOURCE_MAX];
849 const char *name = np->name;
850 struct regmap *regmap;
851
852 num_parents = of_clk_get_parent_count(np);
853 if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
854 return;
855
856 of_clk_parent_fill(np, parent_names, num_parents);
857
858 of_property_read_string(np, "clock-output-names", &name);
859
860 regmap = syscon_node_to_regmap(of_get_parent(np));
861 if (IS_ERR(regmap))
862 return;
863
864 hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
865 num_parents);
866 if (IS_ERR(hw))
867 return;
868
869 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
870 }
871 CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
872 of_at91sam9x5_clk_usb_setup);
873
of_at91sam9n12_clk_usb_setup(struct device_node * np)874 static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
875 {
876 struct clk_hw *hw;
877 const char *parent_name;
878 const char *name = np->name;
879 struct regmap *regmap;
880
881 parent_name = of_clk_get_parent_name(np, 0);
882 if (!parent_name)
883 return;
884
885 of_property_read_string(np, "clock-output-names", &name);
886
887 regmap = syscon_node_to_regmap(of_get_parent(np));
888 if (IS_ERR(regmap))
889 return;
890
891 hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
892 if (IS_ERR(hw))
893 return;
894
895 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
896 }
897 CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
898 of_at91sam9n12_clk_usb_setup);
899
of_at91rm9200_clk_usb_setup(struct device_node * np)900 static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
901 {
902 struct clk_hw *hw;
903 const char *parent_name;
904 const char *name = np->name;
905 u32 divisors[4] = {0, 0, 0, 0};
906 struct regmap *regmap;
907
908 parent_name = of_clk_get_parent_name(np, 0);
909 if (!parent_name)
910 return;
911
912 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
913 if (!divisors[0])
914 return;
915
916 of_property_read_string(np, "clock-output-names", &name);
917
918 regmap = syscon_node_to_regmap(of_get_parent(np));
919 if (IS_ERR(regmap))
920 return;
921 hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
922 if (IS_ERR(hw))
923 return;
924
925 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
926 }
927 CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
928 of_at91rm9200_clk_usb_setup);
929 #endif /* CONFIG_HAVE_AT91_USB_CLK */
930
931 #ifdef CONFIG_HAVE_AT91_UTMI
of_at91sam9x5_clk_utmi_setup(struct device_node * np)932 static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
933 {
934 struct clk_hw *hw;
935 const char *parent_name;
936 const char *name = np->name;
937 struct regmap *regmap_pmc, *regmap_sfr;
938
939 parent_name = of_clk_get_parent_name(np, 0);
940
941 of_property_read_string(np, "clock-output-names", &name);
942
943 regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
944 if (IS_ERR(regmap_pmc))
945 return;
946
947 /*
948 * If the device supports different mainck rates, this value has to be
949 * set in the UTMI Clock Trimming register.
950 * - 9x5: mainck supports several rates but it is indicated that a
951 * 12 MHz is needed in case of USB.
952 * - sama5d3 and sama5d2: mainck supports several rates. Configuring
953 * the FREQ field of the UTMI Clock Trimming register is mandatory.
954 * - sama5d4: mainck is at 12 MHz.
955 *
956 * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
957 */
958 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
959 if (IS_ERR(regmap_sfr)) {
960 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
961 if (IS_ERR(regmap_sfr))
962 regmap_sfr = NULL;
963 }
964
965 hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
966 if (IS_ERR(hw))
967 return;
968
969 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
970 }
971 CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
972 of_at91sam9x5_clk_utmi_setup);
973 #endif /* CONFIG_HAVE_AT91_UTMI */
974