1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
5
6 #include <dt-bindings/clock/at91.h>
7
8 #include "pmc.h"
9
10 static const struct clk_master_characteristics mck_characteristics = {
11 .output = { .min = 124000000, .max = 166000000 },
12 .divisors = { 1, 2, 4, 3 },
13 };
14
15 static u8 plla_out[] = { 0 };
16
17 static u16 plla_icpll[] = { 0 };
18
19 static const struct clk_range plla_outputs[] = {
20 { .min = 600000000, .max = 1200000000 },
21 };
22
23 static const struct clk_pll_characteristics plla_characteristics = {
24 .input = { .min = 12000000, .max = 24000000 },
25 .num_output = ARRAY_SIZE(plla_outputs),
26 .output = plla_outputs,
27 .icpll = plla_icpll,
28 .out = plla_out,
29 };
30
31 static const struct clk_pcr_layout sama5d2_pcr_layout = {
32 .offset = 0x10c,
33 .cmd = BIT(12),
34 .gckcss_mask = GENMASK(10, 8),
35 .pid_mask = GENMASK(6, 0),
36 };
37
38 static const struct {
39 char *n;
40 char *p;
41 u8 id;
42 } sama5d2_systemck[] = {
43 { .n = "ddrck", .p = "masterck", .id = 2 },
44 { .n = "lcdck", .p = "masterck", .id = 3 },
45 { .n = "uhpck", .p = "usbck", .id = 6 },
46 { .n = "udpck", .p = "usbck", .id = 7 },
47 { .n = "pck0", .p = "prog0", .id = 8 },
48 { .n = "pck1", .p = "prog1", .id = 9 },
49 { .n = "pck2", .p = "prog2", .id = 10 },
50 { .n = "iscck", .p = "masterck", .id = 18 },
51 };
52
53 static const struct {
54 char *n;
55 u8 id;
56 struct clk_range r;
57 } sama5d2_periph32ck[] = {
58 { .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, },
59 { .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, },
60 { .n = "matrix1_clk", .id = 14, },
61 { .n = "hsmc_clk", .id = 17, },
62 { .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, },
63 { .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, },
64 { .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, },
65 { .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, },
66 { .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, },
67 { .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, },
68 { .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, },
69 { .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, },
70 { .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, },
71 { .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, },
72 { .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, },
73 { .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
74 { .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, },
75 { .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, },
76 { .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, },
77 { .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
78 { .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
79 { .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
80 { .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
81 { .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
82 { .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, },
83 { .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, },
84 { .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, },
85 { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, },
86 { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, },
87 { .n = "securam_clk", .id = 51, },
88 { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, },
89 { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, },
90 { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, },
91 { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, },
92 { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, },
93 };
94
95 static const struct {
96 char *n;
97 u8 id;
98 } sama5d2_periphck[] = {
99 { .n = "dma0_clk", .id = 6, },
100 { .n = "dma1_clk", .id = 7, },
101 { .n = "aes_clk", .id = 9, },
102 { .n = "aesb_clk", .id = 10, },
103 { .n = "sha_clk", .id = 12, },
104 { .n = "mpddr_clk", .id = 13, },
105 { .n = "matrix0_clk", .id = 15, },
106 { .n = "sdmmc0_hclk", .id = 31, },
107 { .n = "sdmmc1_hclk", .id = 32, },
108 { .n = "lcdc_clk", .id = 45, },
109 { .n = "isc_clk", .id = 46, },
110 { .n = "qspi0_clk", .id = 52, },
111 { .n = "qspi1_clk", .id = 53, },
112 };
113
114 static const struct {
115 char *n;
116 u8 id;
117 struct clk_range r;
118 int chg_pid;
119 } sama5d2_gck[] = {
120 { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
121 { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
122 { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
123 { .n = "tcb1_gclk", .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
124 { .n = "pwm_gclk", .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
125 { .n = "isc_gclk", .id = 46, .chg_pid = INT_MIN, },
126 { .n = "pdmic_gclk", .id = 48, .chg_pid = INT_MIN, },
127 { .n = "i2s0_gclk", .id = 54, .chg_pid = 5, },
128 { .n = "i2s1_gclk", .id = 55, .chg_pid = 5, },
129 { .n = "can0_gclk", .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
130 { .n = "can1_gclk", .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
131 { .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, },
132 };
133
134 static const struct clk_programmable_layout sama5d2_programmable_layout = {
135 .pres_mask = 0xff,
136 .pres_shift = 4,
137 .css_mask = 0x7,
138 .have_slck_mck = 0,
139 .is_pres_direct = 1,
140 };
141
sama5d2_pmc_setup(struct device_node * np)142 static void __init sama5d2_pmc_setup(struct device_node *np)
143 {
144 struct clk_range range = CLK_RANGE(0, 0);
145 const char *slck_name, *mainxtal_name;
146 struct pmc_data *sama5d2_pmc;
147 const char *parent_names[6];
148 struct regmap *regmap, *regmap_sfr;
149 struct clk_hw *hw;
150 int i;
151 bool bypass;
152
153 i = of_property_match_string(np, "clock-names", "slow_clk");
154 if (i < 0)
155 return;
156
157 slck_name = of_clk_get_parent_name(np, i);
158
159 i = of_property_match_string(np, "clock-names", "main_xtal");
160 if (i < 0)
161 return;
162 mainxtal_name = of_clk_get_parent_name(np, i);
163
164 regmap = device_node_to_regmap(np);
165 if (IS_ERR(regmap))
166 return;
167
168 sama5d2_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
169 nck(sama5d2_systemck),
170 nck(sama5d2_periph32ck),
171 nck(sama5d2_gck));
172 if (!sama5d2_pmc)
173 return;
174
175 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
176 100000000);
177 if (IS_ERR(hw))
178 goto err_free;
179
180 bypass = of_property_read_bool(np, "atmel,osc-bypass");
181
182 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
183 bypass);
184 if (IS_ERR(hw))
185 goto err_free;
186
187 parent_names[0] = "main_rc_osc";
188 parent_names[1] = "main_osc";
189 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
190 if (IS_ERR(hw))
191 goto err_free;
192
193 sama5d2_pmc->chws[PMC_MAIN] = hw;
194
195 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
196 &sama5d3_pll_layout, &plla_characteristics);
197 if (IS_ERR(hw))
198 goto err_free;
199
200 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
201 if (IS_ERR(hw))
202 goto err_free;
203
204 hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
205 "mainck");
206 if (IS_ERR(hw))
207 goto err_free;
208
209 hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
210 "audiopll_fracck");
211 if (IS_ERR(hw))
212 goto err_free;
213
214 hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
215 "audiopll_fracck");
216 if (IS_ERR(hw))
217 goto err_free;
218
219 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
220 if (IS_ERR(regmap_sfr))
221 regmap_sfr = NULL;
222
223 hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
224 if (IS_ERR(hw))
225 goto err_free;
226
227 sama5d2_pmc->chws[PMC_UTMI] = hw;
228
229 parent_names[0] = slck_name;
230 parent_names[1] = "mainck";
231 parent_names[2] = "plladivck";
232 parent_names[3] = "utmick";
233 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
234 &at91sam9x5_master_layout,
235 &mck_characteristics);
236 if (IS_ERR(hw))
237 goto err_free;
238
239 sama5d2_pmc->chws[PMC_MCK] = hw;
240
241 hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
242 if (IS_ERR(hw))
243 goto err_free;
244
245 sama5d2_pmc->chws[PMC_MCK2] = hw;
246
247 parent_names[0] = "plladivck";
248 parent_names[1] = "utmick";
249 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
250 if (IS_ERR(hw))
251 goto err_free;
252
253 parent_names[0] = slck_name;
254 parent_names[1] = "mainck";
255 parent_names[2] = "plladivck";
256 parent_names[3] = "utmick";
257 parent_names[4] = "masterck";
258 parent_names[5] = "audiopll_pmcck";
259 for (i = 0; i < 3; i++) {
260 char name[6];
261
262 snprintf(name, sizeof(name), "prog%d", i);
263
264 hw = at91_clk_register_programmable(regmap, name,
265 parent_names, 6, i,
266 &sama5d2_programmable_layout);
267 if (IS_ERR(hw))
268 goto err_free;
269 }
270
271 for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
272 hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
273 sama5d2_systemck[i].p,
274 sama5d2_systemck[i].id);
275 if (IS_ERR(hw))
276 goto err_free;
277
278 sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
279 }
280
281 for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
282 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
283 &sama5d2_pcr_layout,
284 sama5d2_periphck[i].n,
285 "masterck",
286 sama5d2_periphck[i].id,
287 &range);
288 if (IS_ERR(hw))
289 goto err_free;
290
291 sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
292 }
293
294 for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
295 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
296 &sama5d2_pcr_layout,
297 sama5d2_periph32ck[i].n,
298 "h32mxck",
299 sama5d2_periph32ck[i].id,
300 &sama5d2_periph32ck[i].r);
301 if (IS_ERR(hw))
302 goto err_free;
303
304 sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
305 }
306
307 parent_names[0] = slck_name;
308 parent_names[1] = "mainck";
309 parent_names[2] = "plladivck";
310 parent_names[3] = "utmick";
311 parent_names[4] = "masterck";
312 parent_names[5] = "audiopll_pmcck";
313 for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
314 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
315 &sama5d2_pcr_layout,
316 sama5d2_gck[i].n,
317 parent_names, 6,
318 sama5d2_gck[i].id,
319 &sama5d2_gck[i].r,
320 sama5d2_gck[i].chg_pid);
321 if (IS_ERR(hw))
322 goto err_free;
323
324 sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
325 }
326
327 if (regmap_sfr) {
328 parent_names[0] = "i2s0_clk";
329 parent_names[1] = "i2s0_gclk";
330 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
331 parent_names, 2, 0);
332 if (IS_ERR(hw))
333 goto err_free;
334
335 sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
336
337 parent_names[0] = "i2s1_clk";
338 parent_names[1] = "i2s1_gclk";
339 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
340 parent_names, 2, 1);
341 if (IS_ERR(hw))
342 goto err_free;
343
344 sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
345 }
346
347 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
348
349 return;
350
351 err_free:
352 pmc_data_free(sama5d2_pmc);
353 }
354 CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
355