1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Ingenic JZ4725B SoC CGU driver
4 *
5 * Copyright (C) 2018 Paul Cercueil
6 * Author: Paul Cercueil <paul@crapouillou.net>
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/of.h>
12 #include <dt-bindings/clock/jz4725b-cgu.h>
13 #include "cgu.h"
14 #include "pm.h"
15
16 /* CGU register offsets */
17 #define CGU_REG_CPCCR 0x00
18 #define CGU_REG_LCR 0x04
19 #define CGU_REG_CPPCR 0x10
20 #define CGU_REG_CLKGR 0x20
21 #define CGU_REG_OPCR 0x24
22 #define CGU_REG_I2SCDR 0x60
23 #define CGU_REG_LPCDR 0x64
24 #define CGU_REG_MSCCDR 0x68
25 #define CGU_REG_SSICDR 0x74
26 #define CGU_REG_CIMCDR 0x78
27
28 /* bits within the LCR register */
29 #define LCR_SLEEP BIT(0)
30
31 static struct ingenic_cgu *cgu;
32
33 static const s8 pll_od_encoding[4] = {
34 0x0, 0x1, -1, 0x3,
35 };
36
37 static const u8 jz4725b_cgu_cpccr_div_table[] = {
38 1, 2, 3, 4, 6, 8,
39 };
40
41 static const u8 jz4725b_cgu_pll_half_div_table[] = {
42 2, 1,
43 };
44
45 static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
46
47 /* External clocks */
48
49 [JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
50 [JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
51
52 [JZ4725B_CLK_PLL] = {
53 "pll", CGU_CLK_PLL,
54 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
55 .pll = {
56 .reg = CGU_REG_CPPCR,
57 .m_shift = 23,
58 .m_bits = 9,
59 .m_offset = 2,
60 .n_shift = 18,
61 .n_bits = 5,
62 .n_offset = 2,
63 .od_shift = 16,
64 .od_bits = 2,
65 .od_max = 4,
66 .od_encoding = pll_od_encoding,
67 .stable_bit = 10,
68 .bypass_bit = 9,
69 .enable_bit = 8,
70 },
71 },
72
73 /* Muxes & dividers */
74
75 [JZ4725B_CLK_PLL_HALF] = {
76 "pll half", CGU_CLK_DIV,
77 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
78 .div = {
79 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
80 jz4725b_cgu_pll_half_div_table,
81 },
82 },
83
84 [JZ4725B_CLK_CCLK] = {
85 "cclk", CGU_CLK_DIV,
86 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
87 .div = {
88 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
89 jz4725b_cgu_cpccr_div_table,
90 },
91 },
92
93 [JZ4725B_CLK_HCLK] = {
94 "hclk", CGU_CLK_DIV,
95 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
96 .div = {
97 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
98 jz4725b_cgu_cpccr_div_table,
99 },
100 },
101
102 [JZ4725B_CLK_PCLK] = {
103 "pclk", CGU_CLK_DIV,
104 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
105 .div = {
106 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
107 jz4725b_cgu_cpccr_div_table,
108 },
109 },
110
111 [JZ4725B_CLK_MCLK] = {
112 "mclk", CGU_CLK_DIV,
113 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
114 .div = {
115 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
116 jz4725b_cgu_cpccr_div_table,
117 },
118 },
119
120 [JZ4725B_CLK_IPU] = {
121 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
122 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
123 .div = {
124 CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
125 jz4725b_cgu_cpccr_div_table,
126 },
127 .gate = { CGU_REG_CLKGR, 13 },
128 },
129
130 [JZ4725B_CLK_LCD] = {
131 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
132 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
133 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
134 .gate = { CGU_REG_CLKGR, 9 },
135 },
136
137 [JZ4725B_CLK_I2S] = {
138 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
139 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
140 .mux = { CGU_REG_CPCCR, 31, 1 },
141 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
142 },
143
144 [JZ4725B_CLK_SPI] = {
145 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
146 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
147 .mux = { CGU_REG_SSICDR, 31, 1 },
148 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
149 .gate = { CGU_REG_CLKGR, 4 },
150 },
151
152 [JZ4725B_CLK_MMC_MUX] = {
153 "mmc_mux", CGU_CLK_DIV,
154 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
155 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
156 },
157
158 [JZ4725B_CLK_UDC] = {
159 "udc", CGU_CLK_MUX | CGU_CLK_DIV,
160 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
161 .mux = { CGU_REG_CPCCR, 29, 1 },
162 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
163 },
164
165 /* Gate-only clocks */
166
167 [JZ4725B_CLK_UART] = {
168 "uart", CGU_CLK_GATE,
169 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
170 .gate = { CGU_REG_CLKGR, 0 },
171 },
172
173 [JZ4725B_CLK_DMA] = {
174 "dma", CGU_CLK_GATE,
175 .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
176 .gate = { CGU_REG_CLKGR, 12 },
177 },
178
179 [JZ4725B_CLK_ADC] = {
180 "adc", CGU_CLK_GATE,
181 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
182 .gate = { CGU_REG_CLKGR, 7 },
183 },
184
185 [JZ4725B_CLK_I2C] = {
186 "i2c", CGU_CLK_GATE,
187 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
188 .gate = { CGU_REG_CLKGR, 3 },
189 },
190
191 [JZ4725B_CLK_AIC] = {
192 "aic", CGU_CLK_GATE,
193 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
194 .gate = { CGU_REG_CLKGR, 5 },
195 },
196
197 [JZ4725B_CLK_MMC0] = {
198 "mmc0", CGU_CLK_GATE,
199 .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
200 .gate = { CGU_REG_CLKGR, 6 },
201 },
202
203 [JZ4725B_CLK_MMC1] = {
204 "mmc1", CGU_CLK_GATE,
205 .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
206 .gate = { CGU_REG_CLKGR, 16 },
207 },
208
209 [JZ4725B_CLK_BCH] = {
210 "bch", CGU_CLK_GATE,
211 .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
212 .gate = { CGU_REG_CLKGR, 11 },
213 },
214
215 [JZ4725B_CLK_TCU] = {
216 "tcu", CGU_CLK_GATE,
217 .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
218 .gate = { CGU_REG_CLKGR, 1 },
219 },
220
221 [JZ4725B_CLK_EXT512] = {
222 "ext/512", CGU_CLK_FIXDIV,
223 .parents = { JZ4725B_CLK_EXT },
224
225 /* Doc calls it EXT512, but it seems to be /256... */
226 .fixdiv = { 256 },
227 },
228
229 [JZ4725B_CLK_RTC] = {
230 "rtc", CGU_CLK_MUX,
231 .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
232 .mux = { CGU_REG_OPCR, 2, 1},
233 },
234
235 [JZ4725B_CLK_UDC_PHY] = {
236 "udc_phy", CGU_CLK_GATE,
237 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
238 .gate = { CGU_REG_OPCR, 6, true },
239 },
240 };
241
jz4725b_cgu_init(struct device_node * np)242 static void __init jz4725b_cgu_init(struct device_node *np)
243 {
244 int retval;
245
246 cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
247 ARRAY_SIZE(jz4725b_cgu_clocks), np);
248 if (!cgu) {
249 pr_err("%s: failed to initialise CGU\n", __func__);
250 return;
251 }
252
253 retval = ingenic_cgu_register_clocks(cgu);
254 if (retval)
255 pr_err("%s: failed to register CGU Clocks\n", __func__);
256
257 ingenic_cgu_register_syscore_ops(cgu);
258 }
259 CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
260