1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/err.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <soc/qcom/cmd-db.h>
14 #include <soc/qcom/rpmh.h>
15 #include <soc/qcom/tcs.h>
16
17 #include <dt-bindings/clock/qcom,rpmh.h>
18
19 #define CLK_RPMH_ARC_EN_OFFSET 0
20 #define CLK_RPMH_VRM_EN_OFFSET 4
21
22 /**
23 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
24 * @unit: divisor used to convert Hz value to an RPMh msg
25 * @width: multiplier used to convert Hz value to an RPMh msg
26 * @vcd: virtual clock domain that this bcm belongs to
27 * @reserved: reserved to pad the struct
28 */
29 struct bcm_db {
30 __le32 unit;
31 __le16 width;
32 u8 vcd;
33 u8 reserved;
34 };
35
36 /**
37 * struct clk_rpmh - individual rpmh clock data structure
38 * @hw: handle between common and hardware-specific interfaces
39 * @res_name: resource name for the rpmh clock
40 * @div: clock divider to compute the clock rate
41 * @res_addr: base address of the rpmh resource within the RPMh
42 * @res_on_val: rpmh clock enable value
43 * @state: rpmh clock requested state
44 * @aggr_state: rpmh clock aggregated state
45 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
46 * @valid_state_mask: mask to determine the state of the rpmh clock
47 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz
48 * @dev: device to which it is attached
49 * @peer: pointer to the clock rpmh sibling
50 */
51 struct clk_rpmh {
52 struct clk_hw hw;
53 const char *res_name;
54 u8 div;
55 u32 res_addr;
56 u32 res_on_val;
57 u32 state;
58 u32 aggr_state;
59 u32 last_sent_aggr_state;
60 u32 valid_state_mask;
61 u32 unit;
62 struct device *dev;
63 struct clk_rpmh *peer;
64 };
65
66 struct clk_rpmh_desc {
67 struct clk_hw **clks;
68 size_t num_clks;
69 };
70
71 static DEFINE_MUTEX(rpmh_clk_lock);
72
73 #define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
74 _res_en_offset, _res_on, _div) \
75 static struct clk_rpmh _platform##_##_name_active; \
76 static struct clk_rpmh _platform##_##_name = { \
77 .res_name = _res_name, \
78 .res_addr = _res_en_offset, \
79 .res_on_val = _res_on, \
80 .div = _div, \
81 .peer = &_platform##_##_name_active, \
82 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
83 BIT(RPMH_ACTIVE_ONLY_STATE) | \
84 BIT(RPMH_SLEEP_STATE)), \
85 .hw.init = &(struct clk_init_data){ \
86 .ops = &clk_rpmh_ops, \
87 .name = #_name, \
88 .parent_data = &(const struct clk_parent_data){ \
89 .fw_name = "xo", \
90 .name = "xo_board", \
91 }, \
92 .num_parents = 1, \
93 }, \
94 }; \
95 static struct clk_rpmh _platform##_##_name_active = { \
96 .res_name = _res_name, \
97 .res_addr = _res_en_offset, \
98 .res_on_val = _res_on, \
99 .div = _div, \
100 .peer = &_platform##_##_name, \
101 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
102 BIT(RPMH_ACTIVE_ONLY_STATE)), \
103 .hw.init = &(struct clk_init_data){ \
104 .ops = &clk_rpmh_ops, \
105 .name = #_name_active, \
106 .parent_data = &(const struct clk_parent_data){ \
107 .fw_name = "xo", \
108 .name = "xo_board", \
109 }, \
110 .num_parents = 1, \
111 }, \
112 }
113
114 #define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \
115 _res_on, _div) \
116 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
117 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
118
119 #define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \
120 _div) \
121 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
122 CLK_RPMH_VRM_EN_OFFSET, 1, _div)
123
124 #define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \
125 static struct clk_rpmh _platform##_##_name = { \
126 .res_name = _res_name, \
127 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \
128 .div = 1, \
129 .hw.init = &(struct clk_init_data){ \
130 .ops = &clk_rpmh_bcm_ops, \
131 .name = #_name, \
132 }, \
133 }
134
to_clk_rpmh(struct clk_hw * _hw)135 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
136 {
137 return container_of(_hw, struct clk_rpmh, hw);
138 }
139
has_state_changed(struct clk_rpmh * c,u32 state)140 static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
141 {
142 return (c->last_sent_aggr_state & BIT(state))
143 != (c->aggr_state & BIT(state));
144 }
145
clk_rpmh_send(struct clk_rpmh * c,enum rpmh_state state,struct tcs_cmd * cmd,bool wait)146 static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state,
147 struct tcs_cmd *cmd, bool wait)
148 {
149 if (wait)
150 return rpmh_write(c->dev, state, cmd, 1);
151
152 return rpmh_write_async(c->dev, state, cmd, 1);
153 }
154
clk_rpmh_send_aggregate_command(struct clk_rpmh * c)155 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
156 {
157 struct tcs_cmd cmd = { 0 };
158 u32 cmd_state, on_val;
159 enum rpmh_state state = RPMH_SLEEP_STATE;
160 int ret;
161 bool wait;
162
163 cmd.addr = c->res_addr;
164 cmd_state = c->aggr_state;
165 on_val = c->res_on_val;
166
167 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
168 if (has_state_changed(c, state)) {
169 if (cmd_state & BIT(state))
170 cmd.data = on_val;
171
172 wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE;
173 ret = clk_rpmh_send(c, state, &cmd, wait);
174 if (ret) {
175 dev_err(c->dev, "set %s state of %s failed: (%d)\n",
176 !state ? "sleep" :
177 state == RPMH_WAKE_ONLY_STATE ?
178 "wake" : "active", c->res_name, ret);
179 return ret;
180 }
181 }
182 }
183
184 c->last_sent_aggr_state = c->aggr_state;
185 c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
186
187 return 0;
188 }
189
190 /*
191 * Update state and aggregate state values based on enable value.
192 */
clk_rpmh_aggregate_state_send_command(struct clk_rpmh * c,bool enable)193 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
194 bool enable)
195 {
196 int ret;
197
198 /* Nothing required to be done if already off or on */
199 if (enable == c->state)
200 return 0;
201
202 c->state = enable ? c->valid_state_mask : 0;
203 c->aggr_state = c->state | c->peer->state;
204 c->peer->aggr_state = c->aggr_state;
205
206 ret = clk_rpmh_send_aggregate_command(c);
207 if (!ret)
208 return 0;
209
210 if (ret && enable)
211 c->state = 0;
212 else if (ret)
213 c->state = c->valid_state_mask;
214
215 WARN(1, "clk: %s failed to %s\n", c->res_name,
216 enable ? "enable" : "disable");
217 return ret;
218 }
219
clk_rpmh_prepare(struct clk_hw * hw)220 static int clk_rpmh_prepare(struct clk_hw *hw)
221 {
222 struct clk_rpmh *c = to_clk_rpmh(hw);
223 int ret = 0;
224
225 mutex_lock(&rpmh_clk_lock);
226 ret = clk_rpmh_aggregate_state_send_command(c, true);
227 mutex_unlock(&rpmh_clk_lock);
228
229 return ret;
230 };
231
clk_rpmh_unprepare(struct clk_hw * hw)232 static void clk_rpmh_unprepare(struct clk_hw *hw)
233 {
234 struct clk_rpmh *c = to_clk_rpmh(hw);
235
236 mutex_lock(&rpmh_clk_lock);
237 clk_rpmh_aggregate_state_send_command(c, false);
238 mutex_unlock(&rpmh_clk_lock);
239 };
240
clk_rpmh_recalc_rate(struct clk_hw * hw,unsigned long prate)241 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
242 unsigned long prate)
243 {
244 struct clk_rpmh *r = to_clk_rpmh(hw);
245
246 /*
247 * RPMh clocks have a fixed rate. Return static rate.
248 */
249 return prate / r->div;
250 }
251
252 static const struct clk_ops clk_rpmh_ops = {
253 .prepare = clk_rpmh_prepare,
254 .unprepare = clk_rpmh_unprepare,
255 .recalc_rate = clk_rpmh_recalc_rate,
256 };
257
clk_rpmh_bcm_send_cmd(struct clk_rpmh * c,bool enable)258 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
259 {
260 struct tcs_cmd cmd = { 0 };
261 u32 cmd_state;
262 int ret;
263
264 mutex_lock(&rpmh_clk_lock);
265
266 cmd_state = 0;
267 if (enable) {
268 cmd_state = 1;
269 if (c->aggr_state)
270 cmd_state = c->aggr_state;
271 }
272
273 if (c->last_sent_aggr_state == cmd_state) {
274 mutex_unlock(&rpmh_clk_lock);
275 return 0;
276 }
277
278 cmd.addr = c->res_addr;
279 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
280
281 ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable);
282 if (ret) {
283 dev_err(c->dev, "set active state of %s failed: (%d)\n",
284 c->res_name, ret);
285 mutex_unlock(&rpmh_clk_lock);
286 return ret;
287 }
288
289 c->last_sent_aggr_state = cmd_state;
290
291 mutex_unlock(&rpmh_clk_lock);
292
293 return 0;
294 }
295
clk_rpmh_bcm_prepare(struct clk_hw * hw)296 static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
297 {
298 struct clk_rpmh *c = to_clk_rpmh(hw);
299
300 return clk_rpmh_bcm_send_cmd(c, true);
301 };
302
clk_rpmh_bcm_unprepare(struct clk_hw * hw)303 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
304 {
305 struct clk_rpmh *c = to_clk_rpmh(hw);
306
307 clk_rpmh_bcm_send_cmd(c, false);
308 };
309
clk_rpmh_bcm_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)310 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
311 unsigned long parent_rate)
312 {
313 struct clk_rpmh *c = to_clk_rpmh(hw);
314
315 c->aggr_state = rate / c->unit;
316 /*
317 * Since any non-zero value sent to hw would result in enabling the
318 * clock, only send the value if the clock has already been prepared.
319 */
320 if (clk_hw_is_prepared(hw))
321 clk_rpmh_bcm_send_cmd(c, true);
322
323 return 0;
324 };
325
clk_rpmh_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)326 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
327 unsigned long *parent_rate)
328 {
329 return rate;
330 }
331
clk_rpmh_bcm_recalc_rate(struct clk_hw * hw,unsigned long prate)332 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
333 unsigned long prate)
334 {
335 struct clk_rpmh *c = to_clk_rpmh(hw);
336
337 return c->aggr_state * c->unit;
338 }
339
340 static const struct clk_ops clk_rpmh_bcm_ops = {
341 .prepare = clk_rpmh_bcm_prepare,
342 .unprepare = clk_rpmh_bcm_unprepare,
343 .set_rate = clk_rpmh_bcm_set_rate,
344 .round_rate = clk_rpmh_round_rate,
345 .recalc_rate = clk_rpmh_bcm_recalc_rate,
346 };
347
348 /* Resource name must match resource id present in cmd-db. */
349 DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
350 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
351 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
352 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
353 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
354 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
355 DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
356
357 static struct clk_hw *sdm845_rpmh_clocks[] = {
358 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
359 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
360 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
361 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
362 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
363 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
364 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
365 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
366 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
367 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
368 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
369 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
370 [RPMH_IPA_CLK] = &sdm845_ipa.hw,
371 };
372
373 static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
374 .clks = sdm845_rpmh_clocks,
375 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
376 };
377
378 DEFINE_CLK_RPMH_ARC(sm8150, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
379 DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
380 DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
381 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk1, rf_clk1_ao, "rfclka1", 1);
382 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk2, rf_clk2_ao, "rfclka2", 1);
383 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
384
385 static struct clk_hw *sm8150_rpmh_clocks[] = {
386 [RPMH_CXO_CLK] = &sm8150_bi_tcxo.hw,
387 [RPMH_CXO_CLK_A] = &sm8150_bi_tcxo_ao.hw,
388 [RPMH_LN_BB_CLK2] = &sm8150_ln_bb_clk2.hw,
389 [RPMH_LN_BB_CLK2_A] = &sm8150_ln_bb_clk2_ao.hw,
390 [RPMH_LN_BB_CLK3] = &sm8150_ln_bb_clk3.hw,
391 [RPMH_LN_BB_CLK3_A] = &sm8150_ln_bb_clk3_ao.hw,
392 [RPMH_RF_CLK1] = &sm8150_rf_clk1.hw,
393 [RPMH_RF_CLK1_A] = &sm8150_rf_clk1_ao.hw,
394 [RPMH_RF_CLK2] = &sm8150_rf_clk2.hw,
395 [RPMH_RF_CLK2_A] = &sm8150_rf_clk2_ao.hw,
396 [RPMH_RF_CLK3] = &sm8150_rf_clk3.hw,
397 [RPMH_RF_CLK3_A] = &sm8150_rf_clk3_ao.hw,
398 };
399
400 static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
401 .clks = sm8150_rpmh_clocks,
402 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
403 };
404
of_clk_rpmh_hw_get(struct of_phandle_args * clkspec,void * data)405 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
406 void *data)
407 {
408 struct clk_rpmh_desc *rpmh = data;
409 unsigned int idx = clkspec->args[0];
410
411 if (idx >= rpmh->num_clks) {
412 pr_err("%s: invalid index %u\n", __func__, idx);
413 return ERR_PTR(-EINVAL);
414 }
415
416 return rpmh->clks[idx];
417 }
418
clk_rpmh_probe(struct platform_device * pdev)419 static int clk_rpmh_probe(struct platform_device *pdev)
420 {
421 struct clk_hw **hw_clks;
422 struct clk_rpmh *rpmh_clk;
423 const struct clk_rpmh_desc *desc;
424 int ret, i;
425
426 desc = of_device_get_match_data(&pdev->dev);
427 if (!desc)
428 return -ENODEV;
429
430 hw_clks = desc->clks;
431
432 for (i = 0; i < desc->num_clks; i++) {
433 const char *name = hw_clks[i]->init->name;
434 u32 res_addr;
435 size_t aux_data_len;
436 const struct bcm_db *data;
437
438 rpmh_clk = to_clk_rpmh(hw_clks[i]);
439 res_addr = cmd_db_read_addr(rpmh_clk->res_name);
440 if (!res_addr) {
441 dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
442 rpmh_clk->res_name);
443 return -ENODEV;
444 }
445
446 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
447 if (IS_ERR(data)) {
448 ret = PTR_ERR(data);
449 dev_err(&pdev->dev,
450 "error reading RPMh aux data for %s (%d)\n",
451 rpmh_clk->res_name, ret);
452 return ret;
453 }
454
455 /* Convert unit from Khz to Hz */
456 if (aux_data_len == sizeof(*data))
457 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
458
459 rpmh_clk->res_addr += res_addr;
460 rpmh_clk->dev = &pdev->dev;
461
462 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
463 if (ret) {
464 dev_err(&pdev->dev, "failed to register %s\n", name);
465 return ret;
466 }
467 }
468
469 /* typecast to silence compiler warning */
470 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
471 (void *)desc);
472 if (ret) {
473 dev_err(&pdev->dev, "Failed to add clock provider\n");
474 return ret;
475 }
476
477 dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
478
479 return 0;
480 }
481
482 static const struct of_device_id clk_rpmh_match_table[] = {
483 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
484 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
485 { }
486 };
487 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
488
489 static struct platform_driver clk_rpmh_driver = {
490 .probe = clk_rpmh_probe,
491 .driver = {
492 .name = "clk-rpmh",
493 .of_match_table = clk_rpmh_match_table,
494 },
495 };
496
clk_rpmh_init(void)497 static int __init clk_rpmh_init(void)
498 {
499 return platform_driver_register(&clk_rpmh_driver);
500 }
501 subsys_initcall(clk_rpmh_init);
502
clk_rpmh_exit(void)503 static void __exit clk_rpmh_exit(void)
504 {
505 platform_driver_unregister(&clk_rpmh_driver);
506 }
507 module_exit(clk_rpmh_exit);
508
509 MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
510 MODULE_LICENSE("GPL v2");
511