1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/delay.h>
8 #include <linux/err.h>
9 #include <linux/jiffies.h>
10 #include <linux/kernel.h>
11 #include <linux/ktime.h>
12 #include <linux/pm_domain.h>
13 #include <linux/regmap.h>
14 #include <linux/reset-controller.h>
15 #include <linux/slab.h>
16 #include "gdsc.h"
17
18 #define PWR_ON_MASK BIT(31)
19 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
20 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
21 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
22 #define SW_OVERRIDE_MASK BIT(2)
23 #define HW_CONTROL_MASK BIT(1)
24 #define SW_COLLAPSE_MASK BIT(0)
25 #define GMEM_CLAMP_IO_MASK BIT(0)
26 #define GMEM_RESET_MASK BIT(4)
27
28 /* CFG_GDSCR */
29 #define GDSC_POWER_UP_COMPLETE BIT(16)
30 #define GDSC_POWER_DOWN_COMPLETE BIT(15)
31 #define CFG_GDSCR_OFFSET 0x4
32
33 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
34 #define EN_REST_WAIT_VAL 0x2
35 #define EN_FEW_WAIT_VAL 0x8
36 #define CLK_DIS_WAIT_VAL 0x2
37
38 /* Transition delay shifts */
39 #define EN_REST_WAIT_SHIFT 20
40 #define EN_FEW_WAIT_SHIFT 16
41 #define CLK_DIS_WAIT_SHIFT 12
42
43 #define RETAIN_MEM BIT(14)
44 #define RETAIN_PERIPH BIT(13)
45
46 #define TIMEOUT_US 500
47
48 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
49
50 enum gdsc_status {
51 GDSC_OFF,
52 GDSC_ON
53 };
54
55 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
gdsc_check_status(struct gdsc * sc,enum gdsc_status status)56 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
57 {
58 unsigned int reg;
59 u32 val;
60 int ret;
61
62 if (sc->flags & POLL_CFG_GDSCR)
63 reg = sc->gdscr + CFG_GDSCR_OFFSET;
64 else if (sc->gds_hw_ctrl)
65 reg = sc->gds_hw_ctrl;
66 else
67 reg = sc->gdscr;
68
69 ret = regmap_read(sc->regmap, reg, &val);
70 if (ret)
71 return ret;
72
73 if (sc->flags & POLL_CFG_GDSCR) {
74 switch (status) {
75 case GDSC_ON:
76 return !!(val & GDSC_POWER_UP_COMPLETE);
77 case GDSC_OFF:
78 return !!(val & GDSC_POWER_DOWN_COMPLETE);
79 }
80 }
81
82 switch (status) {
83 case GDSC_ON:
84 return !!(val & PWR_ON_MASK);
85 case GDSC_OFF:
86 return !(val & PWR_ON_MASK);
87 }
88
89 return -EINVAL;
90 }
91
gdsc_hwctrl(struct gdsc * sc,bool en)92 static int gdsc_hwctrl(struct gdsc *sc, bool en)
93 {
94 u32 val = en ? HW_CONTROL_MASK : 0;
95
96 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
97 }
98
gdsc_poll_status(struct gdsc * sc,enum gdsc_status status)99 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
100 {
101 ktime_t start;
102
103 start = ktime_get();
104 do {
105 if (gdsc_check_status(sc, status))
106 return 0;
107 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
108
109 if (gdsc_check_status(sc, status))
110 return 0;
111
112 return -ETIMEDOUT;
113 }
114
gdsc_toggle_logic(struct gdsc * sc,enum gdsc_status status)115 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
116 {
117 int ret;
118 u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
119
120 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
121 if (ret)
122 return ret;
123
124 /* If disabling votable gdscs, don't poll on status */
125 if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
126 /*
127 * Add a short delay here to ensure that an enable
128 * right after it was disabled does not put it in an
129 * unknown state
130 */
131 udelay(TIMEOUT_US);
132 return 0;
133 }
134
135 if (sc->gds_hw_ctrl) {
136 /*
137 * The gds hw controller asserts/de-asserts the status bit soon
138 * after it receives a power on/off request from a master.
139 * The controller then takes around 8 xo cycles to start its
140 * internal state machine and update the status bit. During
141 * this time, the status bit does not reflect the true status
142 * of the core.
143 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
144 * and polling the status bit.
145 */
146 udelay(1);
147 }
148
149 ret = gdsc_poll_status(sc, status);
150 WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
151 return ret;
152 }
153
gdsc_deassert_reset(struct gdsc * sc)154 static inline int gdsc_deassert_reset(struct gdsc *sc)
155 {
156 int i;
157
158 for (i = 0; i < sc->reset_count; i++)
159 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
160 return 0;
161 }
162
gdsc_assert_reset(struct gdsc * sc)163 static inline int gdsc_assert_reset(struct gdsc *sc)
164 {
165 int i;
166
167 for (i = 0; i < sc->reset_count; i++)
168 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
169 return 0;
170 }
171
gdsc_force_mem_on(struct gdsc * sc)172 static inline void gdsc_force_mem_on(struct gdsc *sc)
173 {
174 int i;
175 u32 mask = RETAIN_MEM | RETAIN_PERIPH;
176
177 for (i = 0; i < sc->cxc_count; i++)
178 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
179 }
180
gdsc_clear_mem_on(struct gdsc * sc)181 static inline void gdsc_clear_mem_on(struct gdsc *sc)
182 {
183 int i;
184 u32 mask = RETAIN_MEM | RETAIN_PERIPH;
185
186 for (i = 0; i < sc->cxc_count; i++)
187 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
188 }
189
gdsc_deassert_clamp_io(struct gdsc * sc)190 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
191 {
192 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
193 GMEM_CLAMP_IO_MASK, 0);
194 }
195
gdsc_assert_clamp_io(struct gdsc * sc)196 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
197 {
198 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
199 GMEM_CLAMP_IO_MASK, 1);
200 }
201
gdsc_assert_reset_aon(struct gdsc * sc)202 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
203 {
204 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
205 GMEM_RESET_MASK, 1);
206 udelay(1);
207 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
208 GMEM_RESET_MASK, 0);
209 }
gdsc_enable(struct generic_pm_domain * domain)210 static int gdsc_enable(struct generic_pm_domain *domain)
211 {
212 struct gdsc *sc = domain_to_gdsc(domain);
213 int ret;
214
215 if (sc->pwrsts == PWRSTS_ON)
216 return gdsc_deassert_reset(sc);
217
218 if (sc->flags & SW_RESET) {
219 gdsc_assert_reset(sc);
220 udelay(1);
221 gdsc_deassert_reset(sc);
222 }
223
224 if (sc->flags & CLAMP_IO) {
225 if (sc->flags & AON_RESET)
226 gdsc_assert_reset_aon(sc);
227 gdsc_deassert_clamp_io(sc);
228 }
229
230 ret = gdsc_toggle_logic(sc, GDSC_ON);
231 if (ret)
232 return ret;
233
234 if (sc->pwrsts & PWRSTS_OFF)
235 gdsc_force_mem_on(sc);
236
237 /*
238 * If clocks to this power domain were already on, they will take an
239 * additional 4 clock cycles to re-enable after the power domain is
240 * enabled. Delay to account for this. A delay is also needed to ensure
241 * clocks are not enabled within 400ns of enabling power to the
242 * memories.
243 */
244 udelay(1);
245
246 /* Turn on HW trigger mode if supported */
247 if (sc->flags & HW_CTRL) {
248 ret = gdsc_hwctrl(sc, true);
249 if (ret)
250 return ret;
251 /*
252 * Wait for the GDSC to go through a power down and
253 * up cycle. In case a firmware ends up polling status
254 * bits for the gdsc, it might read an 'on' status before
255 * the GDSC can finish the power cycle.
256 * We wait 1us before returning to ensure the firmware
257 * can't immediately poll the status bits.
258 */
259 udelay(1);
260 }
261
262 return 0;
263 }
264
gdsc_disable(struct generic_pm_domain * domain)265 static int gdsc_disable(struct generic_pm_domain *domain)
266 {
267 struct gdsc *sc = domain_to_gdsc(domain);
268 int ret;
269
270 if (sc->pwrsts == PWRSTS_ON)
271 return gdsc_assert_reset(sc);
272
273 /* Turn off HW trigger mode if supported */
274 if (sc->flags & HW_CTRL) {
275 ret = gdsc_hwctrl(sc, false);
276 if (ret < 0)
277 return ret;
278 /*
279 * Wait for the GDSC to go through a power down and
280 * up cycle. In case we end up polling status
281 * bits for the gdsc before the power cycle is completed
282 * it might read an 'on' status wrongly.
283 */
284 udelay(1);
285
286 ret = gdsc_poll_status(sc, GDSC_ON);
287 if (ret)
288 return ret;
289 }
290
291 if (sc->pwrsts & PWRSTS_OFF)
292 gdsc_clear_mem_on(sc);
293
294 ret = gdsc_toggle_logic(sc, GDSC_OFF);
295 if (ret)
296 return ret;
297
298 if (sc->flags & CLAMP_IO)
299 gdsc_assert_clamp_io(sc);
300
301 return 0;
302 }
303
gdsc_init(struct gdsc * sc)304 static int gdsc_init(struct gdsc *sc)
305 {
306 u32 mask, val;
307 int on, ret;
308
309 /*
310 * Disable HW trigger: collapse/restore occur based on registers writes.
311 * Disable SW override: Use hardware state-machine for sequencing.
312 * Configure wait time between states.
313 */
314 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
315 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
316
317 if (!sc->en_rest_wait_val)
318 sc->en_rest_wait_val = EN_REST_WAIT_VAL;
319 if (!sc->en_few_wait_val)
320 sc->en_few_wait_val = EN_FEW_WAIT_VAL;
321 if (!sc->clk_dis_wait_val)
322 sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
323
324 val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
325 sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
326 sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
327
328 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
329 if (ret)
330 return ret;
331
332 /* Force gdsc ON if only ON state is supported */
333 if (sc->pwrsts == PWRSTS_ON) {
334 ret = gdsc_toggle_logic(sc, GDSC_ON);
335 if (ret)
336 return ret;
337 }
338
339 on = gdsc_check_status(sc, GDSC_ON);
340 if (on < 0)
341 return on;
342
343 /*
344 * Votable GDSCs can be ON due to Vote from other masters.
345 * If a Votable GDSC is ON, make sure we have a Vote.
346 */
347 if ((sc->flags & VOTABLE) && on)
348 gdsc_enable(&sc->pd);
349
350 /* If ALWAYS_ON GDSCs are not ON, turn them ON */
351 if (sc->flags & ALWAYS_ON) {
352 if (!on)
353 gdsc_enable(&sc->pd);
354 on = true;
355 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
356 }
357
358 if (on || (sc->pwrsts & PWRSTS_RET))
359 gdsc_force_mem_on(sc);
360 else
361 gdsc_clear_mem_on(sc);
362
363 if (!sc->pd.power_off)
364 sc->pd.power_off = gdsc_disable;
365 if (!sc->pd.power_on)
366 sc->pd.power_on = gdsc_enable;
367 pm_genpd_init(&sc->pd, NULL, !on);
368
369 return 0;
370 }
371
gdsc_register(struct gdsc_desc * desc,struct reset_controller_dev * rcdev,struct regmap * regmap)372 int gdsc_register(struct gdsc_desc *desc,
373 struct reset_controller_dev *rcdev, struct regmap *regmap)
374 {
375 int i, ret;
376 struct genpd_onecell_data *data;
377 struct device *dev = desc->dev;
378 struct gdsc **scs = desc->scs;
379 size_t num = desc->num;
380
381 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
382 if (!data)
383 return -ENOMEM;
384
385 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
386 GFP_KERNEL);
387 if (!data->domains)
388 return -ENOMEM;
389
390 data->num_domains = num;
391 for (i = 0; i < num; i++) {
392 if (!scs[i])
393 continue;
394 scs[i]->regmap = regmap;
395 scs[i]->rcdev = rcdev;
396 ret = gdsc_init(scs[i]);
397 if (ret)
398 return ret;
399 data->domains[i] = &scs[i]->pd;
400 }
401
402 /* Add subdomains */
403 for (i = 0; i < num; i++) {
404 if (!scs[i])
405 continue;
406 if (scs[i]->parent)
407 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
408 }
409
410 return of_genpd_add_provider_onecell(dev->of_node, data);
411 }
412
gdsc_unregister(struct gdsc_desc * desc)413 void gdsc_unregister(struct gdsc_desc *desc)
414 {
415 int i;
416 struct device *dev = desc->dev;
417 struct gdsc **scs = desc->scs;
418 size_t num = desc->num;
419
420 /* Remove subdomains */
421 for (i = 0; i < num; i++) {
422 if (!scs[i])
423 continue;
424 if (scs[i]->parent)
425 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
426 }
427 of_genpd_del_provider(dev->of_node);
428 }
429