1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car Gen3 Clock Pulse Generator
4 *
5 * Copyright (C) 2015-2018 Glider bvba
6 * Copyright (C) 2019 Renesas Electronics Corp.
7 *
8 * Based on clk-rcar-gen3.c
9 *
10 * Copyright (C) 2015 Renesas Electronics Corp.
11 */
12
13 #include <linux/bug.h>
14 #include <linux/bitfield.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/device.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/pm.h>
22 #include <linux/slab.h>
23 #include <linux/sys_soc.h>
24
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
27
28 #define CPG_PLL0CR 0x00d8
29 #define CPG_PLL2CR 0x002c
30 #define CPG_PLL4CR 0x01f4
31
32 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
33
34 static spinlock_t cpg_lock;
35
cpg_reg_modify(void __iomem * reg,u32 clear,u32 set)36 static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
37 {
38 unsigned long flags;
39 u32 val;
40
41 spin_lock_irqsave(&cpg_lock, flags);
42 val = readl(reg);
43 val &= ~clear;
44 val |= set;
45 writel(val, reg);
46 spin_unlock_irqrestore(&cpg_lock, flags);
47 };
48
49 struct cpg_simple_notifier {
50 struct notifier_block nb;
51 void __iomem *reg;
52 u32 saved;
53 };
54
cpg_simple_notifier_call(struct notifier_block * nb,unsigned long action,void * data)55 static int cpg_simple_notifier_call(struct notifier_block *nb,
56 unsigned long action, void *data)
57 {
58 struct cpg_simple_notifier *csn =
59 container_of(nb, struct cpg_simple_notifier, nb);
60
61 switch (action) {
62 case PM_EVENT_SUSPEND:
63 csn->saved = readl(csn->reg);
64 return NOTIFY_OK;
65
66 case PM_EVENT_RESUME:
67 writel(csn->saved, csn->reg);
68 return NOTIFY_OK;
69 }
70 return NOTIFY_DONE;
71 }
72
cpg_simple_notifier_register(struct raw_notifier_head * notifiers,struct cpg_simple_notifier * csn)73 static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
74 struct cpg_simple_notifier *csn)
75 {
76 csn->nb.notifier_call = cpg_simple_notifier_call;
77 raw_notifier_chain_register(notifiers, &csn->nb);
78 }
79
80 /*
81 * Z Clock & Z2 Clock
82 *
83 * Traits of this clock:
84 * prepare - clk_prepare only ensures that parents are prepared
85 * enable - clk_enable only ensures that parents are enabled
86 * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
87 * parent - fixed parent. No clk_set_parent support
88 */
89 #define CPG_FRQCRB 0x00000004
90 #define CPG_FRQCRB_KICK BIT(31)
91 #define CPG_FRQCRC 0x000000e0
92
93 struct cpg_z_clk {
94 struct clk_hw hw;
95 void __iomem *reg;
96 void __iomem *kick_reg;
97 unsigned long mask;
98 unsigned int fixed_div;
99 };
100
101 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
102
cpg_z_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)103 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
104 unsigned long parent_rate)
105 {
106 struct cpg_z_clk *zclk = to_z_clk(hw);
107 unsigned int mult;
108 u32 val;
109
110 val = readl(zclk->reg) & zclk->mask;
111 mult = 32 - (val >> __ffs(zclk->mask));
112
113 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
114 32 * zclk->fixed_div);
115 }
116
cpg_z_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)117 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
118 unsigned long *parent_rate)
119 {
120 struct cpg_z_clk *zclk = to_z_clk(hw);
121 unsigned long prate;
122 unsigned int mult;
123
124 prate = *parent_rate / zclk->fixed_div;
125 mult = div_u64(rate * 32ULL, prate);
126 mult = clamp(mult, 1U, 32U);
127
128 return (u64)prate * mult / 32;
129 }
130
cpg_z_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)131 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
132 unsigned long parent_rate)
133 {
134 struct cpg_z_clk *zclk = to_z_clk(hw);
135 unsigned int mult;
136 unsigned int i;
137
138 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
139 parent_rate);
140 mult = clamp(mult, 1U, 32U);
141
142 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
143 return -EBUSY;
144
145 cpg_reg_modify(zclk->reg, zclk->mask,
146 ((32 - mult) << __ffs(zclk->mask)) & zclk->mask);
147
148 /*
149 * Set KICK bit in FRQCRB to update hardware setting and wait for
150 * clock change completion.
151 */
152 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
153
154 /*
155 * Note: There is no HW information about the worst case latency.
156 *
157 * Using experimental measurements, it seems that no more than
158 * ~10 iterations are needed, independently of the CPU rate.
159 * Since this value might be dependent of external xtal rate, pll1
160 * rate or even the other emulation clocks rate, use 1000 as a
161 * "super" safe value.
162 */
163 for (i = 1000; i; i--) {
164 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
165 return 0;
166
167 cpu_relax();
168 }
169
170 return -ETIMEDOUT;
171 }
172
173 static const struct clk_ops cpg_z_clk_ops = {
174 .recalc_rate = cpg_z_clk_recalc_rate,
175 .round_rate = cpg_z_clk_round_rate,
176 .set_rate = cpg_z_clk_set_rate,
177 };
178
cpg_z_clk_register(const char * name,const char * parent_name,void __iomem * reg,unsigned int div,unsigned int offset)179 static struct clk * __init cpg_z_clk_register(const char *name,
180 const char *parent_name,
181 void __iomem *reg,
182 unsigned int div,
183 unsigned int offset)
184 {
185 struct clk_init_data init;
186 struct cpg_z_clk *zclk;
187 struct clk *clk;
188
189 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
190 if (!zclk)
191 return ERR_PTR(-ENOMEM);
192
193 init.name = name;
194 init.ops = &cpg_z_clk_ops;
195 init.flags = 0;
196 init.parent_names = &parent_name;
197 init.num_parents = 1;
198
199 zclk->reg = reg + CPG_FRQCRC;
200 zclk->kick_reg = reg + CPG_FRQCRB;
201 zclk->hw.init = &init;
202 zclk->mask = GENMASK(offset + 4, offset);
203 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
204
205 clk = clk_register(NULL, &zclk->hw);
206 if (IS_ERR(clk))
207 kfree(zclk);
208
209 return clk;
210 }
211
212 /*
213 * SDn Clock
214 */
215 #define CPG_SD_STP_HCK BIT(9)
216 #define CPG_SD_STP_CK BIT(8)
217
218 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
219 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
220
221 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
222 { \
223 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
224 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
225 ((sd_srcfc) << 2) | \
226 ((sd_fc) << 0), \
227 .div = (sd_div), \
228 }
229
230 struct sd_div_table {
231 u32 val;
232 unsigned int div;
233 };
234
235 struct sd_clock {
236 struct clk_hw hw;
237 const struct sd_div_table *div_table;
238 struct cpg_simple_notifier csn;
239 unsigned int div_num;
240 unsigned int cur_div_idx;
241 };
242
243 /* SDn divider
244 * sd_srcfc sd_fc div
245 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
246 *-------------------------------------------------------------------
247 * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
248 * 0 0 1 (2) 1 (4) 8 : SDR50
249 * 1 0 2 (4) 1 (4) 16 : HS / SDR25
250 * 1 0 3 (8) 1 (4) 32 : NS / SDR12
251 * 1 0 4 (16) 1 (4) 64
252 * 0 0 0 (1) 0 (2) 2
253 * 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
254 * 1 0 2 (4) 0 (2) 8
255 * 1 0 3 (8) 0 (2) 16
256 * 1 0 4 (16) 0 (2) 32
257 *
258 * NOTE: There is a quirk option to ignore the first row of the dividers
259 * table when searching for suitable settings. This is because HS400 on
260 * early ES versions of H3 and M3-W requires a specific setting to work.
261 */
262 static const struct sd_div_table cpg_sd_div_table[] = {
263 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
264 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
265 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
266 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
267 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
268 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
269 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
270 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
271 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
272 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
273 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
274 };
275
276 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
277
cpg_sd_clock_enable(struct clk_hw * hw)278 static int cpg_sd_clock_enable(struct clk_hw *hw)
279 {
280 struct sd_clock *clock = to_sd_clock(hw);
281
282 cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK,
283 clock->div_table[clock->cur_div_idx].val &
284 CPG_SD_STP_MASK);
285
286 return 0;
287 }
288
cpg_sd_clock_disable(struct clk_hw * hw)289 static void cpg_sd_clock_disable(struct clk_hw *hw)
290 {
291 struct sd_clock *clock = to_sd_clock(hw);
292
293 cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK);
294 }
295
cpg_sd_clock_is_enabled(struct clk_hw * hw)296 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
297 {
298 struct sd_clock *clock = to_sd_clock(hw);
299
300 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
301 }
302
cpg_sd_clock_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)303 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
304 unsigned long parent_rate)
305 {
306 struct sd_clock *clock = to_sd_clock(hw);
307
308 return DIV_ROUND_CLOSEST(parent_rate,
309 clock->div_table[clock->cur_div_idx].div);
310 }
311
cpg_sd_clock_calc_div(struct sd_clock * clock,unsigned long rate,unsigned long parent_rate)312 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
313 unsigned long rate,
314 unsigned long parent_rate)
315 {
316 unsigned long calc_rate, diff, diff_min = ULONG_MAX;
317 unsigned int i, best_div = 0;
318
319 for (i = 0; i < clock->div_num; i++) {
320 calc_rate = DIV_ROUND_CLOSEST(parent_rate,
321 clock->div_table[i].div);
322 diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate;
323 if (diff < diff_min) {
324 best_div = clock->div_table[i].div;
325 diff_min = diff;
326 }
327 }
328
329 return best_div;
330 }
331
cpg_sd_clock_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)332 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
333 unsigned long *parent_rate)
334 {
335 struct sd_clock *clock = to_sd_clock(hw);
336 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
337
338 return DIV_ROUND_CLOSEST(*parent_rate, div);
339 }
340
cpg_sd_clock_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)341 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
342 unsigned long parent_rate)
343 {
344 struct sd_clock *clock = to_sd_clock(hw);
345 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
346 unsigned int i;
347
348 for (i = 0; i < clock->div_num; i++)
349 if (div == clock->div_table[i].div)
350 break;
351
352 if (i >= clock->div_num)
353 return -EINVAL;
354
355 clock->cur_div_idx = i;
356
357 cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK,
358 clock->div_table[i].val &
359 (CPG_SD_STP_MASK | CPG_SD_FC_MASK));
360
361 return 0;
362 }
363
364 static const struct clk_ops cpg_sd_clock_ops = {
365 .enable = cpg_sd_clock_enable,
366 .disable = cpg_sd_clock_disable,
367 .is_enabled = cpg_sd_clock_is_enabled,
368 .recalc_rate = cpg_sd_clock_recalc_rate,
369 .round_rate = cpg_sd_clock_round_rate,
370 .set_rate = cpg_sd_clock_set_rate,
371 };
372
373 static u32 cpg_quirks __initdata;
374
375 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
376 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
377 #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
378
cpg_sd_clk_register(const char * name,void __iomem * base,unsigned int offset,const char * parent_name,struct raw_notifier_head * notifiers)379 static struct clk * __init cpg_sd_clk_register(const char *name,
380 void __iomem *base, unsigned int offset, const char *parent_name,
381 struct raw_notifier_head *notifiers)
382 {
383 struct clk_init_data init;
384 struct sd_clock *clock;
385 struct clk *clk;
386 u32 val;
387
388 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
389 if (!clock)
390 return ERR_PTR(-ENOMEM);
391
392 init.name = name;
393 init.ops = &cpg_sd_clock_ops;
394 init.flags = CLK_SET_RATE_PARENT;
395 init.parent_names = &parent_name;
396 init.num_parents = 1;
397
398 clock->csn.reg = base + offset;
399 clock->hw.init = &init;
400 clock->div_table = cpg_sd_div_table;
401 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
402
403 if (cpg_quirks & SD_SKIP_FIRST) {
404 clock->div_table++;
405 clock->div_num--;
406 }
407
408 val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
409 val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
410 writel(val, clock->csn.reg);
411
412 clk = clk_register(NULL, &clock->hw);
413 if (IS_ERR(clk))
414 goto free_clock;
415
416 cpg_simple_notifier_register(notifiers, &clock->csn);
417 return clk;
418
419 free_clock:
420 kfree(clock);
421 return clk;
422 }
423
424 struct rpc_clock {
425 struct clk_divider div;
426 struct clk_gate gate;
427 /*
428 * One notifier covers both RPC and RPCD2 clocks as they are both
429 * controlled by the same RPCCKCR register...
430 */
431 struct cpg_simple_notifier csn;
432 };
433
434 static const struct clk_div_table cpg_rpcsrc_div_table[] = {
435 { 2, 5 }, { 3, 6 }, { 0, 0 },
436 };
437
438 static const struct clk_div_table cpg_rpc_div_table[] = {
439 { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
440 };
441
cpg_rpc_clk_register(const char * name,void __iomem * base,const char * parent_name,struct raw_notifier_head * notifiers)442 static struct clk * __init cpg_rpc_clk_register(const char *name,
443 void __iomem *base, const char *parent_name,
444 struct raw_notifier_head *notifiers)
445 {
446 struct rpc_clock *rpc;
447 struct clk *clk;
448
449 rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
450 if (!rpc)
451 return ERR_PTR(-ENOMEM);
452
453 rpc->div.reg = base + CPG_RPCCKCR;
454 rpc->div.width = 3;
455 rpc->div.table = cpg_rpc_div_table;
456 rpc->div.lock = &cpg_lock;
457
458 rpc->gate.reg = base + CPG_RPCCKCR;
459 rpc->gate.bit_idx = 8;
460 rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
461 rpc->gate.lock = &cpg_lock;
462
463 rpc->csn.reg = base + CPG_RPCCKCR;
464
465 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
466 &rpc->div.hw, &clk_divider_ops,
467 &rpc->gate.hw, &clk_gate_ops,
468 CLK_SET_RATE_PARENT);
469 if (IS_ERR(clk)) {
470 kfree(rpc);
471 return clk;
472 }
473
474 cpg_simple_notifier_register(notifiers, &rpc->csn);
475 return clk;
476 }
477
478 struct rpcd2_clock {
479 struct clk_fixed_factor fixed;
480 struct clk_gate gate;
481 };
482
cpg_rpcd2_clk_register(const char * name,void __iomem * base,const char * parent_name)483 static struct clk * __init cpg_rpcd2_clk_register(const char *name,
484 void __iomem *base,
485 const char *parent_name)
486 {
487 struct rpcd2_clock *rpcd2;
488 struct clk *clk;
489
490 rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL);
491 if (!rpcd2)
492 return ERR_PTR(-ENOMEM);
493
494 rpcd2->fixed.mult = 1;
495 rpcd2->fixed.div = 2;
496
497 rpcd2->gate.reg = base + CPG_RPCCKCR;
498 rpcd2->gate.bit_idx = 9;
499 rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE;
500 rpcd2->gate.lock = &cpg_lock;
501
502 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
503 &rpcd2->fixed.hw, &clk_fixed_factor_ops,
504 &rpcd2->gate.hw, &clk_gate_ops,
505 CLK_SET_RATE_PARENT);
506 if (IS_ERR(clk))
507 kfree(rpcd2);
508
509 return clk;
510 }
511
512
513 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
514 static unsigned int cpg_clk_extalr __initdata;
515 static u32 cpg_mode __initdata;
516
517 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
518 {
519 .soc_id = "r8a7795", .revision = "ES1.0",
520 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
521 },
522 {
523 .soc_id = "r8a7795", .revision = "ES1.*",
524 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
525 },
526 {
527 .soc_id = "r8a7795", .revision = "ES2.0",
528 .data = (void *)SD_SKIP_FIRST,
529 },
530 {
531 .soc_id = "r8a7796", .revision = "ES1.0",
532 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
533 },
534 {
535 .soc_id = "r8a7796", .revision = "ES1.1",
536 .data = (void *)SD_SKIP_FIRST,
537 },
538 { /* sentinel */ }
539 };
540
rcar_gen3_cpg_clk_register(struct device * dev,const struct cpg_core_clk * core,const struct cpg_mssr_info * info,struct clk ** clks,void __iomem * base,struct raw_notifier_head * notifiers)541 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
542 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
543 struct clk **clks, void __iomem *base,
544 struct raw_notifier_head *notifiers)
545 {
546 const struct clk *parent;
547 unsigned int mult = 1;
548 unsigned int div = 1;
549 u32 value;
550
551 parent = clks[core->parent & 0xffff]; /* some types use high bits */
552 if (IS_ERR(parent))
553 return ERR_CAST(parent);
554
555 switch (core->type) {
556 case CLK_TYPE_GEN3_MAIN:
557 div = cpg_pll_config->extal_div;
558 break;
559
560 case CLK_TYPE_GEN3_PLL0:
561 /*
562 * PLL0 is a configurable multiplier clock. Register it as a
563 * fixed factor clock for now as there's no generic multiplier
564 * clock implementation and we currently have no need to change
565 * the multiplier value.
566 */
567 value = readl(base + CPG_PLL0CR);
568 mult = (((value >> 24) & 0x7f) + 1) * 2;
569 if (cpg_quirks & PLL_ERRATA)
570 mult *= 2;
571 break;
572
573 case CLK_TYPE_GEN3_PLL1:
574 mult = cpg_pll_config->pll1_mult;
575 div = cpg_pll_config->pll1_div;
576 break;
577
578 case CLK_TYPE_GEN3_PLL2:
579 /*
580 * PLL2 is a configurable multiplier clock. Register it as a
581 * fixed factor clock for now as there's no generic multiplier
582 * clock implementation and we currently have no need to change
583 * the multiplier value.
584 */
585 value = readl(base + CPG_PLL2CR);
586 mult = (((value >> 24) & 0x7f) + 1) * 2;
587 if (cpg_quirks & PLL_ERRATA)
588 mult *= 2;
589 break;
590
591 case CLK_TYPE_GEN3_PLL3:
592 mult = cpg_pll_config->pll3_mult;
593 div = cpg_pll_config->pll3_div;
594 break;
595
596 case CLK_TYPE_GEN3_PLL4:
597 /*
598 * PLL4 is a configurable multiplier clock. Register it as a
599 * fixed factor clock for now as there's no generic multiplier
600 * clock implementation and we currently have no need to change
601 * the multiplier value.
602 */
603 value = readl(base + CPG_PLL4CR);
604 mult = (((value >> 24) & 0x7f) + 1) * 2;
605 if (cpg_quirks & PLL_ERRATA)
606 mult *= 2;
607 break;
608
609 case CLK_TYPE_GEN3_SD:
610 return cpg_sd_clk_register(core->name, base, core->offset,
611 __clk_get_name(parent), notifiers);
612
613 case CLK_TYPE_GEN3_R:
614 if (cpg_quirks & RCKCR_CKSEL) {
615 struct cpg_simple_notifier *csn;
616
617 csn = kzalloc(sizeof(*csn), GFP_KERNEL);
618 if (!csn)
619 return ERR_PTR(-ENOMEM);
620
621 csn->reg = base + CPG_RCKCR;
622
623 /*
624 * RINT is default.
625 * Only if EXTALR is populated, we switch to it.
626 */
627 value = readl(csn->reg) & 0x3f;
628
629 if (clk_get_rate(clks[cpg_clk_extalr])) {
630 parent = clks[cpg_clk_extalr];
631 value |= CPG_RCKCR_CKSEL;
632 }
633
634 writel(value, csn->reg);
635 cpg_simple_notifier_register(notifiers, csn);
636 break;
637 }
638
639 /* Select parent clock of RCLK by MD28 */
640 if (cpg_mode & BIT(28))
641 parent = clks[cpg_clk_extalr];
642 break;
643
644 case CLK_TYPE_GEN3_MDSEL:
645 /*
646 * Clock selectable between two parents and two fixed dividers
647 * using a mode pin
648 */
649 if (cpg_mode & BIT(core->offset)) {
650 div = core->div & 0xffff;
651 } else {
652 parent = clks[core->parent >> 16];
653 if (IS_ERR(parent))
654 return ERR_CAST(parent);
655 div = core->div >> 16;
656 }
657 mult = 1;
658 break;
659
660 case CLK_TYPE_GEN3_Z:
661 return cpg_z_clk_register(core->name, __clk_get_name(parent),
662 base, core->div, core->offset);
663
664 case CLK_TYPE_GEN3_OSC:
665 /*
666 * Clock combining OSC EXTAL predivider and a fixed divider
667 */
668 div = cpg_pll_config->osc_prediv * core->div;
669 break;
670
671 case CLK_TYPE_GEN3_RCKSEL:
672 /*
673 * Clock selectable between two parents and two fixed dividers
674 * using RCKCR.CKSEL
675 */
676 if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
677 div = core->div & 0xffff;
678 } else {
679 parent = clks[core->parent >> 16];
680 if (IS_ERR(parent))
681 return ERR_CAST(parent);
682 div = core->div >> 16;
683 }
684 break;
685
686 case CLK_TYPE_GEN3_RPCSRC:
687 return clk_register_divider_table(NULL, core->name,
688 __clk_get_name(parent), 0,
689 base + CPG_RPCCKCR, 3, 2, 0,
690 cpg_rpcsrc_div_table,
691 &cpg_lock);
692
693 case CLK_TYPE_GEN3_RPC:
694 return cpg_rpc_clk_register(core->name, base,
695 __clk_get_name(parent), notifiers);
696
697 case CLK_TYPE_GEN3_RPCD2:
698 return cpg_rpcd2_clk_register(core->name, base,
699 __clk_get_name(parent));
700
701 default:
702 return ERR_PTR(-EINVAL);
703 }
704
705 return clk_register_fixed_factor(NULL, core->name,
706 __clk_get_name(parent), 0, mult, div);
707 }
708
rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config * config,unsigned int clk_extalr,u32 mode)709 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
710 unsigned int clk_extalr, u32 mode)
711 {
712 const struct soc_device_attribute *attr;
713
714 cpg_pll_config = config;
715 cpg_clk_extalr = clk_extalr;
716 cpg_mode = mode;
717 attr = soc_device_match(cpg_quirks_match);
718 if (attr)
719 cpg_quirks = (uintptr_t)attr->data;
720 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
721
722 spin_lock_init(&cpg_lock);
723
724 return 0;
725 }
726