1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Zynq UltraScale+ MPSoC mux
4 *
5 * Copyright (C) 2016-2018 Xilinx
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/slab.h>
10 #include "clk-zynqmp.h"
11
12 /*
13 * DOC: basic adjustable multiplexer clock that cannot gate
14 *
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is only affected by parent switching. No clk_set_rate support
19 * parent - parent is adjustable through clk_set_parent
20 */
21
22 /**
23 * struct zynqmp_clk_mux - multiplexer clock
24 *
25 * @hw: handle between common and hardware-specific interfaces
26 * @flags: hardware-specific flags
27 * @clk_id: Id of clock
28 */
29 struct zynqmp_clk_mux {
30 struct clk_hw hw;
31 u8 flags;
32 u32 clk_id;
33 };
34
35 #define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw)
36
37 /**
38 * zynqmp_clk_mux_get_parent() - Get parent of clock
39 * @hw: handle between common and hardware-specific interfaces
40 *
41 * Return: Parent index
42 */
zynqmp_clk_mux_get_parent(struct clk_hw * hw)43 static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
44 {
45 struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
46 const char *clk_name = clk_hw_get_name(hw);
47 u32 clk_id = mux->clk_id;
48 u32 val;
49 int ret;
50 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
51
52 ret = eemi_ops->clock_getparent(clk_id, &val);
53
54 if (ret)
55 pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
56 __func__, clk_name, ret);
57
58 return val;
59 }
60
61 /**
62 * zynqmp_clk_mux_set_parent() - Set parent of clock
63 * @hw: handle between common and hardware-specific interfaces
64 * @index: Parent index
65 *
66 * Return: 0 on success else error+reason
67 */
zynqmp_clk_mux_set_parent(struct clk_hw * hw,u8 index)68 static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
69 {
70 struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
71 const char *clk_name = clk_hw_get_name(hw);
72 u32 clk_id = mux->clk_id;
73 int ret;
74 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
75
76 ret = eemi_ops->clock_setparent(clk_id, index);
77
78 if (ret)
79 pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
80 __func__, clk_name, ret);
81
82 return ret;
83 }
84
85 static const struct clk_ops zynqmp_clk_mux_ops = {
86 .get_parent = zynqmp_clk_mux_get_parent,
87 .set_parent = zynqmp_clk_mux_set_parent,
88 .determine_rate = __clk_mux_determine_rate_closest,
89 };
90
91 static const struct clk_ops zynqmp_clk_mux_ro_ops = {
92 .get_parent = zynqmp_clk_mux_get_parent,
93 };
94
95 /**
96 * zynqmp_clk_register_mux() - Register a mux table with the clock
97 * framework
98 * @name: Name of this clock
99 * @clk_id: Id of this clock
100 * @parents: Name of this clock's parents
101 * @num_parents: Number of parents
102 * @nodes: Clock topology node
103 *
104 * Return: clock hardware of the registered clock mux
105 */
zynqmp_clk_register_mux(const char * name,u32 clk_id,const char * const * parents,u8 num_parents,const struct clock_topology * nodes)106 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
107 const char * const *parents,
108 u8 num_parents,
109 const struct clock_topology *nodes)
110 {
111 struct zynqmp_clk_mux *mux;
112 struct clk_hw *hw;
113 struct clk_init_data init;
114 int ret;
115
116 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
117 if (!mux)
118 return ERR_PTR(-ENOMEM);
119
120 init.name = name;
121 if (nodes->type_flag & CLK_MUX_READ_ONLY)
122 init.ops = &zynqmp_clk_mux_ro_ops;
123 else
124 init.ops = &zynqmp_clk_mux_ops;
125 init.flags = nodes->flag;
126 init.parent_names = parents;
127 init.num_parents = num_parents;
128 mux->flags = nodes->type_flag;
129 mux->hw.init = &init;
130 mux->clk_id = clk_id;
131
132 hw = &mux->hw;
133 ret = clk_hw_register(NULL, hw);
134 if (ret) {
135 kfree(hw);
136 hw = ERR_PTR(ret);
137 }
138
139 return hw;
140 }
141