1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Zynq UltraScale+ MPSoC clock controller
4 *
5 * Copyright (C) 2016-2018 Xilinx
6 *
7 * Based on drivers/clk/zynq/clkc.c
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
17
18 #include "clk-zynqmp.h"
19
20 #define MAX_PARENT 100
21 #define MAX_NODES 6
22 #define MAX_NAME_LEN 50
23
24 /* Flags for parents */
25 #define PARENT_CLK_SELF 0
26 #define PARENT_CLK_NODE1 1
27 #define PARENT_CLK_NODE2 2
28 #define PARENT_CLK_NODE3 3
29 #define PARENT_CLK_NODE4 4
30 #define PARENT_CLK_EXTERNAL 5
31
32 #define END_OF_CLK_NAME "END_OF_CLK"
33 #define END_OF_TOPOLOGY_NODE 1
34 #define END_OF_PARENTS 1
35 #define RESERVED_CLK_NAME ""
36
37 #define CLK_GET_NAME_RESP_LEN 16
38 #define CLK_GET_TOPOLOGY_RESP_WORDS 3
39 #define CLK_GET_PARENTS_RESP_WORDS 3
40 #define CLK_GET_ATTR_RESP_WORDS 1
41
42 enum clk_type {
43 CLK_TYPE_OUTPUT,
44 CLK_TYPE_EXTERNAL,
45 };
46
47 /**
48 * struct clock_parent - Clock parent
49 * @name: Parent name
50 * @id: Parent clock ID
51 * @flag: Parent flags
52 */
53 struct clock_parent {
54 char name[MAX_NAME_LEN];
55 int id;
56 u32 flag;
57 };
58
59 /**
60 * struct zynqmp_clock - Clock
61 * @clk_name: Clock name
62 * @valid: Validity flag of clock
63 * @type: Clock type (Output/External)
64 * @node: Clock topology nodes
65 * @num_nodes: Number of nodes present in topology
66 * @parent: Parent of clock
67 * @num_parents: Number of parents of clock
68 * @clk_id: Clock id
69 */
70 struct zynqmp_clock {
71 char clk_name[MAX_NAME_LEN];
72 u32 valid;
73 enum clk_type type;
74 struct clock_topology node[MAX_NODES];
75 u32 num_nodes;
76 struct clock_parent parent[MAX_PARENT];
77 u32 num_parents;
78 u32 clk_id;
79 };
80
81 struct name_resp {
82 char name[CLK_GET_NAME_RESP_LEN];
83 };
84
85 struct topology_resp {
86 #define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
87 #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
88 #define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
89 u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
90 };
91
92 struct parents_resp {
93 #define NA_PARENT 0xFFFFFFFF
94 #define DUMMY_PARENT 0xFFFFFFFE
95 #define CLK_PARENTS_ID GENMASK(15, 0)
96 #define CLK_PARENTS_FLAGS GENMASK(31, 16)
97 u32 parents[CLK_GET_PARENTS_RESP_WORDS];
98 };
99
100 struct attr_resp {
101 #define CLK_ATTR_VALID BIT(0)
102 #define CLK_ATTR_TYPE BIT(2)
103 #define CLK_ATTR_NODE_INDEX GENMASK(13, 0)
104 #define CLK_ATTR_NODE_TYPE GENMASK(19, 14)
105 #define CLK_ATTR_NODE_SUBCLASS GENMASK(25, 20)
106 #define CLK_ATTR_NODE_CLASS GENMASK(31, 26)
107 u32 attr[CLK_GET_ATTR_RESP_WORDS];
108 };
109
110 static const char clk_type_postfix[][10] = {
111 [TYPE_INVALID] = "",
112 [TYPE_MUX] = "_mux",
113 [TYPE_GATE] = "",
114 [TYPE_DIV1] = "_div1",
115 [TYPE_DIV2] = "_div2",
116 [TYPE_FIXEDFACTOR] = "_ff",
117 [TYPE_PLL] = ""
118 };
119
120 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
121 const char * const *parents,
122 u8 num_parents,
123 const struct clock_topology *nodes)
124 = {
125 [TYPE_INVALID] = NULL,
126 [TYPE_MUX] = zynqmp_clk_register_mux,
127 [TYPE_PLL] = zynqmp_clk_register_pll,
128 [TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor,
129 [TYPE_DIV1] = zynqmp_clk_register_divider,
130 [TYPE_DIV2] = zynqmp_clk_register_divider,
131 [TYPE_GATE] = zynqmp_clk_register_gate
132 };
133
134 static struct zynqmp_clock *clock;
135 static struct clk_hw_onecell_data *zynqmp_data;
136 static unsigned int clock_max_idx;
137 static const struct zynqmp_eemi_ops *eemi_ops;
138
139 /**
140 * zynqmp_is_valid_clock() - Check whether clock is valid or not
141 * @clk_id: Clock index
142 *
143 * Return: 1 if clock is valid, 0 if clock is invalid else error code
144 */
zynqmp_is_valid_clock(u32 clk_id)145 static inline int zynqmp_is_valid_clock(u32 clk_id)
146 {
147 if (clk_id >= clock_max_idx)
148 return -ENODEV;
149
150 return clock[clk_id].valid;
151 }
152
153 /**
154 * zynqmp_get_clock_name() - Get name of clock from Clock index
155 * @clk_id: Clock index
156 * @clk_name: Name of clock
157 *
158 * Return: 0 on success else error code
159 */
zynqmp_get_clock_name(u32 clk_id,char * clk_name)160 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name)
161 {
162 int ret;
163
164 ret = zynqmp_is_valid_clock(clk_id);
165 if (ret == 1) {
166 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
167 return 0;
168 }
169
170 return ret == 0 ? -EINVAL : ret;
171 }
172
173 /**
174 * zynqmp_get_clock_type() - Get type of clock
175 * @clk_id: Clock index
176 * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
177 *
178 * Return: 0 on success else error code
179 */
zynqmp_get_clock_type(u32 clk_id,u32 * type)180 static int zynqmp_get_clock_type(u32 clk_id, u32 *type)
181 {
182 int ret;
183
184 ret = zynqmp_is_valid_clock(clk_id);
185 if (ret == 1) {
186 *type = clock[clk_id].type;
187 return 0;
188 }
189
190 return ret == 0 ? -EINVAL : ret;
191 }
192
193 /**
194 * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
195 * @nclocks: Number of clocks in system/board.
196 *
197 * Call firmware API to get number of clocks.
198 *
199 * Return: 0 on success else error code.
200 */
zynqmp_pm_clock_get_num_clocks(u32 * nclocks)201 static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
202 {
203 struct zynqmp_pm_query_data qdata = {0};
204 u32 ret_payload[PAYLOAD_ARG_CNT];
205 int ret;
206
207 qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
208
209 ret = eemi_ops->query_data(qdata, ret_payload);
210 *nclocks = ret_payload[1];
211
212 return ret;
213 }
214
215 /**
216 * zynqmp_pm_clock_get_name() - Get the name of clock for given id
217 * @clock_id: ID of the clock to be queried
218 * @response: Name of the clock with the given id
219 *
220 * This function is used to get name of clock specified by given
221 * clock ID.
222 *
223 * Return: Returns 0
224 */
zynqmp_pm_clock_get_name(u32 clock_id,struct name_resp * response)225 static int zynqmp_pm_clock_get_name(u32 clock_id,
226 struct name_resp *response)
227 {
228 struct zynqmp_pm_query_data qdata = {0};
229 u32 ret_payload[PAYLOAD_ARG_CNT];
230
231 qdata.qid = PM_QID_CLOCK_GET_NAME;
232 qdata.arg1 = clock_id;
233
234 eemi_ops->query_data(qdata, ret_payload);
235 memcpy(response, ret_payload, sizeof(*response));
236
237 return 0;
238 }
239
240 /**
241 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
242 * @clock_id: ID of the clock to be queried
243 * @index: Node index of clock topology
244 * @response: Buffer used for the topology response
245 *
246 * This function is used to get topology information for the clock
247 * specified by given clock ID.
248 *
249 * This API will return 3 node of topology with a single response. To get
250 * other nodes, master should call same API in loop with new
251 * index till error is returned. E.g First call should have
252 * index 0 which will return nodes 0,1 and 2. Next call, index
253 * should be 3 which will return nodes 3,4 and 5 and so on.
254 *
255 * Return: 0 on success else error+reason
256 */
zynqmp_pm_clock_get_topology(u32 clock_id,u32 index,struct topology_resp * response)257 static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
258 struct topology_resp *response)
259 {
260 struct zynqmp_pm_query_data qdata = {0};
261 u32 ret_payload[PAYLOAD_ARG_CNT];
262 int ret;
263
264 qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
265 qdata.arg1 = clock_id;
266 qdata.arg2 = index;
267
268 ret = eemi_ops->query_data(qdata, ret_payload);
269 memcpy(response, &ret_payload[1], sizeof(*response));
270
271 return ret;
272 }
273
274 /**
275 * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
276 * clock framework
277 * @name: Name of this clock
278 * @clk_id: Clock ID
279 * @parents: Name of this clock's parents
280 * @num_parents: Number of parents
281 * @nodes: Clock topology node
282 *
283 * Return: clock hardware to the registered clock
284 */
zynqmp_clk_register_fixed_factor(const char * name,u32 clk_id,const char * const * parents,u8 num_parents,const struct clock_topology * nodes)285 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
286 const char * const *parents,
287 u8 num_parents,
288 const struct clock_topology *nodes)
289 {
290 u32 mult, div;
291 struct clk_hw *hw;
292 struct zynqmp_pm_query_data qdata = {0};
293 u32 ret_payload[PAYLOAD_ARG_CNT];
294 int ret;
295
296 qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
297 qdata.arg1 = clk_id;
298
299 ret = eemi_ops->query_data(qdata, ret_payload);
300 if (ret)
301 return ERR_PTR(ret);
302
303 mult = ret_payload[1];
304 div = ret_payload[2];
305
306 hw = clk_hw_register_fixed_factor(NULL, name,
307 parents[0],
308 nodes->flag, mult,
309 div);
310
311 return hw;
312 }
313
314 /**
315 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
316 * @clock_id: Clock ID
317 * @index: Parent index
318 * @response: Parents of the given clock
319 *
320 * This function is used to get 3 parents for the clock specified by
321 * given clock ID.
322 *
323 * This API will return 3 parents with a single response. To get
324 * other parents, master should call same API in loop with new
325 * parent index till error is returned. E.g First call should have
326 * index 0 which will return parents 0,1 and 2. Next call, index
327 * should be 3 which will return parent 3,4 and 5 and so on.
328 *
329 * Return: 0 on success else error+reason
330 */
zynqmp_pm_clock_get_parents(u32 clock_id,u32 index,struct parents_resp * response)331 static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index,
332 struct parents_resp *response)
333 {
334 struct zynqmp_pm_query_data qdata = {0};
335 u32 ret_payload[PAYLOAD_ARG_CNT];
336 int ret;
337
338 qdata.qid = PM_QID_CLOCK_GET_PARENTS;
339 qdata.arg1 = clock_id;
340 qdata.arg2 = index;
341
342 ret = eemi_ops->query_data(qdata, ret_payload);
343 memcpy(response, &ret_payload[1], sizeof(*response));
344
345 return ret;
346 }
347
348 /**
349 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
350 * @clock_id: Clock ID
351 * @response: Clock attributes response
352 *
353 * This function is used to get clock's attributes(e.g. valid, clock type, etc).
354 *
355 * Return: 0 on success else error+reason
356 */
zynqmp_pm_clock_get_attributes(u32 clock_id,struct attr_resp * response)357 static int zynqmp_pm_clock_get_attributes(u32 clock_id,
358 struct attr_resp *response)
359 {
360 struct zynqmp_pm_query_data qdata = {0};
361 u32 ret_payload[PAYLOAD_ARG_CNT];
362 int ret;
363
364 qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
365 qdata.arg1 = clock_id;
366
367 ret = eemi_ops->query_data(qdata, ret_payload);
368 memcpy(response, &ret_payload[1], sizeof(*response));
369
370 return ret;
371 }
372
373 /**
374 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
375 * response data
376 * @topology: Clock topology
377 * @response: Clock topology data received from firmware
378 * @nnodes: Number of nodes
379 *
380 * Return: 0 on success else error+reason
381 */
__zynqmp_clock_get_topology(struct clock_topology * topology,struct topology_resp * response,u32 * nnodes)382 static int __zynqmp_clock_get_topology(struct clock_topology *topology,
383 struct topology_resp *response,
384 u32 *nnodes)
385 {
386 int i;
387 u32 type;
388
389 for (i = 0; i < ARRAY_SIZE(response->topology); i++) {
390 type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);
391 if (type == TYPE_INVALID)
392 return END_OF_TOPOLOGY_NODE;
393 topology[*nnodes].type = type;
394 topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
395 response->topology[i]);
396 topology[*nnodes].type_flag =
397 FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
398 response->topology[i]);
399 (*nnodes)++;
400 }
401
402 return 0;
403 }
404
405 /**
406 * zynqmp_clock_get_topology() - Get topology of clock from firmware using
407 * PM_API
408 * @clk_id: Clock index
409 * @topology: Clock topology
410 * @num_nodes: Number of nodes
411 *
412 * Return: 0 on success else error+reason
413 */
zynqmp_clock_get_topology(u32 clk_id,struct clock_topology * topology,u32 * num_nodes)414 static int zynqmp_clock_get_topology(u32 clk_id,
415 struct clock_topology *topology,
416 u32 *num_nodes)
417 {
418 int j, ret;
419 struct topology_resp response = { };
420
421 *num_nodes = 0;
422 for (j = 0; j <= MAX_NODES; j += ARRAY_SIZE(response.topology)) {
423 ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j,
424 &response);
425 if (ret)
426 return ret;
427 ret = __zynqmp_clock_get_topology(topology, &response,
428 num_nodes);
429 if (ret == END_OF_TOPOLOGY_NODE)
430 return 0;
431 }
432
433 return 0;
434 }
435
436 /**
437 * __zynqmp_clock_get_parents() - Get parents info of clock from firmware
438 * response data
439 * @parents: Clock parents
440 * @response: Clock parents data received from firmware
441 * @nparent: Number of parent
442 *
443 * Return: 0 on success else error+reason
444 */
__zynqmp_clock_get_parents(struct clock_parent * parents,struct parents_resp * response,u32 * nparent)445 static int __zynqmp_clock_get_parents(struct clock_parent *parents,
446 struct parents_resp *response,
447 u32 *nparent)
448 {
449 int i;
450 struct clock_parent *parent;
451
452 for (i = 0; i < ARRAY_SIZE(response->parents); i++) {
453 if (response->parents[i] == NA_PARENT)
454 return END_OF_PARENTS;
455
456 parent = &parents[i];
457 parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]);
458 if (response->parents[i] == DUMMY_PARENT) {
459 strcpy(parent->name, "dummy_name");
460 parent->flag = 0;
461 } else {
462 parent->flag = FIELD_GET(CLK_PARENTS_FLAGS,
463 response->parents[i]);
464 if (zynqmp_get_clock_name(parent->id, parent->name))
465 continue;
466 }
467 *nparent += 1;
468 }
469
470 return 0;
471 }
472
473 /**
474 * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
475 * @clk_id: Clock index
476 * @parents: Clock parents
477 * @num_parents: Total number of parents
478 *
479 * Return: 0 on success else error+reason
480 */
zynqmp_clock_get_parents(u32 clk_id,struct clock_parent * parents,u32 * num_parents)481 static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents,
482 u32 *num_parents)
483 {
484 int j = 0, ret;
485 struct parents_resp response = { };
486
487 *num_parents = 0;
488 do {
489 /* Get parents from firmware */
490 ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j,
491 &response);
492 if (ret)
493 return ret;
494
495 ret = __zynqmp_clock_get_parents(&parents[j], &response,
496 num_parents);
497 if (ret == END_OF_PARENTS)
498 return 0;
499 j += ARRAY_SIZE(response.parents);
500 } while (*num_parents <= MAX_PARENT);
501
502 return 0;
503 }
504
505 /**
506 * zynqmp_get_parent_list() - Create list of parents name
507 * @np: Device node
508 * @clk_id: Clock index
509 * @parent_list: List of parent's name
510 * @num_parents: Total number of parents
511 *
512 * Return: 0 on success else error+reason
513 */
zynqmp_get_parent_list(struct device_node * np,u32 clk_id,const char ** parent_list,u32 * num_parents)514 static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id,
515 const char **parent_list, u32 *num_parents)
516 {
517 int i = 0, ret;
518 u32 total_parents = clock[clk_id].num_parents;
519 struct clock_topology *clk_nodes;
520 struct clock_parent *parents;
521
522 clk_nodes = clock[clk_id].node;
523 parents = clock[clk_id].parent;
524
525 for (i = 0; i < total_parents; i++) {
526 if (!parents[i].flag) {
527 parent_list[i] = parents[i].name;
528 } else if (parents[i].flag == PARENT_CLK_EXTERNAL) {
529 ret = of_property_match_string(np, "clock-names",
530 parents[i].name);
531 if (ret < 0)
532 strcpy(parents[i].name, "dummy_name");
533 parent_list[i] = parents[i].name;
534 } else {
535 strcat(parents[i].name,
536 clk_type_postfix[clk_nodes[parents[i].flag - 1].
537 type]);
538 parent_list[i] = parents[i].name;
539 }
540 }
541
542 *num_parents = total_parents;
543 return 0;
544 }
545
546 /**
547 * zynqmp_register_clk_topology() - Register clock topology
548 * @clk_id: Clock index
549 * @clk_name: Clock Name
550 * @num_parents: Total number of parents
551 * @parent_names: List of parents name
552 *
553 * Return: Returns either clock hardware or error+reason
554 */
zynqmp_register_clk_topology(int clk_id,char * clk_name,int num_parents,const char ** parent_names)555 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
556 int num_parents,
557 const char **parent_names)
558 {
559 int j;
560 u32 num_nodes, clk_dev_id;
561 char *clk_out[MAX_NODES];
562 struct clock_topology *nodes;
563 struct clk_hw *hw = NULL;
564
565 nodes = clock[clk_id].node;
566 num_nodes = clock[clk_id].num_nodes;
567 clk_dev_id = clock[clk_id].clk_id;
568
569 for (j = 0; j < num_nodes; j++) {
570 /*
571 * Clock name received from firmware is output clock name.
572 * Intermediate clock names are postfixed with type of clock.
573 */
574 if (j != (num_nodes - 1)) {
575 clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name,
576 clk_type_postfix[nodes[j].type]);
577 } else {
578 clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name);
579 }
580
581 if (!clk_topology[nodes[j].type])
582 continue;
583
584 hw = (*clk_topology[nodes[j].type])(clk_out[j], clk_dev_id,
585 parent_names,
586 num_parents,
587 &nodes[j]);
588 if (IS_ERR(hw))
589 pr_warn_once("%s() 0x%x: %s register fail with %ld\n",
590 __func__, clk_dev_id, clk_name,
591 PTR_ERR(hw));
592
593 parent_names[0] = clk_out[j];
594 }
595
596 for (j = 0; j < num_nodes; j++)
597 kfree(clk_out[j]);
598
599 return hw;
600 }
601
602 /**
603 * zynqmp_register_clocks() - Register clocks
604 * @np: Device node
605 *
606 * Return: 0 on success else error code
607 */
zynqmp_register_clocks(struct device_node * np)608 static int zynqmp_register_clocks(struct device_node *np)
609 {
610 int ret;
611 u32 i, total_parents = 0, type = 0;
612 const char *parent_names[MAX_PARENT];
613
614 for (i = 0; i < clock_max_idx; i++) {
615 char clk_name[MAX_NAME_LEN];
616
617 /* get clock name, continue to next clock if name not found */
618 if (zynqmp_get_clock_name(i, clk_name))
619 continue;
620
621 /* Check if clock is valid and output clock.
622 * Do not register invalid or external clock.
623 */
624 ret = zynqmp_get_clock_type(i, &type);
625 if (ret || type != CLK_TYPE_OUTPUT)
626 continue;
627
628 /* Get parents of clock*/
629 if (zynqmp_get_parent_list(np, i, parent_names,
630 &total_parents)) {
631 WARN_ONCE(1, "No parents found for %s\n",
632 clock[i].clk_name);
633 continue;
634 }
635
636 zynqmp_data->hws[i] =
637 zynqmp_register_clk_topology(i, clk_name,
638 total_parents,
639 parent_names);
640 }
641
642 for (i = 0; i < clock_max_idx; i++) {
643 if (IS_ERR(zynqmp_data->hws[i])) {
644 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",
645 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
646 WARN_ON(1);
647 }
648 }
649 return 0;
650 }
651
652 /**
653 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
654 */
zynqmp_get_clock_info(void)655 static void zynqmp_get_clock_info(void)
656 {
657 int i, ret;
658 u32 type = 0;
659 u32 nodetype, subclass, class;
660 struct attr_resp attr;
661 struct name_resp name;
662
663 for (i = 0; i < clock_max_idx; i++) {
664 ret = zynqmp_pm_clock_get_attributes(i, &attr);
665 if (ret)
666 continue;
667
668 clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]);
669 clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ?
670 CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
671
672 nodetype = FIELD_GET(CLK_ATTR_NODE_TYPE, attr.attr[0]);
673 subclass = FIELD_GET(CLK_ATTR_NODE_SUBCLASS, attr.attr[0]);
674 class = FIELD_GET(CLK_ATTR_NODE_CLASS, attr.attr[0]);
675
676 clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) |
677 FIELD_PREP(CLK_ATTR_NODE_SUBCLASS, subclass) |
678 FIELD_PREP(CLK_ATTR_NODE_TYPE, nodetype) |
679 FIELD_PREP(CLK_ATTR_NODE_INDEX, i);
680
681 zynqmp_pm_clock_get_name(clock[i].clk_id, &name);
682
683 /*
684 * Terminate with NULL character in case name provided by firmware
685 * is longer and truncated due to size limit.
686 */
687 name.name[sizeof(name.name) - 1] = '\0';
688
689 if (!strcmp(name.name, RESERVED_CLK_NAME))
690 continue;
691 strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
692 }
693
694 /* Get topology of all clock */
695 for (i = 0; i < clock_max_idx; i++) {
696 ret = zynqmp_get_clock_type(i, &type);
697 if (ret || type != CLK_TYPE_OUTPUT)
698 continue;
699
700 ret = zynqmp_clock_get_topology(i, clock[i].node,
701 &clock[i].num_nodes);
702 if (ret)
703 continue;
704
705 ret = zynqmp_clock_get_parents(i, clock[i].parent,
706 &clock[i].num_parents);
707 if (ret)
708 continue;
709 }
710 }
711
712 /**
713 * zynqmp_clk_setup() - Setup the clock framework and register clocks
714 * @np: Device node
715 *
716 * Return: 0 on success else error code
717 */
zynqmp_clk_setup(struct device_node * np)718 static int zynqmp_clk_setup(struct device_node *np)
719 {
720 int ret;
721
722 ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx);
723 if (ret)
724 return ret;
725
726 zynqmp_data = kzalloc(struct_size(zynqmp_data, hws, clock_max_idx),
727 GFP_KERNEL);
728 if (!zynqmp_data)
729 return -ENOMEM;
730
731 clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
732 if (!clock) {
733 kfree(zynqmp_data);
734 return -ENOMEM;
735 }
736
737 zynqmp_get_clock_info();
738 zynqmp_register_clocks(np);
739
740 zynqmp_data->num = clock_max_idx;
741 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data);
742
743 return 0;
744 }
745
zynqmp_clock_probe(struct platform_device * pdev)746 static int zynqmp_clock_probe(struct platform_device *pdev)
747 {
748 int ret;
749 struct device *dev = &pdev->dev;
750
751 eemi_ops = zynqmp_pm_get_eemi_ops();
752 if (IS_ERR(eemi_ops))
753 return PTR_ERR(eemi_ops);
754
755 ret = zynqmp_clk_setup(dev->of_node);
756
757 return ret;
758 }
759
760 static const struct of_device_id zynqmp_clock_of_match[] = {
761 {.compatible = "xlnx,zynqmp-clk"},
762 {},
763 };
764 MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
765
766 static struct platform_driver zynqmp_clock_driver = {
767 .driver = {
768 .name = "zynqmp_clock",
769 .of_match_table = zynqmp_clock_of_match,
770 },
771 .probe = zynqmp_clock_probe,
772 };
773 module_platform_driver(zynqmp_clock_driver);
774