1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Zynq UltraScale+ MPSoC PLL driver
4 *
5 * Copyright (C) 2016-2018 Xilinx
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/slab.h>
11 #include "clk-zynqmp.h"
12
13 /**
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
17 */
18 struct zynqmp_pll {
19 struct clk_hw hw;
20 u32 clk_id;
21 };
22
23 #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
24
25 #define PLL_FBDIV_MIN 25
26 #define PLL_FBDIV_MAX 125
27
28 #define PS_PLL_VCO_MIN 1500000000
29 #define PS_PLL_VCO_MAX 3000000000UL
30
31 enum pll_mode {
32 PLL_MODE_INT,
33 PLL_MODE_FRAC,
34 };
35
36 #define FRAC_OFFSET 0x8
37 #define PLLFCFG_FRAC_EN BIT(31)
38 #define FRAC_DIV BIT(16) /* 2^16 */
39
40 /**
41 * zynqmp_pll_get_mode() - Get mode of PLL
42 * @hw: Handle between common and hardware-specific interfaces
43 *
44 * Return: Mode of PLL
45 */
zynqmp_pll_get_mode(struct clk_hw * hw)46 static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
47 {
48 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
49 u32 clk_id = clk->clk_id;
50 const char *clk_name = clk_hw_get_name(hw);
51 u32 ret_payload[PAYLOAD_ARG_CNT];
52 int ret;
53 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
54
55 ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0,
56 ret_payload);
57 if (ret)
58 pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
59 __func__, clk_name, ret);
60
61 return ret_payload[1];
62 }
63
64 /**
65 * zynqmp_pll_set_mode() - Set the PLL mode
66 * @hw: Handle between common and hardware-specific interfaces
67 * @on: Flag to determine the mode
68 */
zynqmp_pll_set_mode(struct clk_hw * hw,bool on)69 static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
70 {
71 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
72 u32 clk_id = clk->clk_id;
73 const char *clk_name = clk_hw_get_name(hw);
74 int ret;
75 u32 mode;
76 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
77
78 if (on)
79 mode = PLL_MODE_FRAC;
80 else
81 mode = PLL_MODE_INT;
82
83 ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL);
84 if (ret)
85 pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
86 __func__, clk_name, ret);
87 }
88
89 /**
90 * zynqmp_pll_round_rate() - Round a clock frequency
91 * @hw: Handle between common and hardware-specific interfaces
92 * @rate: Desired clock frequency
93 * @prate: Clock frequency of parent clock
94 *
95 * Return: Frequency closest to @rate the hardware can generate
96 */
zynqmp_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)97 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
98 unsigned long *prate)
99 {
100 u32 fbdiv;
101 u32 mult, div;
102
103 /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
104 if (rate > PS_PLL_VCO_MAX) {
105 div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
106 rate = rate / div;
107 }
108 if (rate < PS_PLL_VCO_MIN) {
109 mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
110 rate = rate * mult;
111 }
112
113 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
114 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
115 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
116 rate = *prate * fbdiv;
117 }
118
119 return rate;
120 }
121
122 /**
123 * zynqmp_pll_recalc_rate() - Recalculate clock frequency
124 * @hw: Handle between common and hardware-specific interfaces
125 * @parent_rate: Clock frequency of parent clock
126 *
127 * Return: Current clock frequency
128 */
zynqmp_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)129 static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
130 unsigned long parent_rate)
131 {
132 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
133 u32 clk_id = clk->clk_id;
134 const char *clk_name = clk_hw_get_name(hw);
135 u32 fbdiv, data;
136 unsigned long rate, frac;
137 u32 ret_payload[PAYLOAD_ARG_CNT];
138 int ret;
139 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
140
141 ret = eemi_ops->clock_getdivider(clk_id, &fbdiv);
142 if (ret)
143 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
144 __func__, clk_name, ret);
145
146 rate = parent_rate * fbdiv;
147 if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
148 eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0,
149 ret_payload);
150 data = ret_payload[1];
151 frac = (parent_rate * data) / FRAC_DIV;
152 rate = rate + frac;
153 }
154
155 return rate;
156 }
157
158 /**
159 * zynqmp_pll_set_rate() - Set rate of PLL
160 * @hw: Handle between common and hardware-specific interfaces
161 * @rate: Frequency of clock to be set
162 * @parent_rate: Clock frequency of parent clock
163 *
164 * Set PLL divider to set desired rate.
165 *
166 * Returns: rate which is set on success else error code
167 */
zynqmp_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)168 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
169 unsigned long parent_rate)
170 {
171 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
172 u32 clk_id = clk->clk_id;
173 const char *clk_name = clk_hw_get_name(hw);
174 u32 fbdiv;
175 long rate_div, frac, m, f;
176 int ret;
177 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
178
179 rate_div = (rate * FRAC_DIV) / parent_rate;
180 f = rate_div % FRAC_DIV;
181 zynqmp_pll_set_mode(hw, !!f);
182
183 if (f) {
184 m = rate_div / FRAC_DIV;
185 m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
186 rate = parent_rate * m;
187 frac = (parent_rate * f) / FRAC_DIV;
188
189 ret = eemi_ops->clock_setdivider(clk_id, m);
190 if (ret)
191 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
192 __func__, clk_name, ret);
193
194 eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL);
195
196 return rate + frac;
197 }
198
199 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
200 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
201 ret = eemi_ops->clock_setdivider(clk_id, fbdiv);
202 if (ret)
203 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
204 __func__, clk_name, ret);
205
206 return parent_rate * fbdiv;
207 }
208
209 /**
210 * zynqmp_pll_is_enabled() - Check if a clock is enabled
211 * @hw: Handle between common and hardware-specific interfaces
212 *
213 * Return: 1 if the clock is enabled, 0 otherwise
214 */
zynqmp_pll_is_enabled(struct clk_hw * hw)215 static int zynqmp_pll_is_enabled(struct clk_hw *hw)
216 {
217 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
218 const char *clk_name = clk_hw_get_name(hw);
219 u32 clk_id = clk->clk_id;
220 unsigned int state;
221 int ret;
222 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
223
224 ret = eemi_ops->clock_getstate(clk_id, &state);
225 if (ret) {
226 pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
227 __func__, clk_name, ret);
228 return -EIO;
229 }
230
231 return state ? 1 : 0;
232 }
233
234 /**
235 * zynqmp_pll_enable() - Enable clock
236 * @hw: Handle between common and hardware-specific interfaces
237 *
238 * Return: 0 on success else error code
239 */
zynqmp_pll_enable(struct clk_hw * hw)240 static int zynqmp_pll_enable(struct clk_hw *hw)
241 {
242 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
243 const char *clk_name = clk_hw_get_name(hw);
244 u32 clk_id = clk->clk_id;
245 int ret;
246 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
247
248 if (zynqmp_pll_is_enabled(hw))
249 return 0;
250
251 ret = eemi_ops->clock_enable(clk_id);
252 if (ret)
253 pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
254 __func__, clk_name, ret);
255
256 return ret;
257 }
258
259 /**
260 * zynqmp_pll_disable() - Disable clock
261 * @hw: Handle between common and hardware-specific interfaces
262 */
zynqmp_pll_disable(struct clk_hw * hw)263 static void zynqmp_pll_disable(struct clk_hw *hw)
264 {
265 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
266 const char *clk_name = clk_hw_get_name(hw);
267 u32 clk_id = clk->clk_id;
268 int ret;
269 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
270
271 if (!zynqmp_pll_is_enabled(hw))
272 return;
273
274 ret = eemi_ops->clock_disable(clk_id);
275 if (ret)
276 pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
277 __func__, clk_name, ret);
278 }
279
280 static const struct clk_ops zynqmp_pll_ops = {
281 .enable = zynqmp_pll_enable,
282 .disable = zynqmp_pll_disable,
283 .is_enabled = zynqmp_pll_is_enabled,
284 .round_rate = zynqmp_pll_round_rate,
285 .recalc_rate = zynqmp_pll_recalc_rate,
286 .set_rate = zynqmp_pll_set_rate,
287 };
288
289 /**
290 * zynqmp_clk_register_pll() - Register PLL with the clock framework
291 * @name: PLL name
292 * @clk_id: Clock ID
293 * @parents: Name of this clock's parents
294 * @num_parents: Number of parents
295 * @nodes: Clock topology node
296 *
297 * Return: clock hardware to the registered clock
298 */
zynqmp_clk_register_pll(const char * name,u32 clk_id,const char * const * parents,u8 num_parents,const struct clock_topology * nodes)299 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
300 const char * const *parents,
301 u8 num_parents,
302 const struct clock_topology *nodes)
303 {
304 struct zynqmp_pll *pll;
305 struct clk_hw *hw;
306 struct clk_init_data init;
307 int ret;
308
309 init.name = name;
310 init.ops = &zynqmp_pll_ops;
311 init.flags = nodes->flag;
312 init.parent_names = parents;
313 init.num_parents = 1;
314
315 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
316 if (!pll)
317 return ERR_PTR(-ENOMEM);
318
319 pll->hw.init = &init;
320 pll->clk_id = clk_id;
321
322 hw = &pll->hw;
323 ret = clk_hw_register(NULL, hw);
324 if (ret) {
325 kfree(pll);
326 return ERR_PTR(ret);
327 }
328
329 clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
330 if (ret < 0)
331 pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);
332
333 return hw;
334 }
335