1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * drivers/dma/fsl-edma.c
4 *
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 *
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
9 * Vybrid and Layerscape SoCs.
10 */
11
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/clk.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_dma.h>
20
21 #include "fsl-edma-common.h"
22
fsl_edma_synchronize(struct dma_chan * chan)23 static void fsl_edma_synchronize(struct dma_chan *chan)
24 {
25 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
26
27 vchan_synchronize(&fsl_chan->vchan);
28 }
29
fsl_edma_tx_handler(int irq,void * dev_id)30 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
31 {
32 struct fsl_edma_engine *fsl_edma = dev_id;
33 unsigned int intr, ch;
34 struct edma_regs *regs = &fsl_edma->regs;
35 struct fsl_edma_chan *fsl_chan;
36
37 intr = edma_readl(fsl_edma, regs->intl);
38 if (!intr)
39 return IRQ_NONE;
40
41 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
42 if (intr & (0x1 << ch)) {
43 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
44
45 fsl_chan = &fsl_edma->chans[ch];
46
47 spin_lock(&fsl_chan->vchan.lock);
48
49 if (!fsl_chan->edesc) {
50 /* terminate_all called before */
51 spin_unlock(&fsl_chan->vchan.lock);
52 continue;
53 }
54
55 if (!fsl_chan->edesc->iscyclic) {
56 list_del(&fsl_chan->edesc->vdesc.node);
57 vchan_cookie_complete(&fsl_chan->edesc->vdesc);
58 fsl_chan->edesc = NULL;
59 fsl_chan->status = DMA_COMPLETE;
60 fsl_chan->idle = true;
61 } else {
62 vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
63 }
64
65 if (!fsl_chan->edesc)
66 fsl_edma_xfer_desc(fsl_chan);
67
68 spin_unlock(&fsl_chan->vchan.lock);
69 }
70 }
71 return IRQ_HANDLED;
72 }
73
fsl_edma_err_handler(int irq,void * dev_id)74 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
75 {
76 struct fsl_edma_engine *fsl_edma = dev_id;
77 unsigned int err, ch;
78 struct edma_regs *regs = &fsl_edma->regs;
79
80 err = edma_readl(fsl_edma, regs->errl);
81 if (!err)
82 return IRQ_NONE;
83
84 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
85 if (err & (0x1 << ch)) {
86 fsl_edma_disable_request(&fsl_edma->chans[ch]);
87 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
88 fsl_edma->chans[ch].status = DMA_ERROR;
89 fsl_edma->chans[ch].idle = true;
90 }
91 }
92 return IRQ_HANDLED;
93 }
94
fsl_edma_irq_handler(int irq,void * dev_id)95 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
96 {
97 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
98 return IRQ_HANDLED;
99
100 return fsl_edma_err_handler(irq, dev_id);
101 }
102
fsl_edma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)103 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
104 struct of_dma *ofdma)
105 {
106 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
107 struct dma_chan *chan, *_chan;
108 struct fsl_edma_chan *fsl_chan;
109 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
110 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
111
112 if (dma_spec->args_count != 2)
113 return NULL;
114
115 mutex_lock(&fsl_edma->fsl_edma_mutex);
116 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
117 if (chan->client_count)
118 continue;
119 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
120 chan = dma_get_slave_channel(chan);
121 if (chan) {
122 chan->device->privatecnt++;
123 fsl_chan = to_fsl_edma_chan(chan);
124 fsl_chan->slave_id = dma_spec->args[1];
125 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
126 true);
127 mutex_unlock(&fsl_edma->fsl_edma_mutex);
128 return chan;
129 }
130 }
131 }
132 mutex_unlock(&fsl_edma->fsl_edma_mutex);
133 return NULL;
134 }
135
136 static int
fsl_edma_irq_init(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)137 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
138 {
139 int ret;
140
141 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
142 if (fsl_edma->txirq < 0)
143 return fsl_edma->txirq;
144
145 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
146 if (fsl_edma->errirq < 0)
147 return fsl_edma->errirq;
148
149 if (fsl_edma->txirq == fsl_edma->errirq) {
150 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
151 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
152 if (ret) {
153 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
154 return ret;
155 }
156 } else {
157 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
158 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
159 if (ret) {
160 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
161 return ret;
162 }
163
164 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
165 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
166 if (ret) {
167 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
168 return ret;
169 }
170 }
171
172 return 0;
173 }
174
175 static int
fsl_edma2_irq_init(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)176 fsl_edma2_irq_init(struct platform_device *pdev,
177 struct fsl_edma_engine *fsl_edma)
178 {
179 int i, ret, irq;
180 int count;
181
182 count = platform_irq_count(pdev);
183 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
184 if (count <= 2) {
185 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
186 return -EINVAL;
187 }
188 /*
189 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
190 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
191 * For now, just simply request irq without IRQF_SHARED flag, since 16
192 * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
193 */
194 for (i = 0; i < count; i++) {
195 irq = platform_get_irq(pdev, i);
196 if (irq < 0)
197 return -ENXIO;
198
199 sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
200
201 /* The last IRQ is for eDMA err */
202 if (i == count - 1)
203 ret = devm_request_irq(&pdev->dev, irq,
204 fsl_edma_err_handler,
205 0, "eDMA2-ERR", fsl_edma);
206 else
207 ret = devm_request_irq(&pdev->dev, irq,
208 fsl_edma_tx_handler, 0,
209 fsl_edma->chans[i].chan_name,
210 fsl_edma);
211 if (ret)
212 return ret;
213 }
214
215 return 0;
216 }
217
fsl_edma_irq_exit(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)218 static void fsl_edma_irq_exit(
219 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
220 {
221 if (fsl_edma->txirq == fsl_edma->errirq) {
222 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
223 } else {
224 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
225 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
226 }
227 }
228
fsl_disable_clocks(struct fsl_edma_engine * fsl_edma,int nr_clocks)229 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
230 {
231 int i;
232
233 for (i = 0; i < nr_clocks; i++)
234 clk_disable_unprepare(fsl_edma->muxclk[i]);
235 }
236
237 static struct fsl_edma_drvdata vf610_data = {
238 .version = v1,
239 .dmamuxs = DMAMUX_NR,
240 .setup_irq = fsl_edma_irq_init,
241 };
242
243 static struct fsl_edma_drvdata imx7ulp_data = {
244 .version = v3,
245 .dmamuxs = 1,
246 .has_dmaclk = true,
247 .setup_irq = fsl_edma2_irq_init,
248 };
249
250 static const struct of_device_id fsl_edma_dt_ids[] = {
251 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
252 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
253 { /* sentinel */ }
254 };
255 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
256
fsl_edma_probe(struct platform_device * pdev)257 static int fsl_edma_probe(struct platform_device *pdev)
258 {
259 const struct of_device_id *of_id =
260 of_match_device(fsl_edma_dt_ids, &pdev->dev);
261 struct device_node *np = pdev->dev.of_node;
262 struct fsl_edma_engine *fsl_edma;
263 const struct fsl_edma_drvdata *drvdata = NULL;
264 struct fsl_edma_chan *fsl_chan;
265 struct edma_regs *regs;
266 struct resource *res;
267 int len, chans;
268 int ret, i;
269
270 if (of_id)
271 drvdata = of_id->data;
272 if (!drvdata) {
273 dev_err(&pdev->dev, "unable to find driver data\n");
274 return -EINVAL;
275 }
276
277 ret = of_property_read_u32(np, "dma-channels", &chans);
278 if (ret) {
279 dev_err(&pdev->dev, "Can't get dma-channels.\n");
280 return ret;
281 }
282
283 len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
284 fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
285 if (!fsl_edma)
286 return -ENOMEM;
287
288 fsl_edma->drvdata = drvdata;
289 fsl_edma->n_chans = chans;
290 mutex_init(&fsl_edma->fsl_edma_mutex);
291
292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
293 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
294 if (IS_ERR(fsl_edma->membase))
295 return PTR_ERR(fsl_edma->membase);
296
297 fsl_edma_setup_regs(fsl_edma);
298 regs = &fsl_edma->regs;
299
300 if (drvdata->has_dmaclk) {
301 fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
302 if (IS_ERR(fsl_edma->dmaclk)) {
303 dev_err(&pdev->dev, "Missing DMA block clock.\n");
304 return PTR_ERR(fsl_edma->dmaclk);
305 }
306
307 ret = clk_prepare_enable(fsl_edma->dmaclk);
308 if (ret) {
309 dev_err(&pdev->dev, "DMA clk block failed.\n");
310 return ret;
311 }
312 }
313
314 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
315 char clkname[32];
316
317 res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
318 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
319 if (IS_ERR(fsl_edma->muxbase[i])) {
320 /* on error: disable all previously enabled clks */
321 fsl_disable_clocks(fsl_edma, i);
322 return PTR_ERR(fsl_edma->muxbase[i]);
323 }
324
325 sprintf(clkname, "dmamux%d", i);
326 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
327 if (IS_ERR(fsl_edma->muxclk[i])) {
328 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
329 /* on error: disable all previously enabled clks */
330 fsl_disable_clocks(fsl_edma, i);
331 return PTR_ERR(fsl_edma->muxclk[i]);
332 }
333
334 ret = clk_prepare_enable(fsl_edma->muxclk[i]);
335 if (ret)
336 /* on error: disable all previously enabled clks */
337 fsl_disable_clocks(fsl_edma, i);
338
339 }
340
341 fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
342
343 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
344 for (i = 0; i < fsl_edma->n_chans; i++) {
345 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
346
347 fsl_chan->edma = fsl_edma;
348 fsl_chan->pm_state = RUNNING;
349 fsl_chan->slave_id = 0;
350 fsl_chan->idle = true;
351 fsl_chan->dma_dir = DMA_NONE;
352 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
353 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
354
355 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
356 fsl_edma_chan_mux(fsl_chan, 0, false);
357 }
358
359 edma_writel(fsl_edma, ~0, regs->intl);
360 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
361 if (ret)
362 return ret;
363
364 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
365 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
366 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
367
368 fsl_edma->dma_dev.dev = &pdev->dev;
369 fsl_edma->dma_dev.device_alloc_chan_resources
370 = fsl_edma_alloc_chan_resources;
371 fsl_edma->dma_dev.device_free_chan_resources
372 = fsl_edma_free_chan_resources;
373 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
374 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
375 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
376 fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
377 fsl_edma->dma_dev.device_pause = fsl_edma_pause;
378 fsl_edma->dma_dev.device_resume = fsl_edma_resume;
379 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
380 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
381 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
382
383 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
384 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
385 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
386
387 platform_set_drvdata(pdev, fsl_edma);
388
389 ret = dma_async_device_register(&fsl_edma->dma_dev);
390 if (ret) {
391 dev_err(&pdev->dev,
392 "Can't register Freescale eDMA engine. (%d)\n", ret);
393 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
394 return ret;
395 }
396
397 ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
398 if (ret) {
399 dev_err(&pdev->dev,
400 "Can't register Freescale eDMA of_dma. (%d)\n", ret);
401 dma_async_device_unregister(&fsl_edma->dma_dev);
402 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
403 return ret;
404 }
405
406 /* enable round robin arbitration */
407 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
408
409 return 0;
410 }
411
fsl_edma_remove(struct platform_device * pdev)412 static int fsl_edma_remove(struct platform_device *pdev)
413 {
414 struct device_node *np = pdev->dev.of_node;
415 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
416
417 fsl_edma_irq_exit(pdev, fsl_edma);
418 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
419 of_dma_controller_free(np);
420 dma_async_device_unregister(&fsl_edma->dma_dev);
421 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
422
423 return 0;
424 }
425
fsl_edma_suspend_late(struct device * dev)426 static int fsl_edma_suspend_late(struct device *dev)
427 {
428 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
429 struct fsl_edma_chan *fsl_chan;
430 unsigned long flags;
431 int i;
432
433 for (i = 0; i < fsl_edma->n_chans; i++) {
434 fsl_chan = &fsl_edma->chans[i];
435 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
436 /* Make sure chan is idle or will force disable. */
437 if (unlikely(!fsl_chan->idle)) {
438 dev_warn(dev, "WARN: There is non-idle channel.");
439 fsl_edma_disable_request(fsl_chan);
440 fsl_edma_chan_mux(fsl_chan, 0, false);
441 }
442
443 fsl_chan->pm_state = SUSPENDED;
444 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
445 }
446
447 return 0;
448 }
449
fsl_edma_resume_early(struct device * dev)450 static int fsl_edma_resume_early(struct device *dev)
451 {
452 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
453 struct fsl_edma_chan *fsl_chan;
454 struct edma_regs *regs = &fsl_edma->regs;
455 int i;
456
457 for (i = 0; i < fsl_edma->n_chans; i++) {
458 fsl_chan = &fsl_edma->chans[i];
459 fsl_chan->pm_state = RUNNING;
460 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
461 if (fsl_chan->slave_id != 0)
462 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
463 }
464
465 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
466
467 return 0;
468 }
469
470 /*
471 * eDMA provides the service to others, so it should be suspend late
472 * and resume early. When eDMA suspend, all of the clients should stop
473 * the DMA data transmission and let the channel idle.
474 */
475 static const struct dev_pm_ops fsl_edma_pm_ops = {
476 .suspend_late = fsl_edma_suspend_late,
477 .resume_early = fsl_edma_resume_early,
478 };
479
480 static struct platform_driver fsl_edma_driver = {
481 .driver = {
482 .name = "fsl-edma",
483 .of_match_table = fsl_edma_dt_ids,
484 .pm = &fsl_edma_pm_ops,
485 },
486 .probe = fsl_edma_probe,
487 .remove = fsl_edma_remove,
488 };
489
fsl_edma_init(void)490 static int __init fsl_edma_init(void)
491 {
492 return platform_driver_register(&fsl_edma_driver);
493 }
494 subsys_initcall(fsl_edma_init);
495
fsl_edma_exit(void)496 static void __exit fsl_edma_exit(void)
497 {
498 platform_driver_unregister(&fsl_edma_driver);
499 }
500 module_exit(fsl_edma_exit);
501
502 MODULE_ALIAS("platform:fsl-edma");
503 MODULE_DESCRIPTION("Freescale eDMA engine driver");
504 MODULE_LICENSE("GPL v2");
505