1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // drivers/dma/imx-sdma.c
4 //
5 // This file contains a driver for the Freescale Smart DMA engine
6 //
7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 //
9 // Based on code from Freescale:
10 //
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12
13 #include <linux/init.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/bitops.h>
18 #include <linux/mm.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/sched.h>
23 #include <linux/semaphore.h>
24 #include <linux/spinlock.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firmware.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/dmaengine.h>
31 #include <linux/of.h>
32 #include <linux/of_address.h>
33 #include <linux/of_device.h>
34 #include <linux/of_dma.h>
35 #include <linux/workqueue.h>
36
37 #include <asm/irq.h>
38 #include <linux/platform_data/dma-imx-sdma.h>
39 #include <linux/platform_data/dma-imx.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
43
44 #include "dmaengine.h"
45 #include "virt-dma.h"
46
47 /* SDMA registers */
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
77
78 /*
79 * Buffer descriptor status values.
80 */
81 #define BD_DONE 0x01
82 #define BD_WRAP 0x02
83 #define BD_CONT 0x04
84 #define BD_INTR 0x08
85 #define BD_RROR 0x10
86 #define BD_LAST 0x20
87 #define BD_EXTD 0x80
88
89 /*
90 * Data Node descriptor status values.
91 */
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
94 #define DND_DONE 0x20
95 #define DND_UNUSED 0x01
96
97 /*
98 * IPCV2 descriptor status values.
99 */
100 #define BD_IPCV2_END_OF_FRAME 0x40
101
102 #define IPCV2_MAX_NODES 50
103 /*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107 #define DATA_ERROR 0x10000000
108
109 /*
110 * Buffer descriptor commands.
111 */
112 #define C0_ADDR 0x01
113 #define C0_LOAD 0x02
114 #define C0_DUMP 0x03
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
121 /*
122 * Change endianness indicator in the BD command field
123 */
124 #define CHANGE_ENDIANNESS 0x80
125
126 /*
127 * p_2_p watermark_level description
128 * Bits Name Description
129 * 0-7 Lower WML Lower watermark level
130 * 8 PS 1: Pad Swallowing
131 * 0: No Pad Swallowing
132 * 9 PA 1: Pad Adding
133 * 0: No Pad Adding
134 * 10 SPDIF If this bit is set both source
135 * and destination are on SPBA
136 * 11 Source Bit(SP) 1: Source on SPBA
137 * 0: Source on AIPS
138 * 12 Destination Bit(DP) 1: Destination on SPBA
139 * 0: Destination on AIPS
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
143 * which Pad adding/Swallowing
144 * must be done. It must be odd.
145 * 28 Lower WML Event(LWE) SDMA events reg to check for
146 * LWML event mask
147 * 0: LWE in EVENTS register
148 * 1: LWE in EVENTS2 register
149 * 29 Higher WML Event(HWE) SDMA events reg to check for
150 * HWML event mask
151 * 0: HWE in EVENTS register
152 * 1: HWE in EVENTS2 register
153 * 30 --------- MUST BE 0
154 * 31 CONT 1: Amount of samples to be
155 * transferred is unknown and
156 * script will keep on
157 * transferring samples as long as
158 * both events are detected and
159 * script must be manually stopped
160 * by the application
161 * 0: The amount of samples to be
162 * transferred is equal to the
163 * count field of mode word
164 */
165 #define SDMA_WATERMARK_LEVEL_LWML 0xFF
166 #define SDMA_WATERMARK_LEVEL_PS BIT(8)
167 #define SDMA_WATERMARK_LEVEL_PA BIT(9)
168 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
169 #define SDMA_WATERMARK_LEVEL_SP BIT(11)
170 #define SDMA_WATERMARK_LEVEL_DP BIT(12)
171 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
172 #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
173 #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
174 #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
175
176 #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
179
180 #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \
181 BIT(DMA_MEM_TO_DEV) | \
182 BIT(DMA_DEV_TO_DEV))
183
184 /*
185 * Mode/Count of data node descriptors - IPCv2
186 */
187 struct sdma_mode_count {
188 #define SDMA_BD_MAX_CNT 0xffff
189 u32 count : 16; /* size of the buffer pointed by this BD */
190 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
191 u32 command : 8; /* command mostly used for channel 0 */
192 };
193
194 /*
195 * Buffer descriptor
196 */
197 struct sdma_buffer_descriptor {
198 struct sdma_mode_count mode;
199 u32 buffer_addr; /* address of the buffer described */
200 u32 ext_buffer_addr; /* extended buffer address */
201 } __attribute__ ((packed));
202
203 /**
204 * struct sdma_channel_control - Channel control Block
205 *
206 * @current_bd_ptr: current buffer descriptor processed
207 * @base_bd_ptr: first element of buffer descriptor array
208 * @unused: padding. The SDMA engine expects an array of 128 byte
209 * control blocks
210 */
211 struct sdma_channel_control {
212 u32 current_bd_ptr;
213 u32 base_bd_ptr;
214 u32 unused[2];
215 } __attribute__ ((packed));
216
217 /**
218 * struct sdma_state_registers - SDMA context for a channel
219 *
220 * @pc: program counter
221 * @unused1: unused
222 * @t: test bit: status of arithmetic & test instruction
223 * @rpc: return program counter
224 * @unused0: unused
225 * @sf: source fault while loading data
226 * @spc: loop start program counter
227 * @unused2: unused
228 * @df: destination fault while storing data
229 * @epc: loop end program counter
230 * @lm: loop mode
231 */
232 struct sdma_state_registers {
233 u32 pc :14;
234 u32 unused1: 1;
235 u32 t : 1;
236 u32 rpc :14;
237 u32 unused0: 1;
238 u32 sf : 1;
239 u32 spc :14;
240 u32 unused2: 1;
241 u32 df : 1;
242 u32 epc :14;
243 u32 lm : 2;
244 } __attribute__ ((packed));
245
246 /**
247 * struct sdma_context_data - sdma context specific to a channel
248 *
249 * @channel_state: channel state bits
250 * @gReg: general registers
251 * @mda: burst dma destination address register
252 * @msa: burst dma source address register
253 * @ms: burst dma status register
254 * @md: burst dma data register
255 * @pda: peripheral dma destination address register
256 * @psa: peripheral dma source address register
257 * @ps: peripheral dma status register
258 * @pd: peripheral dma data register
259 * @ca: CRC polynomial register
260 * @cs: CRC accumulator register
261 * @dda: dedicated core destination address register
262 * @dsa: dedicated core source address register
263 * @ds: dedicated core status register
264 * @dd: dedicated core data register
265 * @scratch0: 1st word of dedicated ram for context switch
266 * @scratch1: 2nd word of dedicated ram for context switch
267 * @scratch2: 3rd word of dedicated ram for context switch
268 * @scratch3: 4th word of dedicated ram for context switch
269 * @scratch4: 5th word of dedicated ram for context switch
270 * @scratch5: 6th word of dedicated ram for context switch
271 * @scratch6: 7th word of dedicated ram for context switch
272 * @scratch7: 8th word of dedicated ram for context switch
273 */
274 struct sdma_context_data {
275 struct sdma_state_registers channel_state;
276 u32 gReg[8];
277 u32 mda;
278 u32 msa;
279 u32 ms;
280 u32 md;
281 u32 pda;
282 u32 psa;
283 u32 ps;
284 u32 pd;
285 u32 ca;
286 u32 cs;
287 u32 dda;
288 u32 dsa;
289 u32 ds;
290 u32 dd;
291 u32 scratch0;
292 u32 scratch1;
293 u32 scratch2;
294 u32 scratch3;
295 u32 scratch4;
296 u32 scratch5;
297 u32 scratch6;
298 u32 scratch7;
299 } __attribute__ ((packed));
300
301
302 struct sdma_engine;
303
304 /**
305 * struct sdma_desc - descriptor structor for one transfer
306 * @vd: descriptor for virt dma
307 * @num_bd: number of descriptors currently handling
308 * @bd_phys: physical address of bd
309 * @buf_tail: ID of the buffer that was processed
310 * @buf_ptail: ID of the previous buffer that was processed
311 * @period_len: period length, used in cyclic.
312 * @chn_real_count: the real count updated from bd->mode.count
313 * @chn_count: the transfer count set
314 * @sdmac: sdma_channel pointer
315 * @bd: pointer of allocate bd
316 */
317 struct sdma_desc {
318 struct virt_dma_desc vd;
319 unsigned int num_bd;
320 dma_addr_t bd_phys;
321 unsigned int buf_tail;
322 unsigned int buf_ptail;
323 unsigned int period_len;
324 unsigned int chn_real_count;
325 unsigned int chn_count;
326 struct sdma_channel *sdmac;
327 struct sdma_buffer_descriptor *bd;
328 };
329
330 /**
331 * struct sdma_channel - housekeeping for a SDMA channel
332 *
333 * @vc: virt_dma base structure
334 * @desc: sdma description including vd and other special member
335 * @sdma: pointer to the SDMA engine for this channel
336 * @channel: the channel number, matches dmaengine chan_id + 1
337 * @direction: transfer type. Needed for setting SDMA script
338 * @slave_config Slave configuration
339 * @peripheral_type: Peripheral type. Needed for setting SDMA script
340 * @event_id0: aka dma request line
341 * @event_id1: for channels that use 2 events
342 * @word_size: peripheral access size
343 * @pc_from_device: script address for those device_2_memory
344 * @pc_to_device: script address for those memory_2_device
345 * @device_to_device: script address for those device_2_device
346 * @pc_to_pc: script address for those memory_2_memory
347 * @flags: loop mode or not
348 * @per_address: peripheral source or destination address in common case
349 * destination address in p_2_p case
350 * @per_address2: peripheral source address in p_2_p case
351 * @event_mask: event mask used in p_2_p script
352 * @watermark_level: value for gReg[7], some script will extend it from
353 * basic watermark such as p_2_p
354 * @shp_addr: value for gReg[6]
355 * @per_addr: value for gReg[2]
356 * @status: status of dma channel
357 * @data: specific sdma interface structure
358 * @bd_pool: dma_pool for bd
359 */
360 struct sdma_channel {
361 struct virt_dma_chan vc;
362 struct sdma_desc *desc;
363 struct sdma_engine *sdma;
364 unsigned int channel;
365 enum dma_transfer_direction direction;
366 struct dma_slave_config slave_config;
367 enum sdma_peripheral_type peripheral_type;
368 unsigned int event_id0;
369 unsigned int event_id1;
370 enum dma_slave_buswidth word_size;
371 unsigned int pc_from_device, pc_to_device;
372 unsigned int device_to_device;
373 unsigned int pc_to_pc;
374 unsigned long flags;
375 dma_addr_t per_address, per_address2;
376 unsigned long event_mask[2];
377 unsigned long watermark_level;
378 u32 shp_addr, per_addr;
379 enum dma_status status;
380 struct imx_dma_data data;
381 struct work_struct terminate_worker;
382 };
383
384 #define IMX_DMA_SG_LOOP BIT(0)
385
386 #define MAX_DMA_CHANNELS 32
387 #define MXC_SDMA_DEFAULT_PRIORITY 1
388 #define MXC_SDMA_MIN_PRIORITY 1
389 #define MXC_SDMA_MAX_PRIORITY 7
390
391 #define SDMA_FIRMWARE_MAGIC 0x414d4453
392
393 /**
394 * struct sdma_firmware_header - Layout of the firmware image
395 *
396 * @magic: "SDMA"
397 * @version_major: increased whenever layout of struct
398 * sdma_script_start_addrs changes.
399 * @version_minor: firmware minor version (for binary compatible changes)
400 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
401 * @num_script_addrs: Number of script addresses in this image
402 * @ram_code_start: offset of SDMA ram image in this firmware image
403 * @ram_code_size: size of SDMA ram image
404 * @script_addrs: Stores the start address of the SDMA scripts
405 * (in SDMA memory space)
406 */
407 struct sdma_firmware_header {
408 u32 magic;
409 u32 version_major;
410 u32 version_minor;
411 u32 script_addrs_start;
412 u32 num_script_addrs;
413 u32 ram_code_start;
414 u32 ram_code_size;
415 };
416
417 struct sdma_driver_data {
418 int chnenbl0;
419 int num_events;
420 struct sdma_script_start_addrs *script_addrs;
421 bool check_ratio;
422 };
423
424 struct sdma_engine {
425 struct device *dev;
426 struct device_dma_parameters dma_parms;
427 struct sdma_channel channel[MAX_DMA_CHANNELS];
428 struct sdma_channel_control *channel_control;
429 void __iomem *regs;
430 struct sdma_context_data *context;
431 dma_addr_t context_phys;
432 struct dma_device dma_device;
433 struct clk *clk_ipg;
434 struct clk *clk_ahb;
435 spinlock_t channel_0_lock;
436 u32 script_number;
437 struct sdma_script_start_addrs *script_addrs;
438 const struct sdma_driver_data *drvdata;
439 u32 spba_start_addr;
440 u32 spba_end_addr;
441 unsigned int irq;
442 dma_addr_t bd0_phys;
443 struct sdma_buffer_descriptor *bd0;
444 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
445 bool clk_ratio;
446 };
447
448 static int sdma_config_write(struct dma_chan *chan,
449 struct dma_slave_config *dmaengine_cfg,
450 enum dma_transfer_direction direction);
451
452 static struct sdma_driver_data sdma_imx31 = {
453 .chnenbl0 = SDMA_CHNENBL0_IMX31,
454 .num_events = 32,
455 };
456
457 static struct sdma_script_start_addrs sdma_script_imx25 = {
458 .ap_2_ap_addr = 729,
459 .uart_2_mcu_addr = 904,
460 .per_2_app_addr = 1255,
461 .mcu_2_app_addr = 834,
462 .uartsh_2_mcu_addr = 1120,
463 .per_2_shp_addr = 1329,
464 .mcu_2_shp_addr = 1048,
465 .ata_2_mcu_addr = 1560,
466 .mcu_2_ata_addr = 1479,
467 .app_2_per_addr = 1189,
468 .app_2_mcu_addr = 770,
469 .shp_2_per_addr = 1407,
470 .shp_2_mcu_addr = 979,
471 };
472
473 static struct sdma_driver_data sdma_imx25 = {
474 .chnenbl0 = SDMA_CHNENBL0_IMX35,
475 .num_events = 48,
476 .script_addrs = &sdma_script_imx25,
477 };
478
479 static struct sdma_driver_data sdma_imx35 = {
480 .chnenbl0 = SDMA_CHNENBL0_IMX35,
481 .num_events = 48,
482 };
483
484 static struct sdma_script_start_addrs sdma_script_imx51 = {
485 .ap_2_ap_addr = 642,
486 .uart_2_mcu_addr = 817,
487 .mcu_2_app_addr = 747,
488 .mcu_2_shp_addr = 961,
489 .ata_2_mcu_addr = 1473,
490 .mcu_2_ata_addr = 1392,
491 .app_2_per_addr = 1033,
492 .app_2_mcu_addr = 683,
493 .shp_2_per_addr = 1251,
494 .shp_2_mcu_addr = 892,
495 };
496
497 static struct sdma_driver_data sdma_imx51 = {
498 .chnenbl0 = SDMA_CHNENBL0_IMX35,
499 .num_events = 48,
500 .script_addrs = &sdma_script_imx51,
501 };
502
503 static struct sdma_script_start_addrs sdma_script_imx53 = {
504 .ap_2_ap_addr = 642,
505 .app_2_mcu_addr = 683,
506 .mcu_2_app_addr = 747,
507 .uart_2_mcu_addr = 817,
508 .shp_2_mcu_addr = 891,
509 .mcu_2_shp_addr = 960,
510 .uartsh_2_mcu_addr = 1032,
511 .spdif_2_mcu_addr = 1100,
512 .mcu_2_spdif_addr = 1134,
513 .firi_2_mcu_addr = 1193,
514 .mcu_2_firi_addr = 1290,
515 };
516
517 static struct sdma_driver_data sdma_imx53 = {
518 .chnenbl0 = SDMA_CHNENBL0_IMX35,
519 .num_events = 48,
520 .script_addrs = &sdma_script_imx53,
521 };
522
523 static struct sdma_script_start_addrs sdma_script_imx6q = {
524 .ap_2_ap_addr = 642,
525 .uart_2_mcu_addr = 817,
526 .mcu_2_app_addr = 747,
527 .per_2_per_addr = 6331,
528 .uartsh_2_mcu_addr = 1032,
529 .mcu_2_shp_addr = 960,
530 .app_2_mcu_addr = 683,
531 .shp_2_mcu_addr = 891,
532 .spdif_2_mcu_addr = 1100,
533 .mcu_2_spdif_addr = 1134,
534 };
535
536 static struct sdma_driver_data sdma_imx6q = {
537 .chnenbl0 = SDMA_CHNENBL0_IMX35,
538 .num_events = 48,
539 .script_addrs = &sdma_script_imx6q,
540 };
541
542 static struct sdma_script_start_addrs sdma_script_imx7d = {
543 .ap_2_ap_addr = 644,
544 .uart_2_mcu_addr = 819,
545 .mcu_2_app_addr = 749,
546 .uartsh_2_mcu_addr = 1034,
547 .mcu_2_shp_addr = 962,
548 .app_2_mcu_addr = 685,
549 .shp_2_mcu_addr = 893,
550 .spdif_2_mcu_addr = 1102,
551 .mcu_2_spdif_addr = 1136,
552 };
553
554 static struct sdma_driver_data sdma_imx7d = {
555 .chnenbl0 = SDMA_CHNENBL0_IMX35,
556 .num_events = 48,
557 .script_addrs = &sdma_script_imx7d,
558 };
559
560 static struct sdma_driver_data sdma_imx8mq = {
561 .chnenbl0 = SDMA_CHNENBL0_IMX35,
562 .num_events = 48,
563 .script_addrs = &sdma_script_imx7d,
564 .check_ratio = 1,
565 };
566
567 static const struct platform_device_id sdma_devtypes[] = {
568 {
569 .name = "imx25-sdma",
570 .driver_data = (unsigned long)&sdma_imx25,
571 }, {
572 .name = "imx31-sdma",
573 .driver_data = (unsigned long)&sdma_imx31,
574 }, {
575 .name = "imx35-sdma",
576 .driver_data = (unsigned long)&sdma_imx35,
577 }, {
578 .name = "imx51-sdma",
579 .driver_data = (unsigned long)&sdma_imx51,
580 }, {
581 .name = "imx53-sdma",
582 .driver_data = (unsigned long)&sdma_imx53,
583 }, {
584 .name = "imx6q-sdma",
585 .driver_data = (unsigned long)&sdma_imx6q,
586 }, {
587 .name = "imx7d-sdma",
588 .driver_data = (unsigned long)&sdma_imx7d,
589 }, {
590 .name = "imx8mq-sdma",
591 .driver_data = (unsigned long)&sdma_imx8mq,
592 }, {
593 /* sentinel */
594 }
595 };
596 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
597
598 static const struct of_device_id sdma_dt_ids[] = {
599 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
600 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
601 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
602 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
603 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
604 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
605 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
606 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
607 { /* sentinel */ }
608 };
609 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
610
611 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
612 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
613 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
614 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
615
chnenbl_ofs(struct sdma_engine * sdma,unsigned int event)616 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
617 {
618 u32 chnenbl0 = sdma->drvdata->chnenbl0;
619 return chnenbl0 + event * 4;
620 }
621
sdma_config_ownership(struct sdma_channel * sdmac,bool event_override,bool mcu_override,bool dsp_override)622 static int sdma_config_ownership(struct sdma_channel *sdmac,
623 bool event_override, bool mcu_override, bool dsp_override)
624 {
625 struct sdma_engine *sdma = sdmac->sdma;
626 int channel = sdmac->channel;
627 unsigned long evt, mcu, dsp;
628
629 if (event_override && mcu_override && dsp_override)
630 return -EINVAL;
631
632 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
633 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
634 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
635
636 if (dsp_override)
637 __clear_bit(channel, &dsp);
638 else
639 __set_bit(channel, &dsp);
640
641 if (event_override)
642 __clear_bit(channel, &evt);
643 else
644 __set_bit(channel, &evt);
645
646 if (mcu_override)
647 __clear_bit(channel, &mcu);
648 else
649 __set_bit(channel, &mcu);
650
651 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
652 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
653 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
654
655 return 0;
656 }
657
sdma_enable_channel(struct sdma_engine * sdma,int channel)658 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
659 {
660 writel(BIT(channel), sdma->regs + SDMA_H_START);
661 }
662
663 /*
664 * sdma_run_channel0 - run a channel and wait till it's done
665 */
sdma_run_channel0(struct sdma_engine * sdma)666 static int sdma_run_channel0(struct sdma_engine *sdma)
667 {
668 int ret;
669 u32 reg;
670
671 sdma_enable_channel(sdma, 0);
672
673 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
674 reg, !(reg & 1), 1, 500);
675 if (ret)
676 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
677
678 /* Set bits of CONFIG register with dynamic context switching */
679 reg = readl(sdma->regs + SDMA_H_CONFIG);
680 if ((reg & SDMA_H_CONFIG_CSM) == 0) {
681 reg |= SDMA_H_CONFIG_CSM;
682 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
683 }
684
685 return ret;
686 }
687
sdma_load_script(struct sdma_engine * sdma,void * buf,int size,u32 address)688 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
689 u32 address)
690 {
691 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
692 void *buf_virt;
693 dma_addr_t buf_phys;
694 int ret;
695 unsigned long flags;
696
697 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
698 if (!buf_virt) {
699 return -ENOMEM;
700 }
701
702 spin_lock_irqsave(&sdma->channel_0_lock, flags);
703
704 bd0->mode.command = C0_SETPM;
705 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
706 bd0->mode.count = size / 2;
707 bd0->buffer_addr = buf_phys;
708 bd0->ext_buffer_addr = address;
709
710 memcpy(buf_virt, buf, size);
711
712 ret = sdma_run_channel0(sdma);
713
714 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
715
716 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
717
718 return ret;
719 }
720
sdma_event_enable(struct sdma_channel * sdmac,unsigned int event)721 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
722 {
723 struct sdma_engine *sdma = sdmac->sdma;
724 int channel = sdmac->channel;
725 unsigned long val;
726 u32 chnenbl = chnenbl_ofs(sdma, event);
727
728 val = readl_relaxed(sdma->regs + chnenbl);
729 __set_bit(channel, &val);
730 writel_relaxed(val, sdma->regs + chnenbl);
731 }
732
sdma_event_disable(struct sdma_channel * sdmac,unsigned int event)733 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
734 {
735 struct sdma_engine *sdma = sdmac->sdma;
736 int channel = sdmac->channel;
737 u32 chnenbl = chnenbl_ofs(sdma, event);
738 unsigned long val;
739
740 val = readl_relaxed(sdma->regs + chnenbl);
741 __clear_bit(channel, &val);
742 writel_relaxed(val, sdma->regs + chnenbl);
743 }
744
to_sdma_desc(struct dma_async_tx_descriptor * t)745 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
746 {
747 return container_of(t, struct sdma_desc, vd.tx);
748 }
749
sdma_start_desc(struct sdma_channel * sdmac)750 static void sdma_start_desc(struct sdma_channel *sdmac)
751 {
752 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
753 struct sdma_desc *desc;
754 struct sdma_engine *sdma = sdmac->sdma;
755 int channel = sdmac->channel;
756
757 if (!vd) {
758 sdmac->desc = NULL;
759 return;
760 }
761 sdmac->desc = desc = to_sdma_desc(&vd->tx);
762 /*
763 * Do not delete the node in desc_issued list in cyclic mode, otherwise
764 * the desc allocated will never be freed in vchan_dma_desc_free_list
765 */
766 if (!(sdmac->flags & IMX_DMA_SG_LOOP))
767 list_del(&vd->node);
768
769 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
770 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
771 sdma_enable_channel(sdma, sdmac->channel);
772 }
773
sdma_update_channel_loop(struct sdma_channel * sdmac)774 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
775 {
776 struct sdma_buffer_descriptor *bd;
777 int error = 0;
778 enum dma_status old_status = sdmac->status;
779
780 /*
781 * loop mode. Iterate over descriptors, re-setup them and
782 * call callback function.
783 */
784 while (sdmac->desc) {
785 struct sdma_desc *desc = sdmac->desc;
786
787 bd = &desc->bd[desc->buf_tail];
788
789 if (bd->mode.status & BD_DONE)
790 break;
791
792 if (bd->mode.status & BD_RROR) {
793 bd->mode.status &= ~BD_RROR;
794 sdmac->status = DMA_ERROR;
795 error = -EIO;
796 }
797
798 /*
799 * We use bd->mode.count to calculate the residue, since contains
800 * the number of bytes present in the current buffer descriptor.
801 */
802
803 desc->chn_real_count = bd->mode.count;
804 bd->mode.status |= BD_DONE;
805 bd->mode.count = desc->period_len;
806 desc->buf_ptail = desc->buf_tail;
807 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
808
809 /*
810 * The callback is called from the interrupt context in order
811 * to reduce latency and to avoid the risk of altering the
812 * SDMA transaction status by the time the client tasklet is
813 * executed.
814 */
815 spin_unlock(&sdmac->vc.lock);
816 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
817 spin_lock(&sdmac->vc.lock);
818
819 if (error)
820 sdmac->status = old_status;
821 }
822 }
823
mxc_sdma_handle_channel_normal(struct sdma_channel * data)824 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
825 {
826 struct sdma_channel *sdmac = (struct sdma_channel *) data;
827 struct sdma_buffer_descriptor *bd;
828 int i, error = 0;
829
830 sdmac->desc->chn_real_count = 0;
831 /*
832 * non loop mode. Iterate over all descriptors, collect
833 * errors and call callback function
834 */
835 for (i = 0; i < sdmac->desc->num_bd; i++) {
836 bd = &sdmac->desc->bd[i];
837
838 if (bd->mode.status & (BD_DONE | BD_RROR))
839 error = -EIO;
840 sdmac->desc->chn_real_count += bd->mode.count;
841 }
842
843 if (error)
844 sdmac->status = DMA_ERROR;
845 else
846 sdmac->status = DMA_COMPLETE;
847 }
848
sdma_int_handler(int irq,void * dev_id)849 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
850 {
851 struct sdma_engine *sdma = dev_id;
852 unsigned long stat;
853
854 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
855 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
856 /* channel 0 is special and not handled here, see run_channel0() */
857 stat &= ~1;
858
859 while (stat) {
860 int channel = fls(stat) - 1;
861 struct sdma_channel *sdmac = &sdma->channel[channel];
862 struct sdma_desc *desc;
863
864 spin_lock(&sdmac->vc.lock);
865 desc = sdmac->desc;
866 if (desc) {
867 if (sdmac->flags & IMX_DMA_SG_LOOP) {
868 sdma_update_channel_loop(sdmac);
869 } else {
870 mxc_sdma_handle_channel_normal(sdmac);
871 vchan_cookie_complete(&desc->vd);
872 sdma_start_desc(sdmac);
873 }
874 }
875
876 spin_unlock(&sdmac->vc.lock);
877 __clear_bit(channel, &stat);
878 }
879
880 return IRQ_HANDLED;
881 }
882
883 /*
884 * sets the pc of SDMA script according to the peripheral type
885 */
sdma_get_pc(struct sdma_channel * sdmac,enum sdma_peripheral_type peripheral_type)886 static void sdma_get_pc(struct sdma_channel *sdmac,
887 enum sdma_peripheral_type peripheral_type)
888 {
889 struct sdma_engine *sdma = sdmac->sdma;
890 int per_2_emi = 0, emi_2_per = 0;
891 /*
892 * These are needed once we start to support transfers between
893 * two peripherals or memory-to-memory transfers
894 */
895 int per_2_per = 0, emi_2_emi = 0;
896
897 sdmac->pc_from_device = 0;
898 sdmac->pc_to_device = 0;
899 sdmac->device_to_device = 0;
900 sdmac->pc_to_pc = 0;
901
902 switch (peripheral_type) {
903 case IMX_DMATYPE_MEMORY:
904 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
905 break;
906 case IMX_DMATYPE_DSP:
907 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
908 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
909 break;
910 case IMX_DMATYPE_FIRI:
911 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
912 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
913 break;
914 case IMX_DMATYPE_UART:
915 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
916 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
917 break;
918 case IMX_DMATYPE_UART_SP:
919 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
920 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
921 break;
922 case IMX_DMATYPE_ATA:
923 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
924 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
925 break;
926 case IMX_DMATYPE_CSPI:
927 case IMX_DMATYPE_EXT:
928 case IMX_DMATYPE_SSI:
929 case IMX_DMATYPE_SAI:
930 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
931 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
932 break;
933 case IMX_DMATYPE_SSI_DUAL:
934 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
935 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
936 break;
937 case IMX_DMATYPE_SSI_SP:
938 case IMX_DMATYPE_MMC:
939 case IMX_DMATYPE_SDHC:
940 case IMX_DMATYPE_CSPI_SP:
941 case IMX_DMATYPE_ESAI:
942 case IMX_DMATYPE_MSHC_SP:
943 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
944 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
945 break;
946 case IMX_DMATYPE_ASRC:
947 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
948 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
949 per_2_per = sdma->script_addrs->per_2_per_addr;
950 break;
951 case IMX_DMATYPE_ASRC_SP:
952 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
953 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
954 per_2_per = sdma->script_addrs->per_2_per_addr;
955 break;
956 case IMX_DMATYPE_MSHC:
957 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
958 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
959 break;
960 case IMX_DMATYPE_CCM:
961 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
962 break;
963 case IMX_DMATYPE_SPDIF:
964 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
965 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
966 break;
967 case IMX_DMATYPE_IPU_MEMORY:
968 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
969 break;
970 default:
971 break;
972 }
973
974 sdmac->pc_from_device = per_2_emi;
975 sdmac->pc_to_device = emi_2_per;
976 sdmac->device_to_device = per_2_per;
977 sdmac->pc_to_pc = emi_2_emi;
978 }
979
sdma_load_context(struct sdma_channel * sdmac)980 static int sdma_load_context(struct sdma_channel *sdmac)
981 {
982 struct sdma_engine *sdma = sdmac->sdma;
983 int channel = sdmac->channel;
984 int load_address;
985 struct sdma_context_data *context = sdma->context;
986 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
987 int ret;
988 unsigned long flags;
989
990 if (sdmac->direction == DMA_DEV_TO_MEM)
991 load_address = sdmac->pc_from_device;
992 else if (sdmac->direction == DMA_DEV_TO_DEV)
993 load_address = sdmac->device_to_device;
994 else if (sdmac->direction == DMA_MEM_TO_MEM)
995 load_address = sdmac->pc_to_pc;
996 else
997 load_address = sdmac->pc_to_device;
998
999 if (load_address < 0)
1000 return load_address;
1001
1002 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1003 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1004 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1005 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1006 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1007 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1008
1009 spin_lock_irqsave(&sdma->channel_0_lock, flags);
1010
1011 memset(context, 0, sizeof(*context));
1012 context->channel_state.pc = load_address;
1013
1014 /* Send by context the event mask,base address for peripheral
1015 * and watermark level
1016 */
1017 context->gReg[0] = sdmac->event_mask[1];
1018 context->gReg[1] = sdmac->event_mask[0];
1019 context->gReg[2] = sdmac->per_addr;
1020 context->gReg[6] = sdmac->shp_addr;
1021 context->gReg[7] = sdmac->watermark_level;
1022
1023 bd0->mode.command = C0_SETDM;
1024 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
1025 bd0->mode.count = sizeof(*context) / 4;
1026 bd0->buffer_addr = sdma->context_phys;
1027 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1028 ret = sdma_run_channel0(sdma);
1029
1030 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1031
1032 return ret;
1033 }
1034
to_sdma_chan(struct dma_chan * chan)1035 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1036 {
1037 return container_of(chan, struct sdma_channel, vc.chan);
1038 }
1039
sdma_disable_channel(struct dma_chan * chan)1040 static int sdma_disable_channel(struct dma_chan *chan)
1041 {
1042 struct sdma_channel *sdmac = to_sdma_chan(chan);
1043 struct sdma_engine *sdma = sdmac->sdma;
1044 int channel = sdmac->channel;
1045
1046 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1047 sdmac->status = DMA_ERROR;
1048
1049 return 0;
1050 }
sdma_channel_terminate_work(struct work_struct * work)1051 static void sdma_channel_terminate_work(struct work_struct *work)
1052 {
1053 struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1054 terminate_worker);
1055 unsigned long flags;
1056 LIST_HEAD(head);
1057
1058 /*
1059 * According to NXP R&D team a delay of one BD SDMA cost time
1060 * (maximum is 1ms) should be added after disable of the channel
1061 * bit, to ensure SDMA core has really been stopped after SDMA
1062 * clients call .device_terminate_all.
1063 */
1064 usleep_range(1000, 2000);
1065
1066 spin_lock_irqsave(&sdmac->vc.lock, flags);
1067 vchan_get_all_descriptors(&sdmac->vc, &head);
1068 sdmac->desc = NULL;
1069 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1070 vchan_dma_desc_free_list(&sdmac->vc, &head);
1071 }
1072
sdma_disable_channel_async(struct dma_chan * chan)1073 static int sdma_disable_channel_async(struct dma_chan *chan)
1074 {
1075 struct sdma_channel *sdmac = to_sdma_chan(chan);
1076
1077 sdma_disable_channel(chan);
1078
1079 if (sdmac->desc)
1080 schedule_work(&sdmac->terminate_worker);
1081
1082 return 0;
1083 }
1084
sdma_channel_synchronize(struct dma_chan * chan)1085 static void sdma_channel_synchronize(struct dma_chan *chan)
1086 {
1087 struct sdma_channel *sdmac = to_sdma_chan(chan);
1088
1089 vchan_synchronize(&sdmac->vc);
1090
1091 flush_work(&sdmac->terminate_worker);
1092 }
1093
sdma_set_watermarklevel_for_p2p(struct sdma_channel * sdmac)1094 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1095 {
1096 struct sdma_engine *sdma = sdmac->sdma;
1097
1098 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1099 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1100
1101 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1102 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1103
1104 if (sdmac->event_id0 > 31)
1105 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1106
1107 if (sdmac->event_id1 > 31)
1108 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1109
1110 /*
1111 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1112 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1113 * r0(event_mask[1]) and r1(event_mask[0]).
1114 */
1115 if (lwml > hwml) {
1116 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1117 SDMA_WATERMARK_LEVEL_HWML);
1118 sdmac->watermark_level |= hwml;
1119 sdmac->watermark_level |= lwml << 16;
1120 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1121 }
1122
1123 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1124 sdmac->per_address2 <= sdma->spba_end_addr)
1125 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1126
1127 if (sdmac->per_address >= sdma->spba_start_addr &&
1128 sdmac->per_address <= sdma->spba_end_addr)
1129 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1130
1131 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1132 }
1133
sdma_config_channel(struct dma_chan * chan)1134 static int sdma_config_channel(struct dma_chan *chan)
1135 {
1136 struct sdma_channel *sdmac = to_sdma_chan(chan);
1137
1138 sdma_disable_channel(chan);
1139
1140 sdmac->event_mask[0] = 0;
1141 sdmac->event_mask[1] = 0;
1142 sdmac->shp_addr = 0;
1143 sdmac->per_addr = 0;
1144
1145 switch (sdmac->peripheral_type) {
1146 case IMX_DMATYPE_DSP:
1147 sdma_config_ownership(sdmac, false, true, true);
1148 break;
1149 case IMX_DMATYPE_MEMORY:
1150 sdma_config_ownership(sdmac, false, true, false);
1151 break;
1152 default:
1153 sdma_config_ownership(sdmac, true, true, false);
1154 break;
1155 }
1156
1157 sdma_get_pc(sdmac, sdmac->peripheral_type);
1158
1159 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1160 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1161 /* Handle multiple event channels differently */
1162 if (sdmac->event_id1) {
1163 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1164 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1165 sdma_set_watermarklevel_for_p2p(sdmac);
1166 } else
1167 __set_bit(sdmac->event_id0, sdmac->event_mask);
1168
1169 /* Address */
1170 sdmac->shp_addr = sdmac->per_address;
1171 sdmac->per_addr = sdmac->per_address2;
1172 } else {
1173 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1174 }
1175
1176 return 0;
1177 }
1178
sdma_set_channel_priority(struct sdma_channel * sdmac,unsigned int priority)1179 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1180 unsigned int priority)
1181 {
1182 struct sdma_engine *sdma = sdmac->sdma;
1183 int channel = sdmac->channel;
1184
1185 if (priority < MXC_SDMA_MIN_PRIORITY
1186 || priority > MXC_SDMA_MAX_PRIORITY) {
1187 return -EINVAL;
1188 }
1189
1190 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1191
1192 return 0;
1193 }
1194
sdma_request_channel0(struct sdma_engine * sdma)1195 static int sdma_request_channel0(struct sdma_engine *sdma)
1196 {
1197 int ret = -EBUSY;
1198
1199 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
1200 GFP_NOWAIT);
1201 if (!sdma->bd0) {
1202 ret = -ENOMEM;
1203 goto out;
1204 }
1205
1206 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1207 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1208
1209 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1210 return 0;
1211 out:
1212
1213 return ret;
1214 }
1215
1216
sdma_alloc_bd(struct sdma_desc * desc)1217 static int sdma_alloc_bd(struct sdma_desc *desc)
1218 {
1219 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1220 int ret = 0;
1221
1222 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1223 &desc->bd_phys, GFP_NOWAIT);
1224 if (!desc->bd) {
1225 ret = -ENOMEM;
1226 goto out;
1227 }
1228 out:
1229 return ret;
1230 }
1231
sdma_free_bd(struct sdma_desc * desc)1232 static void sdma_free_bd(struct sdma_desc *desc)
1233 {
1234 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1235
1236 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1237 desc->bd_phys);
1238 }
1239
sdma_desc_free(struct virt_dma_desc * vd)1240 static void sdma_desc_free(struct virt_dma_desc *vd)
1241 {
1242 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1243
1244 sdma_free_bd(desc);
1245 kfree(desc);
1246 }
1247
sdma_alloc_chan_resources(struct dma_chan * chan)1248 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1249 {
1250 struct sdma_channel *sdmac = to_sdma_chan(chan);
1251 struct imx_dma_data *data = chan->private;
1252 struct imx_dma_data mem_data;
1253 int prio, ret;
1254
1255 /*
1256 * MEMCPY may never setup chan->private by filter function such as
1257 * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1258 * Please note in any other slave case, you have to setup chan->private
1259 * with 'struct imx_dma_data' in your own filter function if you want to
1260 * request dma channel by dma_request_channel() rather than
1261 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1262 * to warn you to correct your filter function.
1263 */
1264 if (!data) {
1265 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1266 mem_data.priority = 2;
1267 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1268 mem_data.dma_request = 0;
1269 mem_data.dma_request2 = 0;
1270 data = &mem_data;
1271
1272 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1273 }
1274
1275 switch (data->priority) {
1276 case DMA_PRIO_HIGH:
1277 prio = 3;
1278 break;
1279 case DMA_PRIO_MEDIUM:
1280 prio = 2;
1281 break;
1282 case DMA_PRIO_LOW:
1283 default:
1284 prio = 1;
1285 break;
1286 }
1287
1288 sdmac->peripheral_type = data->peripheral_type;
1289 sdmac->event_id0 = data->dma_request;
1290 sdmac->event_id1 = data->dma_request2;
1291
1292 ret = clk_enable(sdmac->sdma->clk_ipg);
1293 if (ret)
1294 return ret;
1295 ret = clk_enable(sdmac->sdma->clk_ahb);
1296 if (ret)
1297 goto disable_clk_ipg;
1298
1299 ret = sdma_set_channel_priority(sdmac, prio);
1300 if (ret)
1301 goto disable_clk_ahb;
1302
1303 return 0;
1304
1305 disable_clk_ahb:
1306 clk_disable(sdmac->sdma->clk_ahb);
1307 disable_clk_ipg:
1308 clk_disable(sdmac->sdma->clk_ipg);
1309 return ret;
1310 }
1311
sdma_free_chan_resources(struct dma_chan * chan)1312 static void sdma_free_chan_resources(struct dma_chan *chan)
1313 {
1314 struct sdma_channel *sdmac = to_sdma_chan(chan);
1315 struct sdma_engine *sdma = sdmac->sdma;
1316
1317 sdma_disable_channel_async(chan);
1318
1319 sdma_channel_synchronize(chan);
1320
1321 if (sdmac->event_id0 >= 0)
1322 sdma_event_disable(sdmac, sdmac->event_id0);
1323 if (sdmac->event_id1)
1324 sdma_event_disable(sdmac, sdmac->event_id1);
1325
1326 sdmac->event_id0 = 0;
1327 sdmac->event_id1 = 0;
1328
1329 sdma_set_channel_priority(sdmac, 0);
1330
1331 clk_disable(sdma->clk_ipg);
1332 clk_disable(sdma->clk_ahb);
1333 }
1334
sdma_transfer_init(struct sdma_channel * sdmac,enum dma_transfer_direction direction,u32 bds)1335 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1336 enum dma_transfer_direction direction, u32 bds)
1337 {
1338 struct sdma_desc *desc;
1339
1340 desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1341 if (!desc)
1342 goto err_out;
1343
1344 sdmac->status = DMA_IN_PROGRESS;
1345 sdmac->direction = direction;
1346 sdmac->flags = 0;
1347
1348 desc->chn_count = 0;
1349 desc->chn_real_count = 0;
1350 desc->buf_tail = 0;
1351 desc->buf_ptail = 0;
1352 desc->sdmac = sdmac;
1353 desc->num_bd = bds;
1354
1355 if (sdma_alloc_bd(desc))
1356 goto err_desc_out;
1357
1358 /* No slave_config called in MEMCPY case, so do here */
1359 if (direction == DMA_MEM_TO_MEM)
1360 sdma_config_ownership(sdmac, false, true, false);
1361
1362 if (sdma_load_context(sdmac))
1363 goto err_bd_out;
1364
1365 return desc;
1366
1367 err_bd_out:
1368 sdma_free_bd(desc);
1369 err_desc_out:
1370 kfree(desc);
1371 err_out:
1372 return NULL;
1373 }
1374
sdma_prep_memcpy(struct dma_chan * chan,dma_addr_t dma_dst,dma_addr_t dma_src,size_t len,unsigned long flags)1375 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1376 struct dma_chan *chan, dma_addr_t dma_dst,
1377 dma_addr_t dma_src, size_t len, unsigned long flags)
1378 {
1379 struct sdma_channel *sdmac = to_sdma_chan(chan);
1380 struct sdma_engine *sdma = sdmac->sdma;
1381 int channel = sdmac->channel;
1382 size_t count;
1383 int i = 0, param;
1384 struct sdma_buffer_descriptor *bd;
1385 struct sdma_desc *desc;
1386
1387 if (!chan || !len)
1388 return NULL;
1389
1390 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1391 &dma_src, &dma_dst, len, channel);
1392
1393 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1394 len / SDMA_BD_MAX_CNT + 1);
1395 if (!desc)
1396 return NULL;
1397
1398 do {
1399 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1400 bd = &desc->bd[i];
1401 bd->buffer_addr = dma_src;
1402 bd->ext_buffer_addr = dma_dst;
1403 bd->mode.count = count;
1404 desc->chn_count += count;
1405 bd->mode.command = 0;
1406
1407 dma_src += count;
1408 dma_dst += count;
1409 len -= count;
1410 i++;
1411
1412 param = BD_DONE | BD_EXTD | BD_CONT;
1413 /* last bd */
1414 if (!len) {
1415 param |= BD_INTR;
1416 param |= BD_LAST;
1417 param &= ~BD_CONT;
1418 }
1419
1420 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1421 i, count, bd->buffer_addr,
1422 param & BD_WRAP ? "wrap" : "",
1423 param & BD_INTR ? " intr" : "");
1424
1425 bd->mode.status = param;
1426 } while (len);
1427
1428 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1429 }
1430
sdma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)1431 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1432 struct dma_chan *chan, struct scatterlist *sgl,
1433 unsigned int sg_len, enum dma_transfer_direction direction,
1434 unsigned long flags, void *context)
1435 {
1436 struct sdma_channel *sdmac = to_sdma_chan(chan);
1437 struct sdma_engine *sdma = sdmac->sdma;
1438 int i, count;
1439 int channel = sdmac->channel;
1440 struct scatterlist *sg;
1441 struct sdma_desc *desc;
1442
1443 sdma_config_write(chan, &sdmac->slave_config, direction);
1444
1445 desc = sdma_transfer_init(sdmac, direction, sg_len);
1446 if (!desc)
1447 goto err_out;
1448
1449 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1450 sg_len, channel);
1451
1452 for_each_sg(sgl, sg, sg_len, i) {
1453 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1454 int param;
1455
1456 bd->buffer_addr = sg->dma_address;
1457
1458 count = sg_dma_len(sg);
1459
1460 if (count > SDMA_BD_MAX_CNT) {
1461 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1462 channel, count, SDMA_BD_MAX_CNT);
1463 goto err_bd_out;
1464 }
1465
1466 bd->mode.count = count;
1467 desc->chn_count += count;
1468
1469 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1470 goto err_bd_out;
1471
1472 switch (sdmac->word_size) {
1473 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1474 bd->mode.command = 0;
1475 if (count & 3 || sg->dma_address & 3)
1476 goto err_bd_out;
1477 break;
1478 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1479 bd->mode.command = 2;
1480 if (count & 1 || sg->dma_address & 1)
1481 goto err_bd_out;
1482 break;
1483 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1484 bd->mode.command = 1;
1485 break;
1486 default:
1487 goto err_bd_out;
1488 }
1489
1490 param = BD_DONE | BD_EXTD | BD_CONT;
1491
1492 if (i + 1 == sg_len) {
1493 param |= BD_INTR;
1494 param |= BD_LAST;
1495 param &= ~BD_CONT;
1496 }
1497
1498 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1499 i, count, (u64)sg->dma_address,
1500 param & BD_WRAP ? "wrap" : "",
1501 param & BD_INTR ? " intr" : "");
1502
1503 bd->mode.status = param;
1504 }
1505
1506 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1507 err_bd_out:
1508 sdma_free_bd(desc);
1509 kfree(desc);
1510 err_out:
1511 sdmac->status = DMA_ERROR;
1512 return NULL;
1513 }
1514
sdma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t dma_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)1515 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1516 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1517 size_t period_len, enum dma_transfer_direction direction,
1518 unsigned long flags)
1519 {
1520 struct sdma_channel *sdmac = to_sdma_chan(chan);
1521 struct sdma_engine *sdma = sdmac->sdma;
1522 int num_periods = buf_len / period_len;
1523 int channel = sdmac->channel;
1524 int i = 0, buf = 0;
1525 struct sdma_desc *desc;
1526
1527 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1528
1529 sdma_config_write(chan, &sdmac->slave_config, direction);
1530
1531 desc = sdma_transfer_init(sdmac, direction, num_periods);
1532 if (!desc)
1533 goto err_out;
1534
1535 desc->period_len = period_len;
1536
1537 sdmac->flags |= IMX_DMA_SG_LOOP;
1538
1539 if (period_len > SDMA_BD_MAX_CNT) {
1540 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1541 channel, period_len, SDMA_BD_MAX_CNT);
1542 goto err_bd_out;
1543 }
1544
1545 while (buf < buf_len) {
1546 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1547 int param;
1548
1549 bd->buffer_addr = dma_addr;
1550
1551 bd->mode.count = period_len;
1552
1553 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1554 goto err_bd_out;
1555 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1556 bd->mode.command = 0;
1557 else
1558 bd->mode.command = sdmac->word_size;
1559
1560 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1561 if (i + 1 == num_periods)
1562 param |= BD_WRAP;
1563
1564 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1565 i, period_len, (u64)dma_addr,
1566 param & BD_WRAP ? "wrap" : "",
1567 param & BD_INTR ? " intr" : "");
1568
1569 bd->mode.status = param;
1570
1571 dma_addr += period_len;
1572 buf += period_len;
1573
1574 i++;
1575 }
1576
1577 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1578 err_bd_out:
1579 sdma_free_bd(desc);
1580 kfree(desc);
1581 err_out:
1582 sdmac->status = DMA_ERROR;
1583 return NULL;
1584 }
1585
sdma_config_write(struct dma_chan * chan,struct dma_slave_config * dmaengine_cfg,enum dma_transfer_direction direction)1586 static int sdma_config_write(struct dma_chan *chan,
1587 struct dma_slave_config *dmaengine_cfg,
1588 enum dma_transfer_direction direction)
1589 {
1590 struct sdma_channel *sdmac = to_sdma_chan(chan);
1591
1592 if (direction == DMA_DEV_TO_MEM) {
1593 sdmac->per_address = dmaengine_cfg->src_addr;
1594 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1595 dmaengine_cfg->src_addr_width;
1596 sdmac->word_size = dmaengine_cfg->src_addr_width;
1597 } else if (direction == DMA_DEV_TO_DEV) {
1598 sdmac->per_address2 = dmaengine_cfg->src_addr;
1599 sdmac->per_address = dmaengine_cfg->dst_addr;
1600 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1601 SDMA_WATERMARK_LEVEL_LWML;
1602 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1603 SDMA_WATERMARK_LEVEL_HWML;
1604 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1605 } else {
1606 sdmac->per_address = dmaengine_cfg->dst_addr;
1607 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1608 dmaengine_cfg->dst_addr_width;
1609 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1610 }
1611 sdmac->direction = direction;
1612 return sdma_config_channel(chan);
1613 }
1614
sdma_config(struct dma_chan * chan,struct dma_slave_config * dmaengine_cfg)1615 static int sdma_config(struct dma_chan *chan,
1616 struct dma_slave_config *dmaengine_cfg)
1617 {
1618 struct sdma_channel *sdmac = to_sdma_chan(chan);
1619
1620 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1621
1622 /* Set ENBLn earlier to make sure dma request triggered after that */
1623 if (sdmac->event_id0 >= 0) {
1624 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1625 return -EINVAL;
1626 sdma_event_enable(sdmac, sdmac->event_id0);
1627 }
1628
1629 if (sdmac->event_id1) {
1630 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1631 return -EINVAL;
1632 sdma_event_enable(sdmac, sdmac->event_id1);
1633 }
1634
1635 return 0;
1636 }
1637
sdma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)1638 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1639 dma_cookie_t cookie,
1640 struct dma_tx_state *txstate)
1641 {
1642 struct sdma_channel *sdmac = to_sdma_chan(chan);
1643 struct sdma_desc *desc;
1644 u32 residue;
1645 struct virt_dma_desc *vd;
1646 enum dma_status ret;
1647 unsigned long flags;
1648
1649 ret = dma_cookie_status(chan, cookie, txstate);
1650 if (ret == DMA_COMPLETE || !txstate)
1651 return ret;
1652
1653 spin_lock_irqsave(&sdmac->vc.lock, flags);
1654 vd = vchan_find_desc(&sdmac->vc, cookie);
1655 if (vd) {
1656 desc = to_sdma_desc(&vd->tx);
1657 if (sdmac->flags & IMX_DMA_SG_LOOP)
1658 residue = (desc->num_bd - desc->buf_ptail) *
1659 desc->period_len - desc->chn_real_count;
1660 else
1661 residue = desc->chn_count - desc->chn_real_count;
1662 } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
1663 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count;
1664 } else {
1665 residue = 0;
1666 }
1667 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1668
1669 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1670 residue);
1671
1672 return sdmac->status;
1673 }
1674
sdma_issue_pending(struct dma_chan * chan)1675 static void sdma_issue_pending(struct dma_chan *chan)
1676 {
1677 struct sdma_channel *sdmac = to_sdma_chan(chan);
1678 unsigned long flags;
1679
1680 spin_lock_irqsave(&sdmac->vc.lock, flags);
1681 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1682 sdma_start_desc(sdmac);
1683 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1684 }
1685
1686 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1687 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1688 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1689 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1690
sdma_add_scripts(struct sdma_engine * sdma,const struct sdma_script_start_addrs * addr)1691 static void sdma_add_scripts(struct sdma_engine *sdma,
1692 const struct sdma_script_start_addrs *addr)
1693 {
1694 s32 *addr_arr = (u32 *)addr;
1695 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1696 int i;
1697
1698 /* use the default firmware in ROM if missing external firmware */
1699 if (!sdma->script_number)
1700 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1701
1702 if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1703 / sizeof(s32)) {
1704 dev_err(sdma->dev,
1705 "SDMA script number %d not match with firmware.\n",
1706 sdma->script_number);
1707 return;
1708 }
1709
1710 for (i = 0; i < sdma->script_number; i++)
1711 if (addr_arr[i] > 0)
1712 saddr_arr[i] = addr_arr[i];
1713 }
1714
sdma_load_firmware(const struct firmware * fw,void * context)1715 static void sdma_load_firmware(const struct firmware *fw, void *context)
1716 {
1717 struct sdma_engine *sdma = context;
1718 const struct sdma_firmware_header *header;
1719 const struct sdma_script_start_addrs *addr;
1720 unsigned short *ram_code;
1721
1722 if (!fw) {
1723 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1724 /* In this case we just use the ROM firmware. */
1725 return;
1726 }
1727
1728 if (fw->size < sizeof(*header))
1729 goto err_firmware;
1730
1731 header = (struct sdma_firmware_header *)fw->data;
1732
1733 if (header->magic != SDMA_FIRMWARE_MAGIC)
1734 goto err_firmware;
1735 if (header->ram_code_start + header->ram_code_size > fw->size)
1736 goto err_firmware;
1737 switch (header->version_major) {
1738 case 1:
1739 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1740 break;
1741 case 2:
1742 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1743 break;
1744 case 3:
1745 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1746 break;
1747 case 4:
1748 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1749 break;
1750 default:
1751 dev_err(sdma->dev, "unknown firmware version\n");
1752 goto err_firmware;
1753 }
1754
1755 addr = (void *)header + header->script_addrs_start;
1756 ram_code = (void *)header + header->ram_code_start;
1757
1758 clk_enable(sdma->clk_ipg);
1759 clk_enable(sdma->clk_ahb);
1760 /* download the RAM image for SDMA */
1761 sdma_load_script(sdma, ram_code,
1762 header->ram_code_size,
1763 addr->ram_code_start_addr);
1764 clk_disable(sdma->clk_ipg);
1765 clk_disable(sdma->clk_ahb);
1766
1767 sdma_add_scripts(sdma, addr);
1768
1769 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1770 header->version_major,
1771 header->version_minor);
1772
1773 err_firmware:
1774 release_firmware(fw);
1775 }
1776
1777 #define EVENT_REMAP_CELLS 3
1778
sdma_event_remap(struct sdma_engine * sdma)1779 static int sdma_event_remap(struct sdma_engine *sdma)
1780 {
1781 struct device_node *np = sdma->dev->of_node;
1782 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1783 struct property *event_remap;
1784 struct regmap *gpr;
1785 char propname[] = "fsl,sdma-event-remap";
1786 u32 reg, val, shift, num_map, i;
1787 int ret = 0;
1788
1789 if (IS_ERR(np) || !gpr_np)
1790 goto out;
1791
1792 event_remap = of_find_property(np, propname, NULL);
1793 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1794 if (!num_map) {
1795 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1796 goto out;
1797 } else if (num_map % EVENT_REMAP_CELLS) {
1798 dev_err(sdma->dev, "the property %s must modulo %d\n",
1799 propname, EVENT_REMAP_CELLS);
1800 ret = -EINVAL;
1801 goto out;
1802 }
1803
1804 gpr = syscon_node_to_regmap(gpr_np);
1805 if (IS_ERR(gpr)) {
1806 dev_err(sdma->dev, "failed to get gpr regmap\n");
1807 ret = PTR_ERR(gpr);
1808 goto out;
1809 }
1810
1811 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1812 ret = of_property_read_u32_index(np, propname, i, ®);
1813 if (ret) {
1814 dev_err(sdma->dev, "failed to read property %s index %d\n",
1815 propname, i);
1816 goto out;
1817 }
1818
1819 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1820 if (ret) {
1821 dev_err(sdma->dev, "failed to read property %s index %d\n",
1822 propname, i + 1);
1823 goto out;
1824 }
1825
1826 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1827 if (ret) {
1828 dev_err(sdma->dev, "failed to read property %s index %d\n",
1829 propname, i + 2);
1830 goto out;
1831 }
1832
1833 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1834 }
1835
1836 out:
1837 if (gpr_np)
1838 of_node_put(gpr_np);
1839
1840 return ret;
1841 }
1842
sdma_get_firmware(struct sdma_engine * sdma,const char * fw_name)1843 static int sdma_get_firmware(struct sdma_engine *sdma,
1844 const char *fw_name)
1845 {
1846 int ret;
1847
1848 ret = request_firmware_nowait(THIS_MODULE,
1849 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1850 GFP_KERNEL, sdma, sdma_load_firmware);
1851
1852 return ret;
1853 }
1854
sdma_init(struct sdma_engine * sdma)1855 static int sdma_init(struct sdma_engine *sdma)
1856 {
1857 int i, ret;
1858 dma_addr_t ccb_phys;
1859
1860 ret = clk_enable(sdma->clk_ipg);
1861 if (ret)
1862 return ret;
1863 ret = clk_enable(sdma->clk_ahb);
1864 if (ret)
1865 goto disable_clk_ipg;
1866
1867 if (sdma->drvdata->check_ratio &&
1868 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
1869 sdma->clk_ratio = 1;
1870
1871 /* Be sure SDMA has not started yet */
1872 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1873
1874 sdma->channel_control = dma_alloc_coherent(sdma->dev,
1875 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1876 sizeof(struct sdma_context_data),
1877 &ccb_phys, GFP_KERNEL);
1878
1879 if (!sdma->channel_control) {
1880 ret = -ENOMEM;
1881 goto err_dma_alloc;
1882 }
1883
1884 sdma->context = (void *)sdma->channel_control +
1885 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1886 sdma->context_phys = ccb_phys +
1887 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1888
1889 /* disable all channels */
1890 for (i = 0; i < sdma->drvdata->num_events; i++)
1891 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1892
1893 /* All channels have priority 0 */
1894 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1895 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1896
1897 ret = sdma_request_channel0(sdma);
1898 if (ret)
1899 goto err_dma_alloc;
1900
1901 sdma_config_ownership(&sdma->channel[0], false, true, false);
1902
1903 /* Set Command Channel (Channel Zero) */
1904 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1905
1906 /* Set bits of CONFIG register but with static context switching */
1907 if (sdma->clk_ratio)
1908 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
1909 else
1910 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1911
1912 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1913
1914 /* Initializes channel's priorities */
1915 sdma_set_channel_priority(&sdma->channel[0], 7);
1916
1917 clk_disable(sdma->clk_ipg);
1918 clk_disable(sdma->clk_ahb);
1919
1920 return 0;
1921
1922 err_dma_alloc:
1923 clk_disable(sdma->clk_ahb);
1924 disable_clk_ipg:
1925 clk_disable(sdma->clk_ipg);
1926 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1927 return ret;
1928 }
1929
sdma_filter_fn(struct dma_chan * chan,void * fn_param)1930 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1931 {
1932 struct sdma_channel *sdmac = to_sdma_chan(chan);
1933 struct imx_dma_data *data = fn_param;
1934
1935 if (!imx_dma_is_general_purpose(chan))
1936 return false;
1937
1938 sdmac->data = *data;
1939 chan->private = &sdmac->data;
1940
1941 return true;
1942 }
1943
sdma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1944 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1945 struct of_dma *ofdma)
1946 {
1947 struct sdma_engine *sdma = ofdma->of_dma_data;
1948 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1949 struct imx_dma_data data;
1950
1951 if (dma_spec->args_count != 3)
1952 return NULL;
1953
1954 data.dma_request = dma_spec->args[0];
1955 data.peripheral_type = dma_spec->args[1];
1956 data.priority = dma_spec->args[2];
1957 /*
1958 * init dma_request2 to zero, which is not used by the dts.
1959 * For P2P, dma_request2 is init from dma_request_channel(),
1960 * chan->private will point to the imx_dma_data, and in
1961 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1962 * be set to sdmac->event_id1.
1963 */
1964 data.dma_request2 = 0;
1965
1966 return __dma_request_channel(&mask, sdma_filter_fn, &data,
1967 ofdma->of_node);
1968 }
1969
sdma_probe(struct platform_device * pdev)1970 static int sdma_probe(struct platform_device *pdev)
1971 {
1972 const struct of_device_id *of_id =
1973 of_match_device(sdma_dt_ids, &pdev->dev);
1974 struct device_node *np = pdev->dev.of_node;
1975 struct device_node *spba_bus;
1976 const char *fw_name;
1977 int ret;
1978 int irq;
1979 struct resource *iores;
1980 struct resource spba_res;
1981 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1982 int i;
1983 struct sdma_engine *sdma;
1984 s32 *saddr_arr;
1985 const struct sdma_driver_data *drvdata = NULL;
1986
1987 if (of_id)
1988 drvdata = of_id->data;
1989 else if (pdev->id_entry)
1990 drvdata = (void *)pdev->id_entry->driver_data;
1991
1992 if (!drvdata) {
1993 dev_err(&pdev->dev, "unable to find driver data\n");
1994 return -EINVAL;
1995 }
1996
1997 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1998 if (ret)
1999 return ret;
2000
2001 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
2002 if (!sdma)
2003 return -ENOMEM;
2004
2005 spin_lock_init(&sdma->channel_0_lock);
2006
2007 sdma->dev = &pdev->dev;
2008 sdma->drvdata = drvdata;
2009
2010 irq = platform_get_irq(pdev, 0);
2011 if (irq < 0)
2012 return irq;
2013
2014 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2015 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
2016 if (IS_ERR(sdma->regs))
2017 return PTR_ERR(sdma->regs);
2018
2019 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2020 if (IS_ERR(sdma->clk_ipg))
2021 return PTR_ERR(sdma->clk_ipg);
2022
2023 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2024 if (IS_ERR(sdma->clk_ahb))
2025 return PTR_ERR(sdma->clk_ahb);
2026
2027 ret = clk_prepare(sdma->clk_ipg);
2028 if (ret)
2029 return ret;
2030
2031 ret = clk_prepare(sdma->clk_ahb);
2032 if (ret)
2033 goto err_clk;
2034
2035 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
2036 sdma);
2037 if (ret)
2038 goto err_irq;
2039
2040 sdma->irq = irq;
2041
2042 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2043 if (!sdma->script_addrs) {
2044 ret = -ENOMEM;
2045 goto err_irq;
2046 }
2047
2048 /* initially no scripts available */
2049 saddr_arr = (s32 *)sdma->script_addrs;
2050 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
2051 saddr_arr[i] = -EINVAL;
2052
2053 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2054 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2055 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2056
2057 INIT_LIST_HEAD(&sdma->dma_device.channels);
2058 /* Initialize channel parameters */
2059 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2060 struct sdma_channel *sdmac = &sdma->channel[i];
2061
2062 sdmac->sdma = sdma;
2063
2064 sdmac->channel = i;
2065 sdmac->vc.desc_free = sdma_desc_free;
2066 INIT_WORK(&sdmac->terminate_worker,
2067 sdma_channel_terminate_work);
2068 /*
2069 * Add the channel to the DMAC list. Do not add channel 0 though
2070 * because we need it internally in the SDMA driver. This also means
2071 * that channel 0 in dmaengine counting matches sdma channel 1.
2072 */
2073 if (i)
2074 vchan_init(&sdmac->vc, &sdma->dma_device);
2075 }
2076
2077 ret = sdma_init(sdma);
2078 if (ret)
2079 goto err_init;
2080
2081 ret = sdma_event_remap(sdma);
2082 if (ret)
2083 goto err_init;
2084
2085 if (sdma->drvdata->script_addrs)
2086 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2087 if (pdata && pdata->script_addrs)
2088 sdma_add_scripts(sdma, pdata->script_addrs);
2089
2090 sdma->dma_device.dev = &pdev->dev;
2091
2092 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2093 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2094 sdma->dma_device.device_tx_status = sdma_tx_status;
2095 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2096 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2097 sdma->dma_device.device_config = sdma_config;
2098 sdma->dma_device.device_terminate_all = sdma_disable_channel_async;
2099 sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2100 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2101 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2102 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2103 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2104 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2105 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2106 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
2107 sdma->dma_device.copy_align = 2;
2108 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2109
2110 platform_set_drvdata(pdev, sdma);
2111
2112 ret = dma_async_device_register(&sdma->dma_device);
2113 if (ret) {
2114 dev_err(&pdev->dev, "unable to register\n");
2115 goto err_init;
2116 }
2117
2118 if (np) {
2119 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2120 if (ret) {
2121 dev_err(&pdev->dev, "failed to register controller\n");
2122 goto err_register;
2123 }
2124
2125 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2126 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2127 if (!ret) {
2128 sdma->spba_start_addr = spba_res.start;
2129 sdma->spba_end_addr = spba_res.end;
2130 }
2131 of_node_put(spba_bus);
2132 }
2133
2134 /*
2135 * Kick off firmware loading as the very last step:
2136 * attempt to load firmware only if we're not on the error path, because
2137 * the firmware callback requires a fully functional and allocated sdma
2138 * instance.
2139 */
2140 if (pdata) {
2141 ret = sdma_get_firmware(sdma, pdata->fw_name);
2142 if (ret)
2143 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
2144 } else {
2145 /*
2146 * Because that device tree does not encode ROM script address,
2147 * the RAM script in firmware is mandatory for device tree
2148 * probe, otherwise it fails.
2149 */
2150 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2151 &fw_name);
2152 if (ret) {
2153 dev_warn(&pdev->dev, "failed to get firmware name\n");
2154 } else {
2155 ret = sdma_get_firmware(sdma, fw_name);
2156 if (ret)
2157 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2158 }
2159 }
2160
2161 return 0;
2162
2163 err_register:
2164 dma_async_device_unregister(&sdma->dma_device);
2165 err_init:
2166 kfree(sdma->script_addrs);
2167 err_irq:
2168 clk_unprepare(sdma->clk_ahb);
2169 err_clk:
2170 clk_unprepare(sdma->clk_ipg);
2171 return ret;
2172 }
2173
sdma_remove(struct platform_device * pdev)2174 static int sdma_remove(struct platform_device *pdev)
2175 {
2176 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2177 int i;
2178
2179 devm_free_irq(&pdev->dev, sdma->irq, sdma);
2180 dma_async_device_unregister(&sdma->dma_device);
2181 kfree(sdma->script_addrs);
2182 clk_unprepare(sdma->clk_ahb);
2183 clk_unprepare(sdma->clk_ipg);
2184 /* Kill the tasklet */
2185 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2186 struct sdma_channel *sdmac = &sdma->channel[i];
2187
2188 tasklet_kill(&sdmac->vc.task);
2189 sdma_free_chan_resources(&sdmac->vc.chan);
2190 }
2191
2192 platform_set_drvdata(pdev, NULL);
2193 return 0;
2194 }
2195
2196 static struct platform_driver sdma_driver = {
2197 .driver = {
2198 .name = "imx-sdma",
2199 .of_match_table = sdma_dt_ids,
2200 },
2201 .id_table = sdma_devtypes,
2202 .remove = sdma_remove,
2203 .probe = sdma_probe,
2204 };
2205
2206 module_platform_driver(sdma_driver);
2207
2208 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2209 MODULE_DESCRIPTION("i.MX SDMA driver");
2210 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2211 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2212 #endif
2213 #if IS_ENABLED(CONFIG_SOC_IMX7D) || IS_ENABLED(CONFIG_SOC_IMX8M)
2214 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2215 #endif
2216 MODULE_LICENSE("GPL");
2217