1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
4 */
5 #ifndef IOATDMA_H
6 #define IOATDMA_H
7
8 #include <linux/dmaengine.h>
9 #include <linux/init.h>
10 #include <linux/dmapool.h>
11 #include <linux/cache.h>
12 #include <linux/pci_ids.h>
13 #include <linux/circ_buf.h>
14 #include <linux/interrupt.h>
15 #include "registers.h"
16 #include "hw.h"
17
18 #define IOAT_DMA_VERSION "5.00"
19
20 #define IOAT_DMA_DCA_ANY_CPU ~0
21
22 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev)
23 #define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev)
24 #define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev)
25
26 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80)
27
28 /* ioat hardware assumes at least two sources for raid operations */
29 #define src_cnt_to_sw(x) ((x) + 2)
30 #define src_cnt_to_hw(x) ((x) - 2)
31 #define ndest_to_sw(x) ((x) + 1)
32 #define ndest_to_hw(x) ((x) - 1)
33 #define src16_cnt_to_sw(x) ((x) + 9)
34 #define src16_cnt_to_hw(x) ((x) - 9)
35
36 /*
37 * workaround for IOAT ver.3.0 null descriptor issue
38 * (channel returns error when size is 0)
39 */
40 #define NULL_DESC_BUFFER_SIZE 1
41
42 enum ioat_irq_mode {
43 IOAT_NOIRQ = 0,
44 IOAT_MSIX,
45 IOAT_MSI,
46 IOAT_INTX
47 };
48
49 /**
50 * struct ioatdma_device - internal representation of a IOAT device
51 * @pdev: PCI-Express device
52 * @reg_base: MMIO register space base address
53 * @completion_pool: DMA buffers for completion ops
54 * @sed_hw_pool: DMA super descriptor pools
55 * @dma_dev: embedded struct dma_device
56 * @version: version of ioatdma device
57 * @msix_entries: irq handlers
58 * @idx: per channel data
59 * @dca: direct cache access context
60 * @irq_mode: interrupt mode (INTX, MSI, MSIX)
61 * @cap: read DMA capabilities register
62 */
63 struct ioatdma_device {
64 struct pci_dev *pdev;
65 void __iomem *reg_base;
66 struct dma_pool *completion_pool;
67 #define MAX_SED_POOLS 5
68 struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
69 struct dma_device dma_dev;
70 u8 version;
71 #define IOAT_MAX_CHANS 4
72 struct msix_entry msix_entries[IOAT_MAX_CHANS];
73 struct ioatdma_chan *idx[IOAT_MAX_CHANS];
74 struct dca_provider *dca;
75 enum ioat_irq_mode irq_mode;
76 u32 cap;
77
78 /* shadow version for CB3.3 chan reset errata workaround */
79 u64 msixtba0;
80 u64 msixdata0;
81 u32 msixpba;
82 };
83
84 struct ioat_descs {
85 void *virt;
86 dma_addr_t hw;
87 };
88
89 struct ioatdma_chan {
90 struct dma_chan dma_chan;
91 void __iomem *reg_base;
92 dma_addr_t last_completion;
93 spinlock_t cleanup_lock;
94 unsigned long state;
95 #define IOAT_CHAN_DOWN 0
96 #define IOAT_COMPLETION_ACK 1
97 #define IOAT_RESET_PENDING 2
98 #define IOAT_KOBJ_INIT_FAIL 3
99 #define IOAT_RUN 5
100 #define IOAT_CHAN_ACTIVE 6
101 struct timer_list timer;
102 #define RESET_DELAY msecs_to_jiffies(100)
103 struct ioatdma_device *ioat_dma;
104 dma_addr_t completion_dma;
105 u64 *completion;
106 struct tasklet_struct cleanup_task;
107 struct kobject kobj;
108
109 /* ioat v2 / v3 channel attributes
110 * @xfercap_log; log2 of channel max transfer length (for fast division)
111 * @head: allocated index
112 * @issued: hardware notification point
113 * @tail: cleanup index
114 * @dmacount: identical to 'head' except for occasionally resetting to zero
115 * @alloc_order: log2 of the number of allocated descriptors
116 * @produce: number of descriptors to produce at submit time
117 * @ring: software ring buffer implementation of hardware ring
118 * @prep_lock: serializes descriptor preparation (producers)
119 */
120 size_t xfercap_log;
121 u16 head;
122 u16 issued;
123 u16 tail;
124 u16 dmacount;
125 u16 alloc_order;
126 u16 produce;
127 struct ioat_ring_ent **ring;
128 spinlock_t prep_lock;
129 struct ioat_descs descs[2];
130 int desc_chunks;
131 int intr_coalesce;
132 int prev_intr_coalesce;
133 };
134
135 struct ioat_sysfs_entry {
136 struct attribute attr;
137 ssize_t (*show)(struct dma_chan *, char *);
138 ssize_t (*store)(struct dma_chan *, const char *, size_t);
139 };
140
141 /**
142 * struct ioat_sed_ent - wrapper around super extended hardware descriptor
143 * @hw: hardware SED
144 * @dma: dma address for the SED
145 * @parent: point to the dma descriptor that's the parent
146 * @hw_pool: descriptor pool index
147 */
148 struct ioat_sed_ent {
149 struct ioat_sed_raw_descriptor *hw;
150 dma_addr_t dma;
151 struct ioat_ring_ent *parent;
152 unsigned int hw_pool;
153 };
154
155 /**
156 * struct ioat_ring_ent - wrapper around hardware descriptor
157 * @hw: hardware DMA descriptor (for memcpy)
158 * @xor: hardware xor descriptor
159 * @xor_ex: hardware xor extension descriptor
160 * @pq: hardware pq descriptor
161 * @pq_ex: hardware pq extension descriptor
162 * @pqu: hardware pq update descriptor
163 * @raw: hardware raw (un-typed) descriptor
164 * @txd: the generic software descriptor for all engines
165 * @len: total transaction length for unmap
166 * @result: asynchronous result of validate operations
167 * @id: identifier for debug
168 * @sed: pointer to super extended descriptor sw desc
169 */
170
171 struct ioat_ring_ent {
172 union {
173 struct ioat_dma_descriptor *hw;
174 struct ioat_xor_descriptor *xor;
175 struct ioat_xor_ext_descriptor *xor_ex;
176 struct ioat_pq_descriptor *pq;
177 struct ioat_pq_ext_descriptor *pq_ex;
178 struct ioat_pq_update_descriptor *pqu;
179 struct ioat_raw_descriptor *raw;
180 };
181 size_t len;
182 struct dma_async_tx_descriptor txd;
183 enum sum_check_flags *result;
184 #ifdef DEBUG
185 int id;
186 #endif
187 struct ioat_sed_ent *sed;
188 };
189
190 extern const struct sysfs_ops ioat_sysfs_ops;
191 extern struct ioat_sysfs_entry ioat_version_attr;
192 extern struct ioat_sysfs_entry ioat_cap_attr;
193 extern int ioat_pending_level;
194 extern int ioat_ring_alloc_order;
195 extern struct kobj_type ioat_ktype;
196 extern struct kmem_cache *ioat_cache;
197 extern int ioat_ring_max_alloc_order;
198 extern struct kmem_cache *ioat_sed_cache;
199
to_ioat_chan(struct dma_chan * c)200 static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c)
201 {
202 return container_of(c, struct ioatdma_chan, dma_chan);
203 }
204
205 /* wrapper around hardware descriptor format + additional software fields */
206 #ifdef DEBUG
207 #define set_desc_id(desc, i) ((desc)->id = (i))
208 #define desc_id(desc) ((desc)->id)
209 #else
210 #define set_desc_id(desc, i)
211 #define desc_id(desc) (0)
212 #endif
213
214 static inline void
__dump_desc_dbg(struct ioatdma_chan * ioat_chan,struct ioat_dma_descriptor * hw,struct dma_async_tx_descriptor * tx,int id)215 __dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw,
216 struct dma_async_tx_descriptor *tx, int id)
217 {
218 struct device *dev = to_dev(ioat_chan);
219
220 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
221 " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
222 (unsigned long long) tx->phys,
223 (unsigned long long) hw->next, tx->cookie, tx->flags,
224 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
225 }
226
227 #define dump_desc_dbg(c, d) \
228 ({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; })
229
230 static inline struct ioatdma_chan *
ioat_chan_by_index(struct ioatdma_device * ioat_dma,int index)231 ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index)
232 {
233 return ioat_dma->idx[index];
234 }
235
ioat_chansts(struct ioatdma_chan * ioat_chan)236 static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
237 {
238 return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
239 }
240
ioat_chansts_to_addr(u64 status)241 static inline u64 ioat_chansts_to_addr(u64 status)
242 {
243 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
244 }
245
ioat_chanerr(struct ioatdma_chan * ioat_chan)246 static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan)
247 {
248 return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
249 }
250
ioat_suspend(struct ioatdma_chan * ioat_chan)251 static inline void ioat_suspend(struct ioatdma_chan *ioat_chan)
252 {
253 u8 ver = ioat_chan->ioat_dma->version;
254
255 writeb(IOAT_CHANCMD_SUSPEND,
256 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
257 }
258
ioat_reset(struct ioatdma_chan * ioat_chan)259 static inline void ioat_reset(struct ioatdma_chan *ioat_chan)
260 {
261 u8 ver = ioat_chan->ioat_dma->version;
262
263 writeb(IOAT_CHANCMD_RESET,
264 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
265 }
266
ioat_reset_pending(struct ioatdma_chan * ioat_chan)267 static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan)
268 {
269 u8 ver = ioat_chan->ioat_dma->version;
270 u8 cmd;
271
272 cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
273 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
274 }
275
is_ioat_active(unsigned long status)276 static inline bool is_ioat_active(unsigned long status)
277 {
278 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
279 }
280
is_ioat_idle(unsigned long status)281 static inline bool is_ioat_idle(unsigned long status)
282 {
283 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
284 }
285
is_ioat_halted(unsigned long status)286 static inline bool is_ioat_halted(unsigned long status)
287 {
288 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
289 }
290
is_ioat_suspended(unsigned long status)291 static inline bool is_ioat_suspended(unsigned long status)
292 {
293 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
294 }
295
296 /* channel was fatally programmed */
is_ioat_bug(unsigned long err)297 static inline bool is_ioat_bug(unsigned long err)
298 {
299 return !!err;
300 }
301
302 #define IOAT_MAX_ORDER 16
303 #define IOAT_MAX_DESCS 65536
304 #define IOAT_DESCS_PER_2M 32768
305
ioat_ring_size(struct ioatdma_chan * ioat_chan)306 static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
307 {
308 return 1 << ioat_chan->alloc_order;
309 }
310
311 /* count of descriptors in flight with the engine */
ioat_ring_active(struct ioatdma_chan * ioat_chan)312 static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan)
313 {
314 return CIRC_CNT(ioat_chan->head, ioat_chan->tail,
315 ioat_ring_size(ioat_chan));
316 }
317
318 /* count of descriptors pending submission to hardware */
ioat_ring_pending(struct ioatdma_chan * ioat_chan)319 static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan)
320 {
321 return CIRC_CNT(ioat_chan->head, ioat_chan->issued,
322 ioat_ring_size(ioat_chan));
323 }
324
ioat_ring_space(struct ioatdma_chan * ioat_chan)325 static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan)
326 {
327 return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan);
328 }
329
330 static inline u16
ioat_xferlen_to_descs(struct ioatdma_chan * ioat_chan,size_t len)331 ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len)
332 {
333 u16 num_descs = len >> ioat_chan->xfercap_log;
334
335 num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1));
336 return num_descs;
337 }
338
339 static inline struct ioat_ring_ent *
ioat_get_ring_ent(struct ioatdma_chan * ioat_chan,u16 idx)340 ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx)
341 {
342 return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)];
343 }
344
345 static inline void
ioat_set_chainaddr(struct ioatdma_chan * ioat_chan,u64 addr)346 ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr)
347 {
348 writel(addr & 0x00000000FFFFFFFF,
349 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
350 writel(addr >> 32,
351 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
352 }
353
354 /* IOAT Prep functions */
355 struct dma_async_tx_descriptor *
356 ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
357 dma_addr_t dma_src, size_t len, unsigned long flags);
358 struct dma_async_tx_descriptor *
359 ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags);
360 struct dma_async_tx_descriptor *
361 ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
362 unsigned int src_cnt, size_t len, unsigned long flags);
363 struct dma_async_tx_descriptor *
364 ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
365 unsigned int src_cnt, size_t len,
366 enum sum_check_flags *result, unsigned long flags);
367 struct dma_async_tx_descriptor *
368 ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
369 unsigned int src_cnt, const unsigned char *scf, size_t len,
370 unsigned long flags);
371 struct dma_async_tx_descriptor *
372 ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
373 unsigned int src_cnt, const unsigned char *scf, size_t len,
374 enum sum_check_flags *pqres, unsigned long flags);
375 struct dma_async_tx_descriptor *
376 ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
377 unsigned int src_cnt, size_t len, unsigned long flags);
378 struct dma_async_tx_descriptor *
379 ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
380 unsigned int src_cnt, size_t len,
381 enum sum_check_flags *result, unsigned long flags);
382
383 /* IOAT Operation functions */
384 irqreturn_t ioat_dma_do_interrupt(int irq, void *data);
385 irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data);
386 struct ioat_ring_ent **
387 ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags);
388 void ioat_start_null_desc(struct ioatdma_chan *ioat_chan);
389 void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan);
390 int ioat_reset_hw(struct ioatdma_chan *ioat_chan);
391 enum dma_status
392 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
393 struct dma_tx_state *txstate);
394 void ioat_cleanup_event(unsigned long data);
395 void ioat_timer_event(struct timer_list *t);
396 int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs);
397 void ioat_issue_pending(struct dma_chan *chan);
398
399 /* IOAT Init functions */
400 bool is_bwd_ioat(struct pci_dev *pdev);
401 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
402 void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type);
403 void ioat_kobject_del(struct ioatdma_device *ioat_dma);
404 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma);
405 void ioat_stop(struct ioatdma_chan *ioat_chan);
406 #endif /* IOATDMA_H */
407