1 /*
2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2016 Freescale Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/spinlock.h>
15 #include <linux/io.h>
16 #include <linux/of.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/slab.h>
22 #include <linux/irq.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/bitops.h>
25
26 #define MPC8XXX_GPIO_PINS 32
27
28 #define GPIO_DIR 0x00
29 #define GPIO_ODR 0x04
30 #define GPIO_DAT 0x08
31 #define GPIO_IER 0x0c
32 #define GPIO_IMR 0x10
33 #define GPIO_ICR 0x14
34 #define GPIO_ICR2 0x18
35 #define GPIO_IBE 0x18
36
37 struct mpc8xxx_gpio_chip {
38 struct gpio_chip gc;
39 void __iomem *regs;
40 raw_spinlock_t lock;
41
42 int (*direction_output)(struct gpio_chip *chip,
43 unsigned offset, int value);
44
45 struct irq_domain *irq;
46 unsigned int irqn;
47 };
48
49 /* The GPIO Input Buffer Enable register(GPIO_IBE) is used to
50 * control the input enable of each individual GPIO port.
51 * When an individual GPIO port’s direction is set to
52 * input (GPIO_GPDIR[DRn=0]), the associated input enable must be
53 * set (GPIOxGPIE[IEn]=1) to propagate the port value to the GPIO
54 * Data Register.
55 */
ls1028a_gpio_dir_in_init(struct gpio_chip * gc)56 static int ls1028a_gpio_dir_in_init(struct gpio_chip *gc)
57 {
58 unsigned long flags;
59 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
60
61 spin_lock_irqsave(&gc->bgpio_lock, flags);
62
63 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
64
65 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
66
67 return 0;
68 }
69
70 /*
71 * This hardware has a big endian bit assignment such that GPIO line 0 is
72 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
73 * This inline helper give the right bitmask for a certain line.
74 */
mpc_pin2mask(unsigned int offset)75 static inline u32 mpc_pin2mask(unsigned int offset)
76 {
77 return BIT(31 - offset);
78 }
79
80 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
81 * defined as output cannot be determined by reading GPDAT register,
82 * so we use shadow data register instead. The status of input pins
83 * is determined by reading GPDAT register.
84 */
mpc8572_gpio_get(struct gpio_chip * gc,unsigned int gpio)85 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
86 {
87 u32 val;
88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
89 u32 out_mask, out_shadow;
90
91 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
92 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
93 out_shadow = gc->bgpio_data & out_mask;
94
95 return !!((val | out_shadow) & mpc_pin2mask(gpio));
96 }
97
mpc5121_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)98 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
99 unsigned int gpio, int val)
100 {
101 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
102 /* GPIO 28..31 are input only on MPC5121 */
103 if (gpio >= 28)
104 return -EINVAL;
105
106 return mpc8xxx_gc->direction_output(gc, gpio, val);
107 }
108
mpc5125_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)109 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
110 unsigned int gpio, int val)
111 {
112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
113 /* GPIO 0..3 are input only on MPC5125 */
114 if (gpio <= 3)
115 return -EINVAL;
116
117 return mpc8xxx_gc->direction_output(gc, gpio, val);
118 }
119
mpc8xxx_gpio_to_irq(struct gpio_chip * gc,unsigned offset)120 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
121 {
122 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
123
124 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
125 return irq_create_mapping(mpc8xxx_gc->irq, offset);
126 else
127 return -ENXIO;
128 }
129
mpc8xxx_gpio_irq_cascade(struct irq_desc * desc)130 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
131 {
132 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
133 struct irq_chip *chip = irq_desc_get_chip(desc);
134 struct gpio_chip *gc = &mpc8xxx_gc->gc;
135 unsigned int mask;
136
137 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
138 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
139 if (mask)
140 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
141 32 - ffs(mask)));
142 if (chip->irq_eoi)
143 chip->irq_eoi(&desc->irq_data);
144 }
145
mpc8xxx_irq_unmask(struct irq_data * d)146 static void mpc8xxx_irq_unmask(struct irq_data *d)
147 {
148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
149 struct gpio_chip *gc = &mpc8xxx_gc->gc;
150 unsigned long flags;
151
152 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
153
154 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
155 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
156 | mpc_pin2mask(irqd_to_hwirq(d)));
157
158 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
159 }
160
mpc8xxx_irq_mask(struct irq_data * d)161 static void mpc8xxx_irq_mask(struct irq_data *d)
162 {
163 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
164 struct gpio_chip *gc = &mpc8xxx_gc->gc;
165 unsigned long flags;
166
167 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
168
169 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
170 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
171 & ~mpc_pin2mask(irqd_to_hwirq(d)));
172
173 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
174 }
175
mpc8xxx_irq_ack(struct irq_data * d)176 static void mpc8xxx_irq_ack(struct irq_data *d)
177 {
178 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
179 struct gpio_chip *gc = &mpc8xxx_gc->gc;
180
181 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
182 mpc_pin2mask(irqd_to_hwirq(d)));
183 }
184
mpc8xxx_irq_set_type(struct irq_data * d,unsigned int flow_type)185 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
186 {
187 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
188 struct gpio_chip *gc = &mpc8xxx_gc->gc;
189 unsigned long flags;
190
191 switch (flow_type) {
192 case IRQ_TYPE_EDGE_FALLING:
193 case IRQ_TYPE_LEVEL_LOW:
194 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
195 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
196 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
197 | mpc_pin2mask(irqd_to_hwirq(d)));
198 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
199 break;
200
201 case IRQ_TYPE_EDGE_BOTH:
202 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
203 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
204 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
205 & ~mpc_pin2mask(irqd_to_hwirq(d)));
206 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
207 break;
208
209 default:
210 return -EINVAL;
211 }
212
213 return 0;
214 }
215
mpc512x_irq_set_type(struct irq_data * d,unsigned int flow_type)216 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
217 {
218 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
219 struct gpio_chip *gc = &mpc8xxx_gc->gc;
220 unsigned long gpio = irqd_to_hwirq(d);
221 void __iomem *reg;
222 unsigned int shift;
223 unsigned long flags;
224
225 if (gpio < 16) {
226 reg = mpc8xxx_gc->regs + GPIO_ICR;
227 shift = (15 - gpio) * 2;
228 } else {
229 reg = mpc8xxx_gc->regs + GPIO_ICR2;
230 shift = (15 - (gpio % 16)) * 2;
231 }
232
233 switch (flow_type) {
234 case IRQ_TYPE_EDGE_FALLING:
235 case IRQ_TYPE_LEVEL_LOW:
236 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
237 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
238 | (2 << shift));
239 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
240 break;
241
242 case IRQ_TYPE_EDGE_RISING:
243 case IRQ_TYPE_LEVEL_HIGH:
244 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
245 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
246 | (1 << shift));
247 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
248 break;
249
250 case IRQ_TYPE_EDGE_BOTH:
251 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
252 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
253 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
254 break;
255
256 default:
257 return -EINVAL;
258 }
259
260 return 0;
261 }
262
263 static struct irq_chip mpc8xxx_irq_chip = {
264 .name = "mpc8xxx-gpio",
265 .irq_unmask = mpc8xxx_irq_unmask,
266 .irq_mask = mpc8xxx_irq_mask,
267 .irq_ack = mpc8xxx_irq_ack,
268 /* this might get overwritten in mpc8xxx_probe() */
269 .irq_set_type = mpc8xxx_irq_set_type,
270 };
271
mpc8xxx_gpio_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)272 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
273 irq_hw_number_t hwirq)
274 {
275 irq_set_chip_data(irq, h->host_data);
276 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
277
278 return 0;
279 }
280
281 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
282 .map = mpc8xxx_gpio_irq_map,
283 .xlate = irq_domain_xlate_twocell,
284 };
285
286 struct mpc8xxx_gpio_devtype {
287 int (*gpio_dir_in_init)(struct gpio_chip *chip);
288 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
289 int (*gpio_get)(struct gpio_chip *, unsigned int);
290 int (*irq_set_type)(struct irq_data *, unsigned int);
291 };
292
293 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
294 .gpio_dir_out = mpc5121_gpio_dir_out,
295 .irq_set_type = mpc512x_irq_set_type,
296 };
297
298 static const struct mpc8xxx_gpio_devtype ls1028a_gpio_devtype = {
299 .gpio_dir_in_init = ls1028a_gpio_dir_in_init,
300 };
301
302 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
303 .gpio_dir_out = mpc5125_gpio_dir_out,
304 .irq_set_type = mpc512x_irq_set_type,
305 };
306
307 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
308 .gpio_get = mpc8572_gpio_get,
309 };
310
311 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
312 .irq_set_type = mpc8xxx_irq_set_type,
313 };
314
315 static const struct of_device_id mpc8xxx_gpio_ids[] = {
316 { .compatible = "fsl,mpc8349-gpio", },
317 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
318 { .compatible = "fsl,mpc8610-gpio", },
319 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
320 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
321 { .compatible = "fsl,pq3-gpio", },
322 { .compatible = "fsl,ls1028a-gpio", .data = &ls1028a_gpio_devtype, },
323 { .compatible = "fsl,ls1088a-gpio", .data = &ls1028a_gpio_devtype, },
324 { .compatible = "fsl,qoriq-gpio", },
325 {}
326 };
327
mpc8xxx_probe(struct platform_device * pdev)328 static int mpc8xxx_probe(struct platform_device *pdev)
329 {
330 struct device_node *np = pdev->dev.of_node;
331 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
332 struct gpio_chip *gc;
333 const struct mpc8xxx_gpio_devtype *devtype =
334 of_device_get_match_data(&pdev->dev);
335 int ret;
336
337 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
338 if (!mpc8xxx_gc)
339 return -ENOMEM;
340
341 platform_set_drvdata(pdev, mpc8xxx_gc);
342
343 raw_spin_lock_init(&mpc8xxx_gc->lock);
344
345 mpc8xxx_gc->regs = of_iomap(np, 0);
346 if (!mpc8xxx_gc->regs)
347 return -ENOMEM;
348
349 gc = &mpc8xxx_gc->gc;
350 gc->parent = &pdev->dev;
351
352 if (of_property_read_bool(np, "little-endian")) {
353 ret = bgpio_init(gc, &pdev->dev, 4,
354 mpc8xxx_gc->regs + GPIO_DAT,
355 NULL, NULL,
356 mpc8xxx_gc->regs + GPIO_DIR, NULL,
357 BGPIOF_BIG_ENDIAN);
358 if (ret)
359 goto err;
360 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
361 } else {
362 ret = bgpio_init(gc, &pdev->dev, 4,
363 mpc8xxx_gc->regs + GPIO_DAT,
364 NULL, NULL,
365 mpc8xxx_gc->regs + GPIO_DIR, NULL,
366 BGPIOF_BIG_ENDIAN
367 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
368 if (ret)
369 goto err;
370 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
371 }
372
373 mpc8xxx_gc->direction_output = gc->direction_output;
374
375 if (!devtype)
376 devtype = &mpc8xxx_gpio_devtype_default;
377
378 /*
379 * It's assumed that only a single type of gpio controller is available
380 * on the current machine, so overwriting global data is fine.
381 */
382 if (devtype->irq_set_type)
383 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
384
385 if (devtype->gpio_dir_out)
386 gc->direction_output = devtype->gpio_dir_out;
387 if (devtype->gpio_get)
388 gc->get = devtype->gpio_get;
389
390 gc->to_irq = mpc8xxx_gpio_to_irq;
391
392 if (of_device_is_compatible(np, "fsl,qoriq-gpio"))
393 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
394
395 ret = gpiochip_add_data(gc, mpc8xxx_gc);
396 if (ret) {
397 pr_err("%pOF: GPIO chip registration failed with status %d\n",
398 np, ret);
399 goto err;
400 }
401
402 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
403 if (!mpc8xxx_gc->irqn)
404 return 0;
405
406 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
407 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
408 if (!mpc8xxx_gc->irq)
409 return 0;
410
411 /* ack and mask all irqs */
412 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
413 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
414 /* enable input buffer */
415 if (devtype->gpio_dir_in_init)
416 devtype->gpio_dir_in_init(gc);
417
418 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
419 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
420 return 0;
421 err:
422 iounmap(mpc8xxx_gc->regs);
423 return ret;
424 }
425
mpc8xxx_remove(struct platform_device * pdev)426 static int mpc8xxx_remove(struct platform_device *pdev)
427 {
428 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
429
430 if (mpc8xxx_gc->irq) {
431 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
432 irq_domain_remove(mpc8xxx_gc->irq);
433 }
434
435 gpiochip_remove(&mpc8xxx_gc->gc);
436 iounmap(mpc8xxx_gc->regs);
437
438 return 0;
439 }
440
441 static struct platform_driver mpc8xxx_plat_driver = {
442 .probe = mpc8xxx_probe,
443 .remove = mpc8xxx_remove,
444 .driver = {
445 .name = "gpio-mpc8xxx",
446 .of_match_table = mpc8xxx_gpio_ids,
447 },
448 };
449
mpc8xxx_init(void)450 static int __init mpc8xxx_init(void)
451 {
452 return platform_driver_register(&mpc8xxx_plat_driver);
453 }
454
455 arch_initcall(mpc8xxx_init);
456