1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * I2C bus driver for the Cadence I2C controller.
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/of.h>
16 #include <linux/pm_runtime.h>
17
18 /* Register offsets for the I2C device. */
19 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
20 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
23 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
24 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
25 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
26 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
27 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
28
29 /* Control Register Bit mask definitions */
30 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
31 #define CDNS_I2C_CR_ACK_EN BIT(3)
32 #define CDNS_I2C_CR_NEA BIT(2)
33 #define CDNS_I2C_CR_MS BIT(1)
34 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
35 #define CDNS_I2C_CR_RW BIT(0)
36 /* 1 = Auto init FIFO to zeroes */
37 #define CDNS_I2C_CR_CLR_FIFO BIT(6)
38 #define CDNS_I2C_CR_DIVA_SHIFT 14
39 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
40 #define CDNS_I2C_CR_DIVB_SHIFT 8
41 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
42
43 /* Status Register Bit mask definitions */
44 #define CDNS_I2C_SR_BA BIT(8)
45 #define CDNS_I2C_SR_RXDV BIT(5)
46
47 /*
48 * I2C Address Register Bit mask definitions
49 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
50 * bits. A write access to this register always initiates a transfer if the I2C
51 * is in master mode.
52 */
53 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
54
55 /*
56 * I2C Interrupt Registers Bit mask definitions
57 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
58 * bit definitions.
59 */
60 #define CDNS_I2C_IXR_ARB_LOST BIT(9)
61 #define CDNS_I2C_IXR_RX_UNF BIT(7)
62 #define CDNS_I2C_IXR_TX_OVF BIT(6)
63 #define CDNS_I2C_IXR_RX_OVF BIT(5)
64 #define CDNS_I2C_IXR_SLV_RDY BIT(4)
65 #define CDNS_I2C_IXR_TO BIT(3)
66 #define CDNS_I2C_IXR_NACK BIT(2)
67 #define CDNS_I2C_IXR_DATA BIT(1)
68 #define CDNS_I2C_IXR_COMP BIT(0)
69
70 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
71 CDNS_I2C_IXR_RX_UNF | \
72 CDNS_I2C_IXR_TX_OVF | \
73 CDNS_I2C_IXR_RX_OVF | \
74 CDNS_I2C_IXR_SLV_RDY | \
75 CDNS_I2C_IXR_TO | \
76 CDNS_I2C_IXR_NACK | \
77 CDNS_I2C_IXR_DATA | \
78 CDNS_I2C_IXR_COMP)
79
80 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
81 CDNS_I2C_IXR_RX_UNF | \
82 CDNS_I2C_IXR_TX_OVF | \
83 CDNS_I2C_IXR_RX_OVF | \
84 CDNS_I2C_IXR_NACK)
85
86 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
87 CDNS_I2C_IXR_RX_UNF | \
88 CDNS_I2C_IXR_TX_OVF | \
89 CDNS_I2C_IXR_RX_OVF | \
90 CDNS_I2C_IXR_NACK | \
91 CDNS_I2C_IXR_DATA | \
92 CDNS_I2C_IXR_COMP)
93
94 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
95 /* timeout for pm runtime autosuspend */
96 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
97
98 #define CDNS_I2C_FIFO_DEPTH 16
99 /* FIFO depth at which the DATA interrupt occurs */
100 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
101 #define CDNS_I2C_MAX_TRANSFER_SIZE 255
102 /* Transfer size in multiples of data interrupt depth */
103 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
104
105 #define DRIVER_NAME "cdns-i2c"
106
107 #define CDNS_I2C_SPEED_MAX 400000
108 #define CDNS_I2C_SPEED_DEFAULT 100000
109
110 #define CDNS_I2C_DIVA_MAX 4
111 #define CDNS_I2C_DIVB_MAX 64
112
113 #define CDNS_I2C_TIMEOUT_MAX 0xFF
114
115 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
116
117 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
118 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
119
120 /**
121 * struct cdns_i2c - I2C device private data structure
122 *
123 * @dev: Pointer to device structure
124 * @membase: Base address of the I2C device
125 * @adap: I2C adapter instance
126 * @p_msg: Message pointer
127 * @err_status: Error status in Interrupt Status Register
128 * @xfer_done: Transfer complete status
129 * @p_send_buf: Pointer to transmit buffer
130 * @p_recv_buf: Pointer to receive buffer
131 * @send_count: Number of bytes still expected to send
132 * @recv_count: Number of bytes still expected to receive
133 * @curr_recv_count: Number of bytes to be received in current transfer
134 * @irq: IRQ number
135 * @input_clk: Input clock to I2C controller
136 * @i2c_clk: Maximum I2C clock speed
137 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
138 * @clk: Pointer to struct clk
139 * @clk_rate_change_nb: Notifier block for clock rate changes
140 * @quirks: flag for broken hold bit usage in r1p10
141 */
142 struct cdns_i2c {
143 struct device *dev;
144 void __iomem *membase;
145 struct i2c_adapter adap;
146 struct i2c_msg *p_msg;
147 int err_status;
148 struct completion xfer_done;
149 unsigned char *p_send_buf;
150 unsigned char *p_recv_buf;
151 unsigned int send_count;
152 unsigned int recv_count;
153 unsigned int curr_recv_count;
154 int irq;
155 unsigned long input_clk;
156 unsigned int i2c_clk;
157 unsigned int bus_hold_flag;
158 struct clk *clk;
159 struct notifier_block clk_rate_change_nb;
160 u32 quirks;
161 };
162
163 struct cdns_platform_data {
164 u32 quirks;
165 };
166
167 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
168 clk_rate_change_nb)
169
170 /**
171 * cdns_i2c_clear_bus_hold - Clear bus hold bit
172 * @id: Pointer to driver data struct
173 *
174 * Helper to clear the controller's bus hold bit.
175 */
cdns_i2c_clear_bus_hold(struct cdns_i2c * id)176 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
177 {
178 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
179 if (reg & CDNS_I2C_CR_HOLD)
180 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
181 }
182
cdns_is_holdquirk(struct cdns_i2c * id,bool hold_wrkaround)183 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
184 {
185 return (hold_wrkaround &&
186 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
187 }
188
189 /**
190 * cdns_i2c_isr - Interrupt handler for the I2C device
191 * @irq: irq number for the I2C device
192 * @ptr: void pointer to cdns_i2c structure
193 *
194 * This function handles the data interrupt, transfer complete interrupt and
195 * the error interrupts of the I2C device.
196 *
197 * Return: IRQ_HANDLED always
198 */
cdns_i2c_isr(int irq,void * ptr)199 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
200 {
201 unsigned int isr_status, avail_bytes;
202 unsigned int bytes_to_send;
203 bool updatetx;
204 struct cdns_i2c *id = ptr;
205 /* Signal completion only after everything is updated */
206 int done_flag = 0;
207 irqreturn_t status = IRQ_NONE;
208
209 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
210 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
211
212 /* Handling nack and arbitration lost interrupt */
213 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
214 done_flag = 1;
215 status = IRQ_HANDLED;
216 }
217
218 /*
219 * Check if transfer size register needs to be updated again for a
220 * large data receive operation.
221 */
222 updatetx = id->recv_count > id->curr_recv_count;
223
224 /* When receiving, handle data interrupt and completion interrupt */
225 if (id->p_recv_buf &&
226 ((isr_status & CDNS_I2C_IXR_COMP) ||
227 (isr_status & CDNS_I2C_IXR_DATA))) {
228 /* Read data if receive data valid is set */
229 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
230 CDNS_I2C_SR_RXDV) {
231 /*
232 * Clear hold bit that was set for FIFO control if
233 * RX data left is less than FIFO depth, unless
234 * repeated start is selected.
235 */
236 if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) &&
237 !id->bus_hold_flag)
238 cdns_i2c_clear_bus_hold(id);
239
240 *(id->p_recv_buf)++ =
241 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
242 id->recv_count--;
243 id->curr_recv_count--;
244
245 if (cdns_is_holdquirk(id, updatetx))
246 break;
247 }
248
249 /*
250 * The controller sends NACK to the slave when transfer size
251 * register reaches zero without considering the HOLD bit.
252 * This workaround is implemented for large data transfers to
253 * maintain transfer size non-zero while performing a large
254 * receive operation.
255 */
256 if (cdns_is_holdquirk(id, updatetx)) {
257 /* wait while fifo is full */
258 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
259 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
260 ;
261
262 /*
263 * Check number of bytes to be received against maximum
264 * transfer size and update register accordingly.
265 */
266 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
267 CDNS_I2C_TRANSFER_SIZE) {
268 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
269 CDNS_I2C_XFER_SIZE_OFFSET);
270 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
271 CDNS_I2C_FIFO_DEPTH;
272 } else {
273 cdns_i2c_writereg(id->recv_count -
274 CDNS_I2C_FIFO_DEPTH,
275 CDNS_I2C_XFER_SIZE_OFFSET);
276 id->curr_recv_count = id->recv_count;
277 }
278 }
279
280 /* Clear hold (if not repeated start) and signal completion */
281 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
282 if (!id->bus_hold_flag)
283 cdns_i2c_clear_bus_hold(id);
284 done_flag = 1;
285 }
286
287 status = IRQ_HANDLED;
288 }
289
290 /* When sending, handle transfer complete interrupt */
291 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
292 /*
293 * If there is more data to be sent, calculate the
294 * space available in FIFO and fill with that many bytes.
295 */
296 if (id->send_count) {
297 avail_bytes = CDNS_I2C_FIFO_DEPTH -
298 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
299 if (id->send_count > avail_bytes)
300 bytes_to_send = avail_bytes;
301 else
302 bytes_to_send = id->send_count;
303
304 while (bytes_to_send--) {
305 cdns_i2c_writereg(
306 (*(id->p_send_buf)++),
307 CDNS_I2C_DATA_OFFSET);
308 id->send_count--;
309 }
310 } else {
311 /*
312 * Signal the completion of transaction and
313 * clear the hold bus bit if there are no
314 * further messages to be processed.
315 */
316 done_flag = 1;
317 }
318 if (!id->send_count && !id->bus_hold_flag)
319 cdns_i2c_clear_bus_hold(id);
320
321 status = IRQ_HANDLED;
322 }
323
324 /* Update the status for errors */
325 id->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
326 if (id->err_status)
327 status = IRQ_HANDLED;
328
329 if (done_flag)
330 complete(&id->xfer_done);
331
332 return status;
333 }
334
335 /**
336 * cdns_i2c_mrecv - Prepare and start a master receive operation
337 * @id: pointer to the i2c device structure
338 */
cdns_i2c_mrecv(struct cdns_i2c * id)339 static void cdns_i2c_mrecv(struct cdns_i2c *id)
340 {
341 unsigned int ctrl_reg;
342 unsigned int isr_status;
343
344 id->p_recv_buf = id->p_msg->buf;
345 id->recv_count = id->p_msg->len;
346
347 /* Put the controller in master receive mode and clear the FIFO */
348 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
349 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
350
351 /*
352 * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length
353 * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if
354 * PEC is enabled, otherwise 1.
355 */
356 if (id->p_msg->flags & I2C_M_RECV_LEN)
357 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len;
358
359 id->curr_recv_count = id->recv_count;
360
361 /*
362 * Check for the message size against FIFO depth and set the
363 * 'hold bus' bit if it is greater than FIFO depth.
364 */
365 if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
366 ctrl_reg |= CDNS_I2C_CR_HOLD;
367
368 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
369
370 /* Clear the interrupts in interrupt status register */
371 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
372 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
373
374 /*
375 * The no. of bytes to receive is checked against the limit of
376 * max transfer size. Set transfer size register with no of bytes
377 * receive if it is less than transfer size and transfer size if
378 * it is more. Enable the interrupts.
379 */
380 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
381 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
382 CDNS_I2C_XFER_SIZE_OFFSET);
383 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
384 } else {
385 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
386 }
387
388 /* Set the slave address in address register - triggers operation */
389 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
390 CDNS_I2C_ADDR_OFFSET);
391 /* Clear the bus hold flag if bytes to receive is less than FIFO size */
392 if (!id->bus_hold_flag &&
393 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
394 (id->recv_count <= CDNS_I2C_FIFO_DEPTH))
395 cdns_i2c_clear_bus_hold(id);
396 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
397 }
398
399 /**
400 * cdns_i2c_msend - Prepare and start a master send operation
401 * @id: pointer to the i2c device
402 */
cdns_i2c_msend(struct cdns_i2c * id)403 static void cdns_i2c_msend(struct cdns_i2c *id)
404 {
405 unsigned int avail_bytes;
406 unsigned int bytes_to_send;
407 unsigned int ctrl_reg;
408 unsigned int isr_status;
409
410 id->p_recv_buf = NULL;
411 id->p_send_buf = id->p_msg->buf;
412 id->send_count = id->p_msg->len;
413
414 /* Set the controller in Master transmit mode and clear the FIFO. */
415 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
416 ctrl_reg &= ~CDNS_I2C_CR_RW;
417 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
418
419 /*
420 * Check for the message size against FIFO depth and set the
421 * 'hold bus' bit if it is greater than FIFO depth.
422 */
423 if (id->send_count > CDNS_I2C_FIFO_DEPTH)
424 ctrl_reg |= CDNS_I2C_CR_HOLD;
425 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
426
427 /* Clear the interrupts in interrupt status register. */
428 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
429 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
430
431 /*
432 * Calculate the space available in FIFO. Check the message length
433 * against the space available, and fill the FIFO accordingly.
434 * Enable the interrupts.
435 */
436 avail_bytes = CDNS_I2C_FIFO_DEPTH -
437 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
438
439 if (id->send_count > avail_bytes)
440 bytes_to_send = avail_bytes;
441 else
442 bytes_to_send = id->send_count;
443
444 while (bytes_to_send--) {
445 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
446 id->send_count--;
447 }
448
449 /*
450 * Clear the bus hold flag if there is no more data
451 * and if it is the last message.
452 */
453 if (!id->bus_hold_flag && !id->send_count)
454 cdns_i2c_clear_bus_hold(id);
455 /* Set the slave address in address register - triggers operation. */
456 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
457 CDNS_I2C_ADDR_OFFSET);
458
459 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
460 }
461
462 /**
463 * cdns_i2c_master_reset - Reset the interface
464 * @adap: pointer to the i2c adapter driver instance
465 *
466 * This function cleanup the fifos, clear the hold bit and status
467 * and disable the interrupts.
468 */
cdns_i2c_master_reset(struct i2c_adapter * adap)469 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
470 {
471 struct cdns_i2c *id = adap->algo_data;
472 u32 regval;
473
474 /* Disable the interrupts */
475 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
476 /* Clear the hold bit and fifos */
477 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
478 regval &= ~CDNS_I2C_CR_HOLD;
479 regval |= CDNS_I2C_CR_CLR_FIFO;
480 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
481 /* Update the transfercount register to zero */
482 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
483 /* Clear the interupt status register */
484 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
485 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
486 /* Clear the status register */
487 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
488 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
489 }
490
cdns_i2c_process_msg(struct cdns_i2c * id,struct i2c_msg * msg,struct i2c_adapter * adap)491 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
492 struct i2c_adapter *adap)
493 {
494 unsigned long time_left, msg_timeout;
495 u32 reg;
496
497 id->p_msg = msg;
498 id->err_status = 0;
499 reinit_completion(&id->xfer_done);
500
501 /* Check for the TEN Bit mode on each msg */
502 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
503 if (msg->flags & I2C_M_TEN) {
504 if (reg & CDNS_I2C_CR_NEA)
505 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
506 CDNS_I2C_CR_OFFSET);
507 } else {
508 if (!(reg & CDNS_I2C_CR_NEA))
509 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
510 CDNS_I2C_CR_OFFSET);
511 }
512
513 /* Check for the R/W flag on each msg */
514 if (msg->flags & I2C_M_RD)
515 cdns_i2c_mrecv(id);
516 else
517 cdns_i2c_msend(id);
518
519 /* Minimal time to execute this message */
520 msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk);
521 /* Plus some wiggle room */
522 msg_timeout += msecs_to_jiffies(500);
523
524 if (msg_timeout < adap->timeout)
525 msg_timeout = adap->timeout;
526
527 /* Wait for the signal of completion */
528 time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout);
529 if (time_left == 0) {
530 cdns_i2c_master_reset(adap);
531 dev_err(id->adap.dev.parent,
532 "timeout waiting on completion\n");
533 return -ETIMEDOUT;
534 }
535
536 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
537 CDNS_I2C_IDR_OFFSET);
538
539 /* If it is bus arbitration error, try again */
540 if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
541 return -EAGAIN;
542
543 if (msg->flags & I2C_M_RECV_LEN)
544 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
545
546 return 0;
547 }
548
549 /**
550 * cdns_i2c_master_xfer - The main i2c transfer function
551 * @adap: pointer to the i2c adapter driver instance
552 * @msgs: pointer to the i2c message structure
553 * @num: the number of messages to transfer
554 *
555 * Initiates the send/recv activity based on the transfer message received.
556 *
557 * Return: number of msgs processed on success, negative error otherwise
558 */
cdns_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)559 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
560 int num)
561 {
562 int ret, count;
563 u32 reg;
564 struct cdns_i2c *id = adap->algo_data;
565 bool hold_quirk;
566
567 ret = pm_runtime_get_sync(id->dev);
568 if (ret < 0)
569 return ret;
570 /* Check if the bus is free */
571 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
572 ret = -EAGAIN;
573 goto out;
574 }
575
576 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
577 /*
578 * Set the flag to one when multiple messages are to be
579 * processed with a repeated start.
580 */
581 if (num > 1) {
582 /*
583 * This controller does not give completion interrupt after a
584 * master receive message if HOLD bit is set (repeated start),
585 * resulting in SW timeout. Hence, if a receive message is
586 * followed by any other message, an error is returned
587 * indicating that this sequence is not supported.
588 */
589 for (count = 0; (count < num - 1 && hold_quirk); count++) {
590 if (msgs[count].flags & I2C_M_RD) {
591 dev_warn(adap->dev.parent,
592 "Can't do repeated start after a receive message\n");
593 ret = -EOPNOTSUPP;
594 goto out;
595 }
596 }
597 id->bus_hold_flag = 1;
598 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
599 reg |= CDNS_I2C_CR_HOLD;
600 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
601 } else {
602 id->bus_hold_flag = 0;
603 }
604
605 /* Process the msg one by one */
606 for (count = 0; count < num; count++, msgs++) {
607 if (count == (num - 1))
608 id->bus_hold_flag = 0;
609
610 ret = cdns_i2c_process_msg(id, msgs, adap);
611 if (ret)
612 goto out;
613
614 /* Report the other error interrupts to application */
615 if (id->err_status) {
616 cdns_i2c_master_reset(adap);
617
618 if (id->err_status & CDNS_I2C_IXR_NACK) {
619 ret = -ENXIO;
620 goto out;
621 }
622 ret = -EIO;
623 goto out;
624 }
625 }
626
627 ret = num;
628 out:
629 pm_runtime_mark_last_busy(id->dev);
630 pm_runtime_put_autosuspend(id->dev);
631 return ret;
632 }
633
634 /**
635 * cdns_i2c_func - Returns the supported features of the I2C driver
636 * @adap: pointer to the i2c adapter structure
637 *
638 * Return: 32 bit value, each bit corresponding to a feature
639 */
cdns_i2c_func(struct i2c_adapter * adap)640 static u32 cdns_i2c_func(struct i2c_adapter *adap)
641 {
642 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
643 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
644 I2C_FUNC_SMBUS_BLOCK_DATA;
645 }
646
647 static const struct i2c_algorithm cdns_i2c_algo = {
648 .master_xfer = cdns_i2c_master_xfer,
649 .functionality = cdns_i2c_func,
650 };
651
652 /**
653 * cdns_i2c_calc_divs - Calculate clock dividers
654 * @f: I2C clock frequency
655 * @input_clk: Input clock frequency
656 * @a: First divider (return value)
657 * @b: Second divider (return value)
658 *
659 * f is used as input and output variable. As input it is used as target I2C
660 * frequency. On function exit f holds the actually resulting I2C frequency.
661 *
662 * Return: 0 on success, negative errno otherwise.
663 */
cdns_i2c_calc_divs(unsigned long * f,unsigned long input_clk,unsigned int * a,unsigned int * b)664 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
665 unsigned int *a, unsigned int *b)
666 {
667 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
668 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
669 unsigned int last_error, current_error;
670
671 /* calculate (divisor_a+1) x (divisor_b+1) */
672 temp = input_clk / (22 * fscl);
673
674 /*
675 * If the calculated value is negative or 0, the fscl input is out of
676 * range. Return error.
677 */
678 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
679 return -EINVAL;
680
681 last_error = -1;
682 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
683 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
684
685 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
686 continue;
687 div_b--;
688
689 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
690
691 if (actual_fscl > fscl)
692 continue;
693
694 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
695 (fscl - actual_fscl));
696
697 if (last_error > current_error) {
698 calc_div_a = div_a;
699 calc_div_b = div_b;
700 best_fscl = actual_fscl;
701 last_error = current_error;
702 }
703 }
704
705 *a = calc_div_a;
706 *b = calc_div_b;
707 *f = best_fscl;
708
709 return 0;
710 }
711
712 /**
713 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
714 * @clk_in: I2C clock input frequency in Hz
715 * @id: Pointer to the I2C device structure
716 *
717 * The device must be idle rather than busy transferring data before setting
718 * these device options.
719 * The data rate is set by values in the control register.
720 * The formula for determining the correct register values is
721 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
722 * See the hardware data sheet for a full explanation of setting the serial
723 * clock rate. The clock can not be faster than the input clock divide by 22.
724 * The two most common clock rates are 100KHz and 400KHz.
725 *
726 * Return: 0 on success, negative error otherwise
727 */
cdns_i2c_setclk(unsigned long clk_in,struct cdns_i2c * id)728 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
729 {
730 unsigned int div_a, div_b;
731 unsigned int ctrl_reg;
732 int ret = 0;
733 unsigned long fscl = id->i2c_clk;
734
735 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
736 if (ret)
737 return ret;
738
739 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
740 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
741 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
742 (div_b << CDNS_I2C_CR_DIVB_SHIFT));
743 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
744
745 return 0;
746 }
747
748 /**
749 * cdns_i2c_clk_notifier_cb - Clock rate change callback
750 * @nb: Pointer to notifier block
751 * @event: Notification reason
752 * @data: Pointer to notification data object
753 *
754 * This function is called when the cdns_i2c input clock frequency changes.
755 * The callback checks whether a valid bus frequency can be generated after the
756 * change. If so, the change is acknowledged, otherwise the change is aborted.
757 * New dividers are written to the HW in the pre- or post change notification
758 * depending on the scaling direction.
759 *
760 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
761 * to acknowledge the change, NOTIFY_DONE if the notification is
762 * considered irrelevant.
763 */
cdns_i2c_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)764 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
765 event, void *data)
766 {
767 struct clk_notifier_data *ndata = data;
768 struct cdns_i2c *id = to_cdns_i2c(nb);
769
770 if (pm_runtime_suspended(id->dev))
771 return NOTIFY_OK;
772
773 switch (event) {
774 case PRE_RATE_CHANGE:
775 {
776 unsigned long input_clk = ndata->new_rate;
777 unsigned long fscl = id->i2c_clk;
778 unsigned int div_a, div_b;
779 int ret;
780
781 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
782 if (ret) {
783 dev_warn(id->adap.dev.parent,
784 "clock rate change rejected\n");
785 return NOTIFY_STOP;
786 }
787
788 /* scale up */
789 if (ndata->new_rate > ndata->old_rate)
790 cdns_i2c_setclk(ndata->new_rate, id);
791
792 return NOTIFY_OK;
793 }
794 case POST_RATE_CHANGE:
795 id->input_clk = ndata->new_rate;
796 /* scale down */
797 if (ndata->new_rate < ndata->old_rate)
798 cdns_i2c_setclk(ndata->new_rate, id);
799 return NOTIFY_OK;
800 case ABORT_RATE_CHANGE:
801 /* scale up */
802 if (ndata->new_rate > ndata->old_rate)
803 cdns_i2c_setclk(ndata->old_rate, id);
804 return NOTIFY_OK;
805 default:
806 return NOTIFY_DONE;
807 }
808 }
809
810 /**
811 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver
812 * @dev: Address of the platform_device structure
813 *
814 * Put the driver into low power mode.
815 *
816 * Return: 0 always
817 */
cdns_i2c_runtime_suspend(struct device * dev)818 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
819 {
820 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
821
822 clk_disable(xi2c->clk);
823
824 return 0;
825 }
826
827 /**
828 * cdns_i2c_runtime_resume - Runtime resume
829 * @dev: Address of the platform_device structure
830 *
831 * Runtime resume callback.
832 *
833 * Return: 0 on success and error value on error
834 */
cdns_i2c_runtime_resume(struct device * dev)835 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
836 {
837 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
838 int ret;
839
840 ret = clk_enable(xi2c->clk);
841 if (ret) {
842 dev_err(dev, "Cannot enable clock.\n");
843 return ret;
844 }
845
846 return 0;
847 }
848
849 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
850 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
851 cdns_i2c_runtime_resume, NULL)
852 };
853
854 static const struct cdns_platform_data r1p10_i2c_def = {
855 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
856 };
857
858 static const struct of_device_id cdns_i2c_of_match[] = {
859 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
860 { .compatible = "cdns,i2c-r1p14",},
861 { /* end of table */ }
862 };
863 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
864
865 /**
866 * cdns_i2c_probe - Platform registration call
867 * @pdev: Handle to the platform device structure
868 *
869 * This function does all the memory allocation and registration for the i2c
870 * device. User can modify the address mode to 10 bit address mode using the
871 * ioctl call with option I2C_TENBIT.
872 *
873 * Return: 0 on success, negative error otherwise
874 */
cdns_i2c_probe(struct platform_device * pdev)875 static int cdns_i2c_probe(struct platform_device *pdev)
876 {
877 struct resource *r_mem;
878 struct cdns_i2c *id;
879 int ret;
880 const struct of_device_id *match;
881
882 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
883 if (!id)
884 return -ENOMEM;
885
886 id->dev = &pdev->dev;
887 platform_set_drvdata(pdev, id);
888
889 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
890 if (match && match->data) {
891 const struct cdns_platform_data *data = match->data;
892 id->quirks = data->quirks;
893 }
894
895 r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
896 id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
897 if (IS_ERR(id->membase))
898 return PTR_ERR(id->membase);
899
900 ret = platform_get_irq(pdev, 0);
901 if (ret < 0)
902 return ret;
903 id->irq = ret;
904
905 id->adap.owner = THIS_MODULE;
906 id->adap.dev.of_node = pdev->dev.of_node;
907 id->adap.algo = &cdns_i2c_algo;
908 id->adap.timeout = CDNS_I2C_TIMEOUT;
909 id->adap.retries = 3; /* Default retry value. */
910 id->adap.algo_data = id;
911 id->adap.dev.parent = &pdev->dev;
912 init_completion(&id->xfer_done);
913 snprintf(id->adap.name, sizeof(id->adap.name),
914 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
915
916 id->clk = devm_clk_get(&pdev->dev, NULL);
917 if (IS_ERR(id->clk)) {
918 dev_err(&pdev->dev, "input clock not found.\n");
919 return PTR_ERR(id->clk);
920 }
921 ret = clk_prepare_enable(id->clk);
922 if (ret)
923 dev_err(&pdev->dev, "Unable to enable clock.\n");
924
925 pm_runtime_enable(id->dev);
926 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
927 pm_runtime_use_autosuspend(id->dev);
928 pm_runtime_set_active(id->dev);
929
930 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
931 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
932 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
933 id->input_clk = clk_get_rate(id->clk);
934
935 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
936 &id->i2c_clk);
937 if (ret || (id->i2c_clk > CDNS_I2C_SPEED_MAX))
938 id->i2c_clk = CDNS_I2C_SPEED_DEFAULT;
939
940 cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
941 CDNS_I2C_CR_OFFSET);
942
943 ret = cdns_i2c_setclk(id->input_clk, id);
944 if (ret) {
945 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
946 ret = -EINVAL;
947 goto err_clk_dis;
948 }
949
950 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
951 DRIVER_NAME, id);
952 if (ret) {
953 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
954 goto err_clk_dis;
955 }
956
957 /*
958 * Cadence I2C controller has a bug wherein it generates
959 * invalid read transaction after HW timeout in master receiver mode.
960 * HW timeout is not used by this driver and the interrupt is disabled.
961 * But the feature itself cannot be disabled. Hence maximum value
962 * is written to this register to reduce the chances of error.
963 */
964 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
965
966 ret = i2c_add_adapter(&id->adap);
967 if (ret < 0)
968 goto err_clk_dis;
969
970 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
971 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
972
973 return 0;
974
975 err_clk_dis:
976 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
977 clk_disable_unprepare(id->clk);
978 pm_runtime_set_suspended(&pdev->dev);
979 pm_runtime_disable(&pdev->dev);
980 return ret;
981 }
982
983 /**
984 * cdns_i2c_remove - Unregister the device after releasing the resources
985 * @pdev: Handle to the platform device structure
986 *
987 * This function frees all the resources allocated to the device.
988 *
989 * Return: 0 always
990 */
cdns_i2c_remove(struct platform_device * pdev)991 static int cdns_i2c_remove(struct platform_device *pdev)
992 {
993 struct cdns_i2c *id = platform_get_drvdata(pdev);
994
995 i2c_del_adapter(&id->adap);
996 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
997 clk_disable_unprepare(id->clk);
998 pm_runtime_disable(&pdev->dev);
999
1000 return 0;
1001 }
1002
1003 static struct platform_driver cdns_i2c_drv = {
1004 .driver = {
1005 .name = DRIVER_NAME,
1006 .of_match_table = cdns_i2c_of_match,
1007 .pm = &cdns_i2c_dev_pm_ops,
1008 },
1009 .probe = cdns_i2c_probe,
1010 .remove = cdns_i2c_remove,
1011 };
1012
1013 module_platform_driver(cdns_i2c_drv);
1014
1015 MODULE_AUTHOR("Xilinx Inc.");
1016 MODULE_DESCRIPTION("Cadence I2C bus driver");
1017 MODULE_LICENSE("GPL");
1018