1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2002 Motorola GSG-China
4 *
5 * Author:
6 * Darius Augulis, Teltonika Inc.
7 *
8 * Desc.:
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
11 *
12 * Derived from Motorola GSG China I2C example driver
13 *
14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
16 * Copyright (C) 2007 RightHand Technologies, Inc.
17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
18 *
19 * Copyright 2013 Freescale Semiconductor, Inc.
20 *
21 */
22
23 #include <linux/acpi.h>
24 #include <linux/clk.h>
25 #include <linux/completion.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dmapool.h>
30 #include <linux/err.h>
31 #include <linux/errno.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/i2c.h>
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
36 #include <linux/io.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/of_dma.h>
42 #include <linux/pinctrl/consumer.h>
43 #include <linux/platform_data/i2c-imx.h>
44 #include <linux/platform_device.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/sched.h>
47 #include <linux/slab.h>
48
49 /* This will be the driver name the kernel reports */
50 #define DRIVER_NAME "imx-i2c"
51
52 /* Default value */
53 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
54
55 /*
56 * Enable DMA if transfer byte size is bigger than this threshold.
57 * As the hardware request, it must bigger than 4 bytes.\
58 * I have set '16' here, maybe it's not the best but I think it's
59 * the appropriate.
60 */
61 #define DMA_THRESHOLD 16
62 #define DMA_TIMEOUT 1000
63
64 /* IMX I2C registers:
65 * the I2C register offset is different between SoCs,
66 * to provid support for all these chips, split the
67 * register offset into a fixed base address and a
68 * variable shift value, then the full register offset
69 * will be calculated by
70 * reg_off = ( reg_base_addr << reg_shift)
71 */
72 #define IMX_I2C_IADR 0x00 /* i2c slave address */
73 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
74 #define IMX_I2C_I2CR 0x02 /* i2c control */
75 #define IMX_I2C_I2SR 0x03 /* i2c status */
76 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
77
78 #define IMX_I2C_REGSHIFT 2
79 #define VF610_I2C_REGSHIFT 0
80
81 /* Bits of IMX I2C registers */
82 #define I2SR_RXAK 0x01
83 #define I2SR_IIF 0x02
84 #define I2SR_SRW 0x04
85 #define I2SR_IAL 0x10
86 #define I2SR_IBB 0x20
87 #define I2SR_IAAS 0x40
88 #define I2SR_ICF 0x80
89 #define I2CR_DMAEN 0x02
90 #define I2CR_RSTA 0x04
91 #define I2CR_TXAK 0x08
92 #define I2CR_MTX 0x10
93 #define I2CR_MSTA 0x20
94 #define I2CR_IIEN 0x40
95 #define I2CR_IEN 0x80
96
97 /* register bits different operating codes definition:
98 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
99 * - write zero to clear(w0c) INT flag on i.MX,
100 * - but write one to clear(w1c) INT flag on Vybrid.
101 * 2) I2CR: I2C module enable operation also differ between SoCs:
102 * - set I2CR_IEN bit enable the module on i.MX,
103 * - but clear I2CR_IEN bit enable the module on Vybrid.
104 */
105 #define I2SR_CLR_OPCODE_W0C 0x0
106 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
107 #define I2CR_IEN_OPCODE_0 0x0
108 #define I2CR_IEN_OPCODE_1 I2CR_IEN
109
110 #define I2C_PM_TIMEOUT 10 /* ms */
111
112 /*
113 * sorted list of clock divider, register value pairs
114 * taken from table 26-5, p.26-9, Freescale i.MX
115 * Integrated Portable System Processor Reference Manual
116 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
117 *
118 * Duplicated divider values removed from list
119 */
120 struct imx_i2c_clk_pair {
121 u16 div;
122 u16 val;
123 };
124
125 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
126 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
127 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
128 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
129 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
130 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
131 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
132 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
133 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
134 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
135 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
136 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
137 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
138 { 3072, 0x1E }, { 3840, 0x1F }
139 };
140
141 /* Vybrid VF610 clock divider, register value pairs */
142 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
143 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
144 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
145 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
146 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
147 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
148 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
149 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
150 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
151 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
152 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
153 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
154 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
155 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
156 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
157 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
158 };
159
160 enum imx_i2c_type {
161 IMX1_I2C,
162 IMX21_I2C,
163 VF610_I2C,
164 };
165
166 struct imx_i2c_hwdata {
167 enum imx_i2c_type devtype;
168 unsigned regshift;
169 struct imx_i2c_clk_pair *clk_div;
170 unsigned ndivs;
171 unsigned i2sr_clr_opcode;
172 unsigned i2cr_ien_opcode;
173 };
174
175 struct imx_i2c_dma {
176 struct dma_chan *chan_tx;
177 struct dma_chan *chan_rx;
178 struct dma_chan *chan_using;
179 struct completion cmd_complete;
180 dma_addr_t dma_buf;
181 unsigned int dma_len;
182 enum dma_transfer_direction dma_transfer_dir;
183 enum dma_data_direction dma_data_dir;
184 };
185
186 struct imx_i2c_struct {
187 struct i2c_adapter adapter;
188 struct clk *clk;
189 struct notifier_block clk_change_nb;
190 void __iomem *base;
191 wait_queue_head_t queue;
192 unsigned long i2csr;
193 unsigned int disable_delay;
194 int stopped;
195 unsigned int ifdr; /* IMX_I2C_IFDR */
196 unsigned int cur_clk;
197 unsigned int bitrate;
198 const struct imx_i2c_hwdata *hwdata;
199 struct i2c_bus_recovery_info rinfo;
200
201 struct pinctrl *pinctrl;
202 struct pinctrl_state *pinctrl_pins_default;
203 struct pinctrl_state *pinctrl_pins_gpio;
204
205 struct imx_i2c_dma *dma;
206 };
207
208 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
209 .devtype = IMX1_I2C,
210 .regshift = IMX_I2C_REGSHIFT,
211 .clk_div = imx_i2c_clk_div,
212 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
213 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
214 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
215
216 };
217
218 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
219 .devtype = IMX21_I2C,
220 .regshift = IMX_I2C_REGSHIFT,
221 .clk_div = imx_i2c_clk_div,
222 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
223 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
224 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
225
226 };
227
228 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
229 .devtype = VF610_I2C,
230 .regshift = VF610_I2C_REGSHIFT,
231 .clk_div = vf610_i2c_clk_div,
232 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
233 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
234 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
235
236 };
237
238 static const struct platform_device_id imx_i2c_devtype[] = {
239 {
240 .name = "imx1-i2c",
241 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
242 }, {
243 .name = "imx21-i2c",
244 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
245 }, {
246 /* sentinel */
247 }
248 };
249 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
250
251 static const struct of_device_id i2c_imx_dt_ids[] = {
252 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
253 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
254 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
255 { /* sentinel */ }
256 };
257 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
258
259 static const struct acpi_device_id i2c_imx_acpi_ids[] = {
260 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
261 { }
262 };
263 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
264
is_imx1_i2c(struct imx_i2c_struct * i2c_imx)265 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
266 {
267 return i2c_imx->hwdata->devtype == IMX1_I2C;
268 }
269
imx_i2c_write_reg(unsigned int val,struct imx_i2c_struct * i2c_imx,unsigned int reg)270 static inline void imx_i2c_write_reg(unsigned int val,
271 struct imx_i2c_struct *i2c_imx, unsigned int reg)
272 {
273 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
274 }
275
imx_i2c_read_reg(struct imx_i2c_struct * i2c_imx,unsigned int reg)276 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
277 unsigned int reg)
278 {
279 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
280 }
281
282 /* Functions for DMA support */
i2c_imx_dma_request(struct imx_i2c_struct * i2c_imx,dma_addr_t phy_addr)283 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
284 dma_addr_t phy_addr)
285 {
286 struct imx_i2c_dma *dma;
287 struct dma_slave_config dma_sconfig;
288 struct device *dev = &i2c_imx->adapter.dev;
289 int ret;
290
291 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
292 if (!dma)
293 return;
294
295 dma->chan_tx = dma_request_chan(dev, "tx");
296 if (IS_ERR(dma->chan_tx)) {
297 ret = PTR_ERR(dma->chan_tx);
298 if (ret != -ENODEV && ret != -EPROBE_DEFER)
299 dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
300 goto fail_al;
301 }
302
303 dma_sconfig.dst_addr = phy_addr +
304 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
305 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
306 dma_sconfig.dst_maxburst = 1;
307 dma_sconfig.direction = DMA_MEM_TO_DEV;
308 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
309 if (ret < 0) {
310 dev_err(dev, "can't configure tx channel (%d)\n", ret);
311 goto fail_tx;
312 }
313
314 dma->chan_rx = dma_request_chan(dev, "rx");
315 if (IS_ERR(dma->chan_rx)) {
316 ret = PTR_ERR(dma->chan_rx);
317 if (ret != -ENODEV && ret != -EPROBE_DEFER)
318 dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
319 goto fail_tx;
320 }
321
322 dma_sconfig.src_addr = phy_addr +
323 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
324 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
325 dma_sconfig.src_maxburst = 1;
326 dma_sconfig.direction = DMA_DEV_TO_MEM;
327 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
328 if (ret < 0) {
329 dev_err(dev, "can't configure rx channel (%d)\n", ret);
330 goto fail_rx;
331 }
332
333 i2c_imx->dma = dma;
334 init_completion(&dma->cmd_complete);
335 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
336 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
337
338 return;
339
340 fail_rx:
341 dma_release_channel(dma->chan_rx);
342 fail_tx:
343 dma_release_channel(dma->chan_tx);
344 fail_al:
345 devm_kfree(dev, dma);
346 }
347
i2c_imx_dma_callback(void * arg)348 static void i2c_imx_dma_callback(void *arg)
349 {
350 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
351 struct imx_i2c_dma *dma = i2c_imx->dma;
352
353 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
354 dma->dma_len, dma->dma_data_dir);
355 complete(&dma->cmd_complete);
356 }
357
i2c_imx_dma_xfer(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)358 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
359 struct i2c_msg *msgs)
360 {
361 struct imx_i2c_dma *dma = i2c_imx->dma;
362 struct dma_async_tx_descriptor *txdesc;
363 struct device *dev = &i2c_imx->adapter.dev;
364 struct device *chan_dev = dma->chan_using->device->dev;
365
366 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
367 dma->dma_len, dma->dma_data_dir);
368 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
369 dev_err(dev, "DMA mapping failed\n");
370 goto err_map;
371 }
372
373 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
374 dma->dma_len, dma->dma_transfer_dir,
375 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
376 if (!txdesc) {
377 dev_err(dev, "Not able to get desc for DMA xfer\n");
378 goto err_desc;
379 }
380
381 reinit_completion(&dma->cmd_complete);
382 txdesc->callback = i2c_imx_dma_callback;
383 txdesc->callback_param = i2c_imx;
384 if (dma_submit_error(dmaengine_submit(txdesc))) {
385 dev_err(dev, "DMA submit failed\n");
386 goto err_submit;
387 }
388
389 dma_async_issue_pending(dma->chan_using);
390 return 0;
391
392 err_submit:
393 dmaengine_terminate_all(dma->chan_using);
394 err_desc:
395 dma_unmap_single(chan_dev, dma->dma_buf,
396 dma->dma_len, dma->dma_data_dir);
397 err_map:
398 return -EINVAL;
399 }
400
i2c_imx_dma_free(struct imx_i2c_struct * i2c_imx)401 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
402 {
403 struct imx_i2c_dma *dma = i2c_imx->dma;
404
405 dma->dma_buf = 0;
406 dma->dma_len = 0;
407
408 dma_release_channel(dma->chan_tx);
409 dma->chan_tx = NULL;
410
411 dma_release_channel(dma->chan_rx);
412 dma->chan_rx = NULL;
413
414 dma->chan_using = NULL;
415 }
416
i2c_imx_clear_irq(struct imx_i2c_struct * i2c_imx,unsigned int bits)417 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
418 {
419 unsigned int temp;
420
421 /*
422 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
423 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
424 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
425 */
426 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
427 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
428 }
429
i2c_imx_bus_busy(struct imx_i2c_struct * i2c_imx,int for_busy)430 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
431 {
432 unsigned long orig_jiffies = jiffies;
433 unsigned int temp;
434
435 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
436
437 while (1) {
438 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
439
440 /* check for arbitration lost */
441 if (temp & I2SR_IAL) {
442 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
443 return -EAGAIN;
444 }
445
446 if (for_busy && (temp & I2SR_IBB)) {
447 i2c_imx->stopped = 0;
448 break;
449 }
450 if (!for_busy && !(temp & I2SR_IBB)) {
451 i2c_imx->stopped = 1;
452 break;
453 }
454 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
455 dev_dbg(&i2c_imx->adapter.dev,
456 "<%s> I2C bus is busy\n", __func__);
457 return -ETIMEDOUT;
458 }
459 schedule();
460 }
461
462 return 0;
463 }
464
i2c_imx_trx_complete(struct imx_i2c_struct * i2c_imx)465 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
466 {
467 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
468
469 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
470 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
471 return -ETIMEDOUT;
472 }
473
474 /* check for arbitration lost */
475 if (i2c_imx->i2csr & I2SR_IAL) {
476 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
477 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
478
479 i2c_imx->i2csr = 0;
480 return -EAGAIN;
481 }
482
483 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
484 i2c_imx->i2csr = 0;
485 return 0;
486 }
487
i2c_imx_acked(struct imx_i2c_struct * i2c_imx)488 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
489 {
490 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
491 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
492 return -ENXIO; /* No ACK */
493 }
494
495 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
496 return 0;
497 }
498
i2c_imx_set_clk(struct imx_i2c_struct * i2c_imx,unsigned int i2c_clk_rate)499 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
500 unsigned int i2c_clk_rate)
501 {
502 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
503 unsigned int div;
504 int i;
505
506 /* Divider value calculation */
507 if (i2c_imx->cur_clk == i2c_clk_rate)
508 return;
509
510 i2c_imx->cur_clk = i2c_clk_rate;
511
512 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
513 if (div < i2c_clk_div[0].div)
514 i = 0;
515 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
516 i = i2c_imx->hwdata->ndivs - 1;
517 else
518 for (i = 0; i2c_clk_div[i].div < div; i++)
519 ;
520
521 /* Store divider value */
522 i2c_imx->ifdr = i2c_clk_div[i].val;
523
524 /*
525 * There dummy delay is calculated.
526 * It should be about one I2C clock period long.
527 * This delay is used in I2C bus disable function
528 * to fix chip hardware bug.
529 */
530 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
531 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
532
533 #ifdef CONFIG_I2C_DEBUG_BUS
534 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
535 i2c_clk_rate, div);
536 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
537 i2c_clk_div[i].val, i2c_clk_div[i].div);
538 #endif
539 }
540
i2c_imx_clk_notifier_call(struct notifier_block * nb,unsigned long action,void * data)541 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
542 unsigned long action, void *data)
543 {
544 struct clk_notifier_data *ndata = data;
545 struct imx_i2c_struct *i2c_imx = container_of(nb,
546 struct imx_i2c_struct,
547 clk_change_nb);
548
549 if (action & POST_RATE_CHANGE)
550 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
551
552 return NOTIFY_OK;
553 }
554
i2c_imx_start(struct imx_i2c_struct * i2c_imx)555 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
556 {
557 unsigned int temp = 0;
558 int result;
559
560 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
561
562 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
563 /* Enable I2C controller */
564 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
565 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
566
567 /* Wait controller to be stable */
568 usleep_range(50, 150);
569
570 /* Start I2C transaction */
571 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
572 temp |= I2CR_MSTA;
573 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
574 result = i2c_imx_bus_busy(i2c_imx, 1);
575 if (result)
576 return result;
577
578 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
579 temp &= ~I2CR_DMAEN;
580 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
581 return result;
582 }
583
i2c_imx_stop(struct imx_i2c_struct * i2c_imx)584 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
585 {
586 unsigned int temp = 0;
587
588 if (!i2c_imx->stopped) {
589 /* Stop I2C transaction */
590 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
591 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
592 if (!(temp & I2CR_MSTA))
593 i2c_imx->stopped = 1;
594 temp &= ~(I2CR_MSTA | I2CR_MTX);
595 if (i2c_imx->dma)
596 temp &= ~I2CR_DMAEN;
597 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
598 }
599 if (is_imx1_i2c(i2c_imx)) {
600 /*
601 * This delay caused by an i.MXL hardware bug.
602 * If no (or too short) delay, no "STOP" bit will be generated.
603 */
604 udelay(i2c_imx->disable_delay);
605 }
606
607 if (!i2c_imx->stopped)
608 i2c_imx_bus_busy(i2c_imx, 0);
609
610 /* Disable I2C controller */
611 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
612 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
613 }
614
i2c_imx_isr(int irq,void * dev_id)615 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
616 {
617 struct imx_i2c_struct *i2c_imx = dev_id;
618 unsigned int temp;
619
620 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
621 if (temp & I2SR_IIF) {
622 /* save status register */
623 i2c_imx->i2csr = temp;
624 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
625 wake_up(&i2c_imx->queue);
626 return IRQ_HANDLED;
627 }
628
629 return IRQ_NONE;
630 }
631
i2c_imx_dma_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)632 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
633 struct i2c_msg *msgs)
634 {
635 int result;
636 unsigned long time_left;
637 unsigned int temp = 0;
638 unsigned long orig_jiffies = jiffies;
639 struct imx_i2c_dma *dma = i2c_imx->dma;
640 struct device *dev = &i2c_imx->adapter.dev;
641
642 dma->chan_using = dma->chan_tx;
643 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
644 dma->dma_data_dir = DMA_TO_DEVICE;
645 dma->dma_len = msgs->len - 1;
646 result = i2c_imx_dma_xfer(i2c_imx, msgs);
647 if (result)
648 return result;
649
650 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
651 temp |= I2CR_DMAEN;
652 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
653
654 /*
655 * Write slave address.
656 * The first byte must be transmitted by the CPU.
657 */
658 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
659 time_left = wait_for_completion_timeout(
660 &i2c_imx->dma->cmd_complete,
661 msecs_to_jiffies(DMA_TIMEOUT));
662 if (time_left == 0) {
663 dmaengine_terminate_all(dma->chan_using);
664 return -ETIMEDOUT;
665 }
666
667 /* Waiting for transfer complete. */
668 while (1) {
669 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
670 if (temp & I2SR_ICF)
671 break;
672 if (time_after(jiffies, orig_jiffies +
673 msecs_to_jiffies(DMA_TIMEOUT))) {
674 dev_dbg(dev, "<%s> Timeout\n", __func__);
675 return -ETIMEDOUT;
676 }
677 schedule();
678 }
679
680 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
681 temp &= ~I2CR_DMAEN;
682 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
683
684 /* The last data byte must be transferred by the CPU. */
685 imx_i2c_write_reg(msgs->buf[msgs->len-1],
686 i2c_imx, IMX_I2C_I2DR);
687 result = i2c_imx_trx_complete(i2c_imx);
688 if (result)
689 return result;
690
691 return i2c_imx_acked(i2c_imx);
692 }
693
i2c_imx_dma_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg)694 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
695 struct i2c_msg *msgs, bool is_lastmsg)
696 {
697 int result;
698 unsigned long time_left;
699 unsigned int temp;
700 unsigned long orig_jiffies = jiffies;
701 struct imx_i2c_dma *dma = i2c_imx->dma;
702 struct device *dev = &i2c_imx->adapter.dev;
703
704
705 dma->chan_using = dma->chan_rx;
706 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
707 dma->dma_data_dir = DMA_FROM_DEVICE;
708 /* The last two data bytes must be transferred by the CPU. */
709 dma->dma_len = msgs->len - 2;
710 result = i2c_imx_dma_xfer(i2c_imx, msgs);
711 if (result)
712 return result;
713
714 time_left = wait_for_completion_timeout(
715 &i2c_imx->dma->cmd_complete,
716 msecs_to_jiffies(DMA_TIMEOUT));
717 if (time_left == 0) {
718 dmaengine_terminate_all(dma->chan_using);
719 return -ETIMEDOUT;
720 }
721
722 /* waiting for transfer complete. */
723 while (1) {
724 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
725 if (temp & I2SR_ICF)
726 break;
727 if (time_after(jiffies, orig_jiffies +
728 msecs_to_jiffies(DMA_TIMEOUT))) {
729 dev_dbg(dev, "<%s> Timeout\n", __func__);
730 return -ETIMEDOUT;
731 }
732 schedule();
733 }
734
735 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
736 temp &= ~I2CR_DMAEN;
737 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
738
739 /* read n-1 byte data */
740 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
741 temp |= I2CR_TXAK;
742 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
743
744 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
745 /* read n byte data */
746 result = i2c_imx_trx_complete(i2c_imx);
747 if (result)
748 return result;
749
750 if (is_lastmsg) {
751 /*
752 * It must generate STOP before read I2DR to prevent
753 * controller from generating another clock cycle
754 */
755 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
756 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
757 if (!(temp & I2CR_MSTA))
758 i2c_imx->stopped = 1;
759 temp &= ~(I2CR_MSTA | I2CR_MTX);
760 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
761 if (!i2c_imx->stopped)
762 i2c_imx_bus_busy(i2c_imx, 0);
763 } else {
764 /*
765 * For i2c master receiver repeat restart operation like:
766 * read -> repeat MSTA -> read/write
767 * The controller must set MTX before read the last byte in
768 * the first read operation, otherwise the first read cost
769 * one extra clock cycle.
770 */
771 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
772 temp |= I2CR_MTX;
773 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
774 }
775 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
776
777 return 0;
778 }
779
i2c_imx_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)780 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
781 {
782 int i, result;
783
784 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
785 __func__, i2c_8bit_addr_from_msg(msgs));
786
787 /* write slave address */
788 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
789 result = i2c_imx_trx_complete(i2c_imx);
790 if (result)
791 return result;
792 result = i2c_imx_acked(i2c_imx);
793 if (result)
794 return result;
795 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
796
797 /* write data */
798 for (i = 0; i < msgs->len; i++) {
799 dev_dbg(&i2c_imx->adapter.dev,
800 "<%s> write byte: B%d=0x%X\n",
801 __func__, i, msgs->buf[i]);
802 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
803 result = i2c_imx_trx_complete(i2c_imx);
804 if (result)
805 return result;
806 result = i2c_imx_acked(i2c_imx);
807 if (result)
808 return result;
809 }
810 return 0;
811 }
812
i2c_imx_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg)813 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
814 {
815 int i, result;
816 unsigned int temp;
817 int block_data = msgs->flags & I2C_M_RECV_LEN;
818 int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
819
820 dev_dbg(&i2c_imx->adapter.dev,
821 "<%s> write slave address: addr=0x%x\n",
822 __func__, i2c_8bit_addr_from_msg(msgs));
823
824 /* write slave address */
825 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
826 result = i2c_imx_trx_complete(i2c_imx);
827 if (result)
828 return result;
829 result = i2c_imx_acked(i2c_imx);
830 if (result)
831 return result;
832
833 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
834
835 /* setup bus to read data */
836 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
837 temp &= ~I2CR_MTX;
838
839 /*
840 * Reset the I2CR_TXAK flag initially for SMBus block read since the
841 * length is unknown
842 */
843 if ((msgs->len - 1) || block_data)
844 temp &= ~I2CR_TXAK;
845 if (use_dma)
846 temp |= I2CR_DMAEN;
847 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
848 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
849
850 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
851
852 if (use_dma)
853 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
854
855 /* read data */
856 for (i = 0; i < msgs->len; i++) {
857 u8 len = 0;
858
859 result = i2c_imx_trx_complete(i2c_imx);
860 if (result)
861 return result;
862 /*
863 * First byte is the length of remaining packet
864 * in the SMBus block data read. Add it to
865 * msgs->len.
866 */
867 if ((!i) && block_data) {
868 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
869 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
870 return -EPROTO;
871 dev_dbg(&i2c_imx->adapter.dev,
872 "<%s> read length: 0x%X\n",
873 __func__, len);
874 msgs->len += len;
875 }
876 if (i == (msgs->len - 1)) {
877 if (is_lastmsg) {
878 /*
879 * It must generate STOP before read I2DR to prevent
880 * controller from generating another clock cycle
881 */
882 dev_dbg(&i2c_imx->adapter.dev,
883 "<%s> clear MSTA\n", __func__);
884 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
885 if (!(temp & I2CR_MSTA))
886 i2c_imx->stopped = 1;
887 temp &= ~(I2CR_MSTA | I2CR_MTX);
888 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
889 if (!i2c_imx->stopped)
890 i2c_imx_bus_busy(i2c_imx, 0);
891 } else {
892 /*
893 * For i2c master receiver repeat restart operation like:
894 * read -> repeat MSTA -> read/write
895 * The controller must set MTX before read the last byte in
896 * the first read operation, otherwise the first read cost
897 * one extra clock cycle.
898 */
899 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
900 temp |= I2CR_MTX;
901 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
902 }
903 } else if (i == (msgs->len - 2)) {
904 dev_dbg(&i2c_imx->adapter.dev,
905 "<%s> set TXAK\n", __func__);
906 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
907 temp |= I2CR_TXAK;
908 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
909 }
910 if ((!i) && block_data)
911 msgs->buf[0] = len;
912 else
913 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
914 dev_dbg(&i2c_imx->adapter.dev,
915 "<%s> read byte: B%d=0x%X\n",
916 __func__, i, msgs->buf[i]);
917 }
918 return 0;
919 }
920
i2c_imx_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)921 static int i2c_imx_xfer(struct i2c_adapter *adapter,
922 struct i2c_msg *msgs, int num)
923 {
924 unsigned int i, temp;
925 int result;
926 bool is_lastmsg = false;
927 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
928
929 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
930
931 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
932 if (result < 0)
933 goto out;
934
935 /* Start I2C transfer */
936 result = i2c_imx_start(i2c_imx);
937 if (result) {
938 if (i2c_imx->adapter.bus_recovery_info) {
939 i2c_recover_bus(&i2c_imx->adapter);
940 result = i2c_imx_start(i2c_imx);
941 }
942 }
943
944 if (result)
945 goto fail0;
946
947 /* read/write data */
948 for (i = 0; i < num; i++) {
949 if (i == num - 1)
950 is_lastmsg = true;
951
952 if (i) {
953 dev_dbg(&i2c_imx->adapter.dev,
954 "<%s> repeated start\n", __func__);
955 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
956 temp |= I2CR_RSTA;
957 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
958 result = i2c_imx_bus_busy(i2c_imx, 1);
959 if (result)
960 goto fail0;
961 }
962 dev_dbg(&i2c_imx->adapter.dev,
963 "<%s> transfer message: %d\n", __func__, i);
964 /* write/read data */
965 #ifdef CONFIG_I2C_DEBUG_BUS
966 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
967 dev_dbg(&i2c_imx->adapter.dev,
968 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
969 __func__,
970 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
971 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
972 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
973 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
974 dev_dbg(&i2c_imx->adapter.dev,
975 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
976 __func__,
977 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
978 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
979 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
980 (temp & I2SR_RXAK ? 1 : 0));
981 #endif
982 if (msgs[i].flags & I2C_M_RD)
983 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
984 else {
985 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
986 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
987 else
988 result = i2c_imx_write(i2c_imx, &msgs[i]);
989 }
990 if (result)
991 goto fail0;
992 }
993
994 fail0:
995 /* Stop I2C transfer */
996 i2c_imx_stop(i2c_imx);
997
998 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
999 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1000
1001 out:
1002 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1003 (result < 0) ? "error" : "success msg",
1004 (result < 0) ? result : num);
1005 return (result < 0) ? result : num;
1006 }
1007
i2c_imx_prepare_recovery(struct i2c_adapter * adap)1008 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1009 {
1010 struct imx_i2c_struct *i2c_imx;
1011
1012 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1013
1014 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1015 }
1016
i2c_imx_unprepare_recovery(struct i2c_adapter * adap)1017 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1018 {
1019 struct imx_i2c_struct *i2c_imx;
1020
1021 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1022
1023 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1024 }
1025
1026 /*
1027 * We switch SCL and SDA to their GPIO function and do some bitbanging
1028 * for bus recovery. These alternative pinmux settings can be
1029 * described in the device tree by a separate pinctrl state "gpio". If
1030 * this is missing this is not a big problem, the only implication is
1031 * that we can't do bus recovery.
1032 */
i2c_imx_init_recovery_info(struct imx_i2c_struct * i2c_imx,struct platform_device * pdev)1033 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1034 struct platform_device *pdev)
1035 {
1036 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1037
1038 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1039 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1040 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1041 return PTR_ERR(i2c_imx->pinctrl);
1042 }
1043
1044 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1045 PINCTRL_STATE_DEFAULT);
1046 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1047 "gpio");
1048 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1049 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1050
1051 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1052 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1053 return -EPROBE_DEFER;
1054 } else if (IS_ERR(rinfo->sda_gpiod) ||
1055 IS_ERR(rinfo->scl_gpiod) ||
1056 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1057 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1058 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1059 return 0;
1060 }
1061
1062 dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1063 rinfo->sda_gpiod ? ",sda" : "");
1064
1065 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1066 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1067 rinfo->recover_bus = i2c_generic_scl_recovery;
1068 i2c_imx->adapter.bus_recovery_info = rinfo;
1069
1070 return 0;
1071 }
1072
i2c_imx_func(struct i2c_adapter * adapter)1073 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1074 {
1075 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1076 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1077 }
1078
1079 static const struct i2c_algorithm i2c_imx_algo = {
1080 .master_xfer = i2c_imx_xfer,
1081 .functionality = i2c_imx_func,
1082 };
1083
i2c_imx_probe(struct platform_device * pdev)1084 static int i2c_imx_probe(struct platform_device *pdev)
1085 {
1086 struct imx_i2c_struct *i2c_imx;
1087 struct resource *res;
1088 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1089 void __iomem *base;
1090 int irq, ret;
1091 dma_addr_t phy_addr;
1092 const struct imx_i2c_hwdata *match;
1093
1094 dev_dbg(&pdev->dev, "<%s>\n", __func__);
1095
1096 irq = platform_get_irq(pdev, 0);
1097 if (irq < 0) {
1098 dev_err(&pdev->dev, "can't get irq number\n");
1099 return irq;
1100 }
1101
1102 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1103 base = devm_ioremap_resource(&pdev->dev, res);
1104 if (IS_ERR(base))
1105 return PTR_ERR(base);
1106
1107 phy_addr = (dma_addr_t)res->start;
1108 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1109 if (!i2c_imx)
1110 return -ENOMEM;
1111
1112 match = device_get_match_data(&pdev->dev);
1113 if (match)
1114 i2c_imx->hwdata = match;
1115 else
1116 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1117 platform_get_device_id(pdev)->driver_data;
1118
1119 /* Setup i2c_imx driver structure */
1120 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1121 i2c_imx->adapter.owner = THIS_MODULE;
1122 i2c_imx->adapter.algo = &i2c_imx_algo;
1123 i2c_imx->adapter.dev.parent = &pdev->dev;
1124 i2c_imx->adapter.nr = pdev->id;
1125 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1126 i2c_imx->base = base;
1127 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1128
1129 /* Get I2C clock */
1130 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1131 if (IS_ERR(i2c_imx->clk)) {
1132 if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1133 dev_err(&pdev->dev, "can't get I2C clock\n");
1134 return PTR_ERR(i2c_imx->clk);
1135 }
1136
1137 ret = clk_prepare_enable(i2c_imx->clk);
1138 if (ret) {
1139 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1140 return ret;
1141 }
1142
1143 /* Init queue */
1144 init_waitqueue_head(&i2c_imx->queue);
1145
1146 /* Set up adapter data */
1147 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1148
1149 /* Set up platform driver data */
1150 platform_set_drvdata(pdev, i2c_imx);
1151
1152 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1153 pm_runtime_use_autosuspend(&pdev->dev);
1154 pm_runtime_set_active(&pdev->dev);
1155 pm_runtime_enable(&pdev->dev);
1156
1157 ret = pm_runtime_get_sync(&pdev->dev);
1158 if (ret < 0)
1159 goto rpm_disable;
1160
1161 /* Request IRQ */
1162 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED,
1163 pdev->name, i2c_imx);
1164 if (ret) {
1165 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1166 goto rpm_disable;
1167 }
1168
1169 /* Set up clock divider */
1170 i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1171 ret = of_property_read_u32(pdev->dev.of_node,
1172 "clock-frequency", &i2c_imx->bitrate);
1173 if (ret < 0 && pdata && pdata->bitrate)
1174 i2c_imx->bitrate = pdata->bitrate;
1175 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1176 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1177 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1178
1179 /* Set up chip registers to defaults */
1180 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1181 i2c_imx, IMX_I2C_I2CR);
1182 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1183
1184 /* Init optional bus recovery function */
1185 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1186 /* Give it another chance if pinctrl used is not ready yet */
1187 if (ret == -EPROBE_DEFER)
1188 goto clk_notifier_unregister;
1189
1190 /* Add I2C adapter */
1191 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1192 if (ret < 0)
1193 goto clk_notifier_unregister;
1194
1195 pm_runtime_mark_last_busy(&pdev->dev);
1196 pm_runtime_put_autosuspend(&pdev->dev);
1197
1198 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1199 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1200 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1201 i2c_imx->adapter.name);
1202 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1203
1204 /* Init DMA config if supported */
1205 i2c_imx_dma_request(i2c_imx, phy_addr);
1206
1207 return 0; /* Return OK */
1208
1209 clk_notifier_unregister:
1210 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1211 free_irq(irq, i2c_imx);
1212 rpm_disable:
1213 pm_runtime_put_noidle(&pdev->dev);
1214 pm_runtime_disable(&pdev->dev);
1215 pm_runtime_set_suspended(&pdev->dev);
1216 pm_runtime_dont_use_autosuspend(&pdev->dev);
1217 clk_disable_unprepare(i2c_imx->clk);
1218 return ret;
1219 }
1220
i2c_imx_remove(struct platform_device * pdev)1221 static int i2c_imx_remove(struct platform_device *pdev)
1222 {
1223 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1224 int irq, ret;
1225
1226 ret = pm_runtime_get_sync(&pdev->dev);
1227 if (ret < 0)
1228 return ret;
1229
1230 /* remove adapter */
1231 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1232 i2c_del_adapter(&i2c_imx->adapter);
1233
1234 if (i2c_imx->dma)
1235 i2c_imx_dma_free(i2c_imx);
1236
1237 /* setup chip registers to defaults */
1238 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1239 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1240 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1241 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1242
1243 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1244 irq = platform_get_irq(pdev, 0);
1245 if (irq >= 0)
1246 free_irq(irq, i2c_imx);
1247 clk_disable_unprepare(i2c_imx->clk);
1248
1249 pm_runtime_put_noidle(&pdev->dev);
1250 pm_runtime_disable(&pdev->dev);
1251
1252 return 0;
1253 }
1254
i2c_imx_runtime_suspend(struct device * dev)1255 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1256 {
1257 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1258
1259 clk_disable(i2c_imx->clk);
1260
1261 return 0;
1262 }
1263
i2c_imx_runtime_resume(struct device * dev)1264 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1265 {
1266 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1267 int ret;
1268
1269 ret = clk_enable(i2c_imx->clk);
1270 if (ret)
1271 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1272
1273 return ret;
1274 }
1275
1276 static const struct dev_pm_ops i2c_imx_pm_ops = {
1277 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1278 i2c_imx_runtime_resume, NULL)
1279 };
1280
1281 static struct platform_driver i2c_imx_driver = {
1282 .probe = i2c_imx_probe,
1283 .remove = i2c_imx_remove,
1284 .driver = {
1285 .name = DRIVER_NAME,
1286 .pm = &i2c_imx_pm_ops,
1287 .of_match_table = i2c_imx_dt_ids,
1288 .acpi_match_table = i2c_imx_acpi_ids,
1289 },
1290 .id_table = imx_i2c_devtype,
1291 };
1292
i2c_adap_imx_init(void)1293 static int __init i2c_adap_imx_init(void)
1294 {
1295 return platform_driver_register(&i2c_imx_driver);
1296 }
1297 subsys_initcall(i2c_adap_imx_init);
1298
i2c_adap_imx_exit(void)1299 static void __exit i2c_adap_imx_exit(void)
1300 {
1301 platform_driver_unregister(&i2c_imx_driver);
1302 }
1303 module_exit(i2c_adap_imx_exit);
1304
1305 MODULE_LICENSE("GPL");
1306 MODULE_AUTHOR("Darius Augulis");
1307 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1308 MODULE_ALIAS("platform:" DRIVER_NAME);
1309