1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * I2C bus driver for Amlogic Meson SoCs
4 *
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/types.h>
20
21 /* Meson I2C register map */
22 #define REG_CTRL 0x00
23 #define REG_SLAVE_ADDR 0x04
24 #define REG_TOK_LIST0 0x08
25 #define REG_TOK_LIST1 0x0c
26 #define REG_TOK_WDATA0 0x10
27 #define REG_TOK_WDATA1 0x14
28 #define REG_TOK_RDATA0 0x18
29 #define REG_TOK_RDATA1 0x1c
30
31 /* Control register fields */
32 #define REG_CTRL_START BIT(0)
33 #define REG_CTRL_ACK_IGNORE BIT(1)
34 #define REG_CTRL_STATUS BIT(2)
35 #define REG_CTRL_ERROR BIT(3)
36 #define REG_CTRL_CLKDIV GENMASK(21, 12)
37 #define REG_CTRL_CLKDIVEXT GENMASK(29, 28)
38
39 #define REG_SLV_ADDR GENMASK(7, 0)
40 #define REG_SLV_SDA_FILTER GENMASK(10, 8)
41 #define REG_SLV_SCL_FILTER GENMASK(13, 11)
42 #define REG_SLV_SCL_LOW GENMASK(27, 16)
43 #define REG_SLV_SCL_LOW_EN BIT(28)
44
45 #define I2C_TIMEOUT_MS 500
46 #define FILTER_DELAY 15
47
48 enum {
49 TOKEN_END = 0,
50 TOKEN_START,
51 TOKEN_SLAVE_ADDR_WRITE,
52 TOKEN_SLAVE_ADDR_READ,
53 TOKEN_DATA,
54 TOKEN_DATA_LAST,
55 TOKEN_STOP,
56 };
57
58 enum {
59 STATE_IDLE,
60 STATE_READ,
61 STATE_WRITE,
62 };
63
64 struct meson_i2c_data {
65 unsigned char div_factor;
66 };
67
68 /**
69 * struct meson_i2c - Meson I2C device private data
70 *
71 * @adap: I2C adapter instance
72 * @dev: Pointer to device structure
73 * @regs: Base address of the device memory mapped registers
74 * @clk: Pointer to clock structure
75 * @msg: Pointer to the current I2C message
76 * @state: Current state in the driver state machine
77 * @last: Flag set for the last message in the transfer
78 * @count: Number of bytes to be sent/received in current transfer
79 * @pos: Current position in the send/receive buffer
80 * @error: Flag set when an error is received
81 * @lock: To avoid race conditions between irq handler and xfer code
82 * @done: Completion used to wait for transfer termination
83 * @tokens: Sequence of tokens to be written to the device
84 * @num_tokens: Number of tokens
85 * @data: Pointer to the controlller's platform data
86 */
87 struct meson_i2c {
88 struct i2c_adapter adap;
89 struct device *dev;
90 void __iomem *regs;
91 struct clk *clk;
92
93 struct i2c_msg *msg;
94 int state;
95 bool last;
96 int count;
97 int pos;
98 int error;
99
100 spinlock_t lock;
101 struct completion done;
102 u32 tokens[2];
103 int num_tokens;
104
105 const struct meson_i2c_data *data;
106 };
107
meson_i2c_set_mask(struct meson_i2c * i2c,int reg,u32 mask,u32 val)108 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
109 u32 val)
110 {
111 u32 data;
112
113 data = readl(i2c->regs + reg);
114 data &= ~mask;
115 data |= val & mask;
116 writel(data, i2c->regs + reg);
117 }
118
meson_i2c_reset_tokens(struct meson_i2c * i2c)119 static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
120 {
121 i2c->tokens[0] = 0;
122 i2c->tokens[1] = 0;
123 i2c->num_tokens = 0;
124 }
125
meson_i2c_add_token(struct meson_i2c * i2c,int token)126 static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
127 {
128 if (i2c->num_tokens < 8)
129 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
130 else
131 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
132
133 i2c->num_tokens++;
134 }
135
meson_i2c_set_clk_div(struct meson_i2c * i2c,unsigned int freq)136 static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
137 {
138 unsigned long clk_rate = clk_get_rate(i2c->clk);
139 unsigned int div;
140
141 div = DIV_ROUND_UP(clk_rate, freq);
142 div -= FILTER_DELAY;
143 div = DIV_ROUND_UP(div, i2c->data->div_factor);
144
145 /* clock divider has 12 bits */
146 if (div > GENMASK(11, 0)) {
147 dev_err(i2c->dev, "requested bus frequency too low\n");
148 div = GENMASK(11, 0);
149 }
150
151 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV,
152 FIELD_PREP(REG_CTRL_CLKDIV, div & GENMASK(9, 0)));
153
154 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT,
155 FIELD_PREP(REG_CTRL_CLKDIVEXT, div >> 10));
156
157 /* Disable HIGH/LOW mode */
158 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, 0);
159
160 dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
161 clk_rate, freq, div);
162 }
163
meson_i2c_get_data(struct meson_i2c * i2c,char * buf,int len)164 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
165 {
166 u32 rdata0, rdata1;
167 int i;
168
169 rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
170 rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
171
172 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
173 rdata0, rdata1, len);
174
175 for (i = 0; i < min(4, len); i++)
176 *buf++ = (rdata0 >> i * 8) & 0xff;
177
178 for (i = 4; i < min(8, len); i++)
179 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
180 }
181
meson_i2c_put_data(struct meson_i2c * i2c,char * buf,int len)182 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
183 {
184 u32 wdata0 = 0, wdata1 = 0;
185 int i;
186
187 for (i = 0; i < min(4, len); i++)
188 wdata0 |= *buf++ << (i * 8);
189
190 for (i = 4; i < min(8, len); i++)
191 wdata1 |= *buf++ << ((i - 4) * 8);
192
193 writel(wdata0, i2c->regs + REG_TOK_WDATA0);
194 writel(wdata1, i2c->regs + REG_TOK_WDATA1);
195
196 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
197 wdata0, wdata1, len);
198 }
199
meson_i2c_prepare_xfer(struct meson_i2c * i2c)200 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
201 {
202 bool write = !(i2c->msg->flags & I2C_M_RD);
203 int i;
204
205 i2c->count = min(i2c->msg->len - i2c->pos, 8);
206
207 for (i = 0; i < i2c->count - 1; i++)
208 meson_i2c_add_token(i2c, TOKEN_DATA);
209
210 if (i2c->count) {
211 if (write || i2c->pos + i2c->count < i2c->msg->len)
212 meson_i2c_add_token(i2c, TOKEN_DATA);
213 else
214 meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
215 }
216
217 if (write)
218 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
219
220 if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
221 meson_i2c_add_token(i2c, TOKEN_STOP);
222
223 writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
224 writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
225 }
226
meson_i2c_irq(int irqno,void * dev_id)227 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
228 {
229 struct meson_i2c *i2c = dev_id;
230 unsigned int ctrl;
231
232 spin_lock(&i2c->lock);
233
234 meson_i2c_reset_tokens(i2c);
235 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
236 ctrl = readl(i2c->regs + REG_CTRL);
237
238 dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
239 i2c->state, i2c->pos, i2c->count, ctrl);
240
241 if (i2c->state == STATE_IDLE) {
242 spin_unlock(&i2c->lock);
243 return IRQ_NONE;
244 }
245
246 if (ctrl & REG_CTRL_ERROR) {
247 /*
248 * The bit is set when the IGNORE_NAK bit is cleared
249 * and the device didn't respond. In this case, the
250 * I2C controller automatically generates a STOP
251 * condition.
252 */
253 dev_dbg(i2c->dev, "error bit set\n");
254 i2c->error = -ENXIO;
255 i2c->state = STATE_IDLE;
256 complete(&i2c->done);
257 goto out;
258 }
259
260 if (i2c->state == STATE_READ && i2c->count)
261 meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
262
263 i2c->pos += i2c->count;
264
265 if (i2c->pos >= i2c->msg->len) {
266 i2c->state = STATE_IDLE;
267 complete(&i2c->done);
268 goto out;
269 }
270
271 /* Restart the processing */
272 meson_i2c_prepare_xfer(i2c);
273 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
274 out:
275 spin_unlock(&i2c->lock);
276
277 return IRQ_HANDLED;
278 }
279
meson_i2c_do_start(struct meson_i2c * i2c,struct i2c_msg * msg)280 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
281 {
282 int token;
283
284 token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
285 TOKEN_SLAVE_ADDR_WRITE;
286
287
288 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_ADDR,
289 FIELD_PREP(REG_SLV_ADDR, msg->addr << 1));
290
291 meson_i2c_add_token(i2c, TOKEN_START);
292 meson_i2c_add_token(i2c, token);
293 }
294
meson_i2c_xfer_msg(struct meson_i2c * i2c,struct i2c_msg * msg,int last)295 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
296 int last)
297 {
298 unsigned long time_left, flags;
299 int ret = 0;
300
301 i2c->msg = msg;
302 i2c->last = last;
303 i2c->pos = 0;
304 i2c->count = 0;
305 i2c->error = 0;
306
307 meson_i2c_reset_tokens(i2c);
308
309 flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
310 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
311
312 if (!(msg->flags & I2C_M_NOSTART))
313 meson_i2c_do_start(i2c, msg);
314
315 i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
316 meson_i2c_prepare_xfer(i2c);
317 reinit_completion(&i2c->done);
318
319 /* Start the transfer */
320 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
321
322 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
323 time_left = wait_for_completion_timeout(&i2c->done, time_left);
324
325 /*
326 * Protect access to i2c struct and registers from interrupt
327 * handlers triggered by a transfer terminated after the
328 * timeout period
329 */
330 spin_lock_irqsave(&i2c->lock, flags);
331
332 /* Abort any active operation */
333 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
334
335 if (!time_left) {
336 i2c->state = STATE_IDLE;
337 ret = -ETIMEDOUT;
338 }
339
340 if (i2c->error)
341 ret = i2c->error;
342
343 spin_unlock_irqrestore(&i2c->lock, flags);
344
345 return ret;
346 }
347
meson_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)348 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
349 int num)
350 {
351 struct meson_i2c *i2c = adap->algo_data;
352 int i, ret = 0;
353
354 clk_enable(i2c->clk);
355
356 for (i = 0; i < num; i++) {
357 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
358 if (ret)
359 break;
360 }
361
362 clk_disable(i2c->clk);
363
364 return ret ?: i;
365 }
366
meson_i2c_func(struct i2c_adapter * adap)367 static u32 meson_i2c_func(struct i2c_adapter *adap)
368 {
369 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
370 }
371
372 static const struct i2c_algorithm meson_i2c_algorithm = {
373 .master_xfer = meson_i2c_xfer,
374 .functionality = meson_i2c_func,
375 };
376
meson_i2c_probe(struct platform_device * pdev)377 static int meson_i2c_probe(struct platform_device *pdev)
378 {
379 struct device_node *np = pdev->dev.of_node;
380 struct meson_i2c *i2c;
381 struct resource *mem;
382 struct i2c_timings timings;
383 int irq, ret = 0;
384
385 i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
386 if (!i2c)
387 return -ENOMEM;
388
389 i2c_parse_fw_timings(&pdev->dev, &timings, true);
390
391 i2c->dev = &pdev->dev;
392 platform_set_drvdata(pdev, i2c);
393
394 spin_lock_init(&i2c->lock);
395 init_completion(&i2c->done);
396
397 i2c->data = (const struct meson_i2c_data *)
398 of_device_get_match_data(&pdev->dev);
399
400 i2c->clk = devm_clk_get(&pdev->dev, NULL);
401 if (IS_ERR(i2c->clk)) {
402 dev_err(&pdev->dev, "can't get device clock\n");
403 return PTR_ERR(i2c->clk);
404 }
405
406 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
408 if (IS_ERR(i2c->regs))
409 return PTR_ERR(i2c->regs);
410
411 irq = platform_get_irq(pdev, 0);
412 if (irq < 0) {
413 dev_err(&pdev->dev, "can't find IRQ\n");
414 return irq;
415 }
416
417 ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
418 if (ret < 0) {
419 dev_err(&pdev->dev, "can't request IRQ\n");
420 return ret;
421 }
422
423 ret = clk_prepare(i2c->clk);
424 if (ret < 0) {
425 dev_err(&pdev->dev, "can't prepare clock\n");
426 return ret;
427 }
428
429 strlcpy(i2c->adap.name, "Meson I2C adapter",
430 sizeof(i2c->adap.name));
431 i2c->adap.owner = THIS_MODULE;
432 i2c->adap.algo = &meson_i2c_algorithm;
433 i2c->adap.dev.parent = &pdev->dev;
434 i2c->adap.dev.of_node = np;
435 i2c->adap.algo_data = i2c;
436
437 /*
438 * A transfer is triggered when START bit changes from 0 to 1.
439 * Ensure that the bit is set to 0 after probe
440 */
441 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
442
443 ret = i2c_add_adapter(&i2c->adap);
444 if (ret < 0) {
445 clk_unprepare(i2c->clk);
446 return ret;
447 }
448
449 /* Disable filtering */
450 meson_i2c_set_mask(i2c, REG_SLAVE_ADDR,
451 REG_SLV_SDA_FILTER | REG_SLV_SCL_FILTER, 0);
452
453 meson_i2c_set_clk_div(i2c, timings.bus_freq_hz);
454
455 return 0;
456 }
457
meson_i2c_remove(struct platform_device * pdev)458 static int meson_i2c_remove(struct platform_device *pdev)
459 {
460 struct meson_i2c *i2c = platform_get_drvdata(pdev);
461
462 i2c_del_adapter(&i2c->adap);
463 clk_unprepare(i2c->clk);
464
465 return 0;
466 }
467
468 static const struct meson_i2c_data i2c_meson6_data = {
469 .div_factor = 4,
470 };
471
472 static const struct meson_i2c_data i2c_gxbb_data = {
473 .div_factor = 4,
474 };
475
476 static const struct meson_i2c_data i2c_axg_data = {
477 .div_factor = 3,
478 };
479
480 static const struct of_device_id meson_i2c_match[] = {
481 { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
482 { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
483 { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
484 {},
485 };
486
487 MODULE_DEVICE_TABLE(of, meson_i2c_match);
488
489 static struct platform_driver meson_i2c_driver = {
490 .probe = meson_i2c_probe,
491 .remove = meson_i2c_remove,
492 .driver = {
493 .name = "meson-i2c",
494 .of_match_table = meson_i2c_match,
495 },
496 };
497
498 module_platform_driver(meson_i2c_driver);
499
500 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
501 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
502 MODULE_LICENSE("GPL v2");
503