1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
6 *
7 * This code was implemented by Mocean Laboratories AB when porting linux
8 * to the automotive development board Russellville. The copyright holder
9 * as seen in the header is Intel corporation.
10 * Mocean Laboratories forked off the GNU/Linux platform work into a
11 * separate company called Pelagicore AB, which committed the code to the
12 * kernel.
13 */
14
15 /* Supports:
16 * Xilinx IIC
17 */
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/wait.h>
27 #include <linux/platform_data/i2c-xiic.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/of.h>
31 #include <linux/clk.h>
32 #include <linux/pm_runtime.h>
33
34 #define DRIVER_NAME "xiic-i2c"
35
36 enum xilinx_i2c_state {
37 STATE_DONE,
38 STATE_ERROR,
39 STATE_START
40 };
41
42 enum xiic_endian {
43 LITTLE,
44 BIG
45 };
46
47 /**
48 * struct xiic_i2c - Internal representation of the XIIC I2C bus
49 * @base: Memory base of the HW registers
50 * @wait: Wait queue for callers
51 * @adap: Kernel adapter representation
52 * @tx_msg: Messages from above to be sent
53 * @lock: Mutual exclusion
54 * @tx_pos: Current pos in TX message
55 * @nmsgs: Number of messages in tx_msg
56 * @state: See STATE_
57 * @rx_msg: Current RX message
58 * @rx_pos: Position within current RX message
59 * @endianness: big/little-endian byte order
60 */
61 struct xiic_i2c {
62 struct device *dev;
63 void __iomem *base;
64 wait_queue_head_t wait;
65 struct i2c_adapter adap;
66 struct i2c_msg *tx_msg;
67 struct mutex lock;
68 unsigned int tx_pos;
69 unsigned int nmsgs;
70 enum xilinx_i2c_state state;
71 struct i2c_msg *rx_msg;
72 int rx_pos;
73 enum xiic_endian endianness;
74 struct clk *clk;
75 };
76
77
78 #define XIIC_MSB_OFFSET 0
79 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
80
81 /*
82 * Register offsets in bytes from RegisterBase. Three is added to the
83 * base offset to access LSB (IBM style) of the word
84 */
85 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
86 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
87 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
88 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
89 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
90 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
91 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
92 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
93 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
94 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
95
96 /* Control Register masks */
97 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
98 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
99 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
100 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
101 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
102 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
103 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
104
105 /* Status Register masks */
106 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
107 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
108 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
109 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
110 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
111 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
112 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
113 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
114
115 /* Interrupt Status Register masks Interrupt occurs when... */
116 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
117 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
118 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
119 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
120 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
121 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
122 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
123 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
124
125 /* The following constants specify the depth of the FIFOs */
126 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
127 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
128
129 /* The following constants specify groups of interrupts that are typically
130 * enabled or disables at the same time
131 */
132 #define XIIC_TX_INTERRUPTS \
133 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
134
135 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
136
137 /*
138 * Tx Fifo upper bit masks.
139 */
140 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
141 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
142
143 /*
144 * The following constants define the register offsets for the Interrupt
145 * registers. There are some holes in the memory map for reserved addresses
146 * to allow other registers to be added and still match the memory map of the
147 * interrupt controller registers
148 */
149 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
150 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
151 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
152 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
153
154 #define XIIC_RESET_MASK 0xAUL
155
156 #define XIIC_PM_TIMEOUT 1000 /* ms */
157 /*
158 * The following constant is used for the device global interrupt enable
159 * register, to enable all interrupts for the device, this is the only bit
160 * in the register
161 */
162 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
163
164 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
165 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
166
167 static void xiic_start_xfer(struct xiic_i2c *i2c);
168 static void __xiic_start_xfer(struct xiic_i2c *i2c);
169
170 /*
171 * For the register read and write functions, a little-endian and big-endian
172 * version are necessary. Endianness is detected during the probe function.
173 * Only the least significant byte [doublet] of the register are ever
174 * accessed. This requires an offset of 3 [2] from the base address for
175 * big-endian systems.
176 */
177
xiic_setreg8(struct xiic_i2c * i2c,int reg,u8 value)178 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
179 {
180 if (i2c->endianness == LITTLE)
181 iowrite8(value, i2c->base + reg);
182 else
183 iowrite8(value, i2c->base + reg + 3);
184 }
185
xiic_getreg8(struct xiic_i2c * i2c,int reg)186 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
187 {
188 u8 ret;
189
190 if (i2c->endianness == LITTLE)
191 ret = ioread8(i2c->base + reg);
192 else
193 ret = ioread8(i2c->base + reg + 3);
194 return ret;
195 }
196
xiic_setreg16(struct xiic_i2c * i2c,int reg,u16 value)197 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
198 {
199 if (i2c->endianness == LITTLE)
200 iowrite16(value, i2c->base + reg);
201 else
202 iowrite16be(value, i2c->base + reg + 2);
203 }
204
xiic_setreg32(struct xiic_i2c * i2c,int reg,int value)205 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
206 {
207 if (i2c->endianness == LITTLE)
208 iowrite32(value, i2c->base + reg);
209 else
210 iowrite32be(value, i2c->base + reg);
211 }
212
xiic_getreg32(struct xiic_i2c * i2c,int reg)213 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
214 {
215 u32 ret;
216
217 if (i2c->endianness == LITTLE)
218 ret = ioread32(i2c->base + reg);
219 else
220 ret = ioread32be(i2c->base + reg);
221 return ret;
222 }
223
xiic_irq_dis(struct xiic_i2c * i2c,u32 mask)224 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
225 {
226 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
227 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
228 }
229
xiic_irq_en(struct xiic_i2c * i2c,u32 mask)230 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
231 {
232 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
233 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
234 }
235
xiic_irq_clr(struct xiic_i2c * i2c,u32 mask)236 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
237 {
238 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
239 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
240 }
241
xiic_irq_clr_en(struct xiic_i2c * i2c,u32 mask)242 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
243 {
244 xiic_irq_clr(i2c, mask);
245 xiic_irq_en(i2c, mask);
246 }
247
xiic_clear_rx_fifo(struct xiic_i2c * i2c)248 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
249 {
250 u8 sr;
251 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
252 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
253 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
254 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
255 }
256
xiic_reinit(struct xiic_i2c * i2c)257 static void xiic_reinit(struct xiic_i2c *i2c)
258 {
259 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
260
261 /* Set receive Fifo depth to maximum (zero based). */
262 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
263
264 /* Reset Tx Fifo. */
265 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
266
267 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
268 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
269
270 /* make sure RX fifo is empty */
271 xiic_clear_rx_fifo(i2c);
272
273 /* Enable interrupts */
274 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
275
276 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
277 }
278
xiic_deinit(struct xiic_i2c * i2c)279 static void xiic_deinit(struct xiic_i2c *i2c)
280 {
281 u8 cr;
282
283 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
284
285 /* Disable IIC Device. */
286 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
287 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
288 }
289
xiic_read_rx(struct xiic_i2c * i2c)290 static void xiic_read_rx(struct xiic_i2c *i2c)
291 {
292 u8 bytes_in_fifo;
293 int i;
294
295 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
296
297 dev_dbg(i2c->adap.dev.parent,
298 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
299 __func__, bytes_in_fifo, xiic_rx_space(i2c),
300 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
301 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
302
303 if (bytes_in_fifo > xiic_rx_space(i2c))
304 bytes_in_fifo = xiic_rx_space(i2c);
305
306 for (i = 0; i < bytes_in_fifo; i++)
307 i2c->rx_msg->buf[i2c->rx_pos++] =
308 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
309
310 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
311 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
312 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
313 }
314
xiic_tx_fifo_space(struct xiic_i2c * i2c)315 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
316 {
317 /* return the actual space left in the FIFO */
318 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
319 }
320
xiic_fill_tx_fifo(struct xiic_i2c * i2c)321 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
322 {
323 u8 fifo_space = xiic_tx_fifo_space(i2c);
324 int len = xiic_tx_space(i2c);
325
326 len = (len > fifo_space) ? fifo_space : len;
327
328 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
329 __func__, len, fifo_space);
330
331 while (len--) {
332 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
333 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
334 /* last message in transfer -> STOP */
335 data |= XIIC_TX_DYN_STOP_MASK;
336 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
337 }
338 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
339 }
340 }
341
xiic_wakeup(struct xiic_i2c * i2c,int code)342 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
343 {
344 i2c->tx_msg = NULL;
345 i2c->rx_msg = NULL;
346 i2c->nmsgs = 0;
347 i2c->state = code;
348 wake_up(&i2c->wait);
349 }
350
xiic_process(int irq,void * dev_id)351 static irqreturn_t xiic_process(int irq, void *dev_id)
352 {
353 struct xiic_i2c *i2c = dev_id;
354 u32 pend, isr, ier;
355 u32 clr = 0;
356 int xfer_more = 0;
357 int wakeup_req = 0;
358 int wakeup_code = 0;
359
360 /* Get the interrupt Status from the IPIF. There is no clearing of
361 * interrupts in the IPIF. Interrupts must be cleared at the source.
362 * To find which interrupts are pending; AND interrupts pending with
363 * interrupts masked.
364 */
365 mutex_lock(&i2c->lock);
366 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
367 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
368 pend = isr & ier;
369
370 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
371 __func__, ier, isr, pend);
372 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
373 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
374 i2c->tx_msg, i2c->nmsgs);
375
376
377 /* Service requesting interrupt */
378 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
379 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
380 !(pend & XIIC_INTR_RX_FULL_MASK))) {
381 /* bus arbritration lost, or...
382 * Transmit error _OR_ RX completed
383 * if this happens when RX_FULL is not set
384 * this is probably a TX error
385 */
386
387 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
388
389 /* dynamic mode seem to suffer from problems if we just flushes
390 * fifos and the next message is a TX with len 0 (only addr)
391 * reset the IP instead of just flush fifos
392 */
393 xiic_reinit(i2c);
394
395 if (i2c->rx_msg) {
396 wakeup_req = 1;
397 wakeup_code = STATE_ERROR;
398 }
399 if (i2c->tx_msg) {
400 wakeup_req = 1;
401 wakeup_code = STATE_ERROR;
402 }
403 /* don't try to handle other events */
404 goto out;
405 }
406 if (pend & XIIC_INTR_RX_FULL_MASK) {
407 /* Receive register/FIFO is full */
408
409 clr |= XIIC_INTR_RX_FULL_MASK;
410 if (!i2c->rx_msg) {
411 dev_dbg(i2c->adap.dev.parent,
412 "%s unexpected RX IRQ\n", __func__);
413 xiic_clear_rx_fifo(i2c);
414 goto out;
415 }
416
417 xiic_read_rx(i2c);
418 if (xiic_rx_space(i2c) == 0) {
419 /* this is the last part of the message */
420 i2c->rx_msg = NULL;
421
422 /* also clear TX error if there (RX complete) */
423 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
424
425 dev_dbg(i2c->adap.dev.parent,
426 "%s end of message, nmsgs: %d\n",
427 __func__, i2c->nmsgs);
428
429 /* send next message if this wasn't the last,
430 * otherwise the transfer will be finialise when
431 * receiving the bus not busy interrupt
432 */
433 if (i2c->nmsgs > 1) {
434 i2c->nmsgs--;
435 i2c->tx_msg++;
436 dev_dbg(i2c->adap.dev.parent,
437 "%s will start next...\n", __func__);
438 xfer_more = 1;
439 }
440 }
441 }
442 if (pend & XIIC_INTR_BNB_MASK) {
443 /* IIC bus has transitioned to not busy */
444 clr |= XIIC_INTR_BNB_MASK;
445
446 /* The bus is not busy, disable BusNotBusy interrupt */
447 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
448
449 if (!i2c->tx_msg)
450 goto out;
451
452 wakeup_req = 1;
453
454 if (i2c->nmsgs == 1 && !i2c->rx_msg &&
455 xiic_tx_space(i2c) == 0)
456 wakeup_code = STATE_DONE;
457 else
458 wakeup_code = STATE_ERROR;
459 }
460 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
461 /* Transmit register/FIFO is empty or ½ empty */
462
463 clr |= (pend &
464 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
465
466 if (!i2c->tx_msg) {
467 dev_dbg(i2c->adap.dev.parent,
468 "%s unexpected TX IRQ\n", __func__);
469 goto out;
470 }
471
472 xiic_fill_tx_fifo(i2c);
473
474 /* current message sent and there is space in the fifo */
475 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
476 dev_dbg(i2c->adap.dev.parent,
477 "%s end of message sent, nmsgs: %d\n",
478 __func__, i2c->nmsgs);
479 if (i2c->nmsgs > 1) {
480 i2c->nmsgs--;
481 i2c->tx_msg++;
482 xfer_more = 1;
483 } else {
484 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
485
486 dev_dbg(i2c->adap.dev.parent,
487 "%s Got TX IRQ but no more to do...\n",
488 __func__);
489 }
490 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
491 /* current frame is sent and is last,
492 * make sure to disable tx half
493 */
494 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
495 }
496 out:
497 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
498
499 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
500 if (xfer_more)
501 __xiic_start_xfer(i2c);
502 if (wakeup_req)
503 xiic_wakeup(i2c, wakeup_code);
504
505 WARN_ON(xfer_more && wakeup_req);
506
507 mutex_unlock(&i2c->lock);
508 return IRQ_HANDLED;
509 }
510
xiic_bus_busy(struct xiic_i2c * i2c)511 static int xiic_bus_busy(struct xiic_i2c *i2c)
512 {
513 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
514
515 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
516 }
517
xiic_busy(struct xiic_i2c * i2c)518 static int xiic_busy(struct xiic_i2c *i2c)
519 {
520 int tries = 3;
521 int err;
522
523 if (i2c->tx_msg)
524 return -EBUSY;
525
526 /* for instance if previous transfer was terminated due to TX error
527 * it might be that the bus is on it's way to become available
528 * give it at most 3 ms to wake
529 */
530 err = xiic_bus_busy(i2c);
531 while (err && tries--) {
532 msleep(1);
533 err = xiic_bus_busy(i2c);
534 }
535
536 return err;
537 }
538
xiic_start_recv(struct xiic_i2c * i2c)539 static void xiic_start_recv(struct xiic_i2c *i2c)
540 {
541 u8 rx_watermark;
542 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
543 unsigned long flags;
544
545 /* Clear and enable Rx full interrupt. */
546 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
547
548 /* we want to get all but last byte, because the TX_ERROR IRQ is used
549 * to inidicate error ACK on the address, and negative ack on the last
550 * received byte, so to not mix them receive all but last.
551 * In the case where there is only one byte to receive
552 * we can check if ERROR and RX full is set at the same time
553 */
554 rx_watermark = msg->len;
555 if (rx_watermark > IIC_RX_FIFO_DEPTH)
556 rx_watermark = IIC_RX_FIFO_DEPTH;
557 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
558
559 local_irq_save(flags);
560 if (!(msg->flags & I2C_M_NOSTART))
561 /* write the address */
562 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
563 i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK);
564
565 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
566
567 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
568 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
569 local_irq_restore(flags);
570
571 if (i2c->nmsgs == 1)
572 /* very last, enable bus not busy as well */
573 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
574
575 /* the message is tx:ed */
576 i2c->tx_pos = msg->len;
577 }
578
xiic_start_send(struct xiic_i2c * i2c)579 static void xiic_start_send(struct xiic_i2c *i2c)
580 {
581 struct i2c_msg *msg = i2c->tx_msg;
582
583 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
584
585 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
586 __func__, msg, msg->len);
587 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
588 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
589 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
590
591 if (!(msg->flags & I2C_M_NOSTART)) {
592 /* write the address */
593 u16 data = i2c_8bit_addr_from_msg(msg) |
594 XIIC_TX_DYN_START_MASK;
595 if ((i2c->nmsgs == 1) && msg->len == 0)
596 /* no data and last message -> add STOP */
597 data |= XIIC_TX_DYN_STOP_MASK;
598
599 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
600 }
601
602 xiic_fill_tx_fifo(i2c);
603
604 /* Clear any pending Tx empty, Tx Error and then enable them. */
605 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
606 XIIC_INTR_BNB_MASK);
607 }
608
xiic_isr(int irq,void * dev_id)609 static irqreturn_t xiic_isr(int irq, void *dev_id)
610 {
611 struct xiic_i2c *i2c = dev_id;
612 u32 pend, isr, ier;
613 irqreturn_t ret = IRQ_NONE;
614 /* Do not processes a devices interrupts if the device has no
615 * interrupts pending
616 */
617
618 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
619
620 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
621 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
622 pend = isr & ier;
623 if (pend)
624 ret = IRQ_WAKE_THREAD;
625
626 return ret;
627 }
628
__xiic_start_xfer(struct xiic_i2c * i2c)629 static void __xiic_start_xfer(struct xiic_i2c *i2c)
630 {
631 int first = 1;
632 int fifo_space = xiic_tx_fifo_space(i2c);
633 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
634 __func__, i2c->tx_msg, fifo_space);
635
636 if (!i2c->tx_msg)
637 return;
638
639 i2c->rx_pos = 0;
640 i2c->tx_pos = 0;
641 i2c->state = STATE_START;
642 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
643 if (!first) {
644 i2c->nmsgs--;
645 i2c->tx_msg++;
646 i2c->tx_pos = 0;
647 } else
648 first = 0;
649
650 if (i2c->tx_msg->flags & I2C_M_RD) {
651 /* we dont date putting several reads in the FIFO */
652 xiic_start_recv(i2c);
653 return;
654 } else {
655 xiic_start_send(i2c);
656 if (xiic_tx_space(i2c) != 0) {
657 /* the message could not be completely sent */
658 break;
659 }
660 }
661
662 fifo_space = xiic_tx_fifo_space(i2c);
663 }
664
665 /* there are more messages or the current one could not be completely
666 * put into the FIFO, also enable the half empty interrupt
667 */
668 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
669 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
670
671 }
672
xiic_start_xfer(struct xiic_i2c * i2c)673 static void xiic_start_xfer(struct xiic_i2c *i2c)
674 {
675 mutex_lock(&i2c->lock);
676 xiic_reinit(i2c);
677 __xiic_start_xfer(i2c);
678 mutex_unlock(&i2c->lock);
679 }
680
xiic_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)681 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
682 {
683 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
684 int err;
685
686 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
687 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
688
689 err = pm_runtime_get_sync(i2c->dev);
690 if (err < 0)
691 return err;
692
693 err = xiic_busy(i2c);
694 if (err)
695 goto out;
696
697 i2c->tx_msg = msgs;
698 i2c->nmsgs = num;
699
700 xiic_start_xfer(i2c);
701
702 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
703 (i2c->state == STATE_DONE), HZ)) {
704 err = (i2c->state == STATE_DONE) ? num : -EIO;
705 goto out;
706 } else {
707 i2c->tx_msg = NULL;
708 i2c->rx_msg = NULL;
709 i2c->nmsgs = 0;
710 err = -ETIMEDOUT;
711 goto out;
712 }
713 out:
714 pm_runtime_mark_last_busy(i2c->dev);
715 pm_runtime_put_autosuspend(i2c->dev);
716 return err;
717 }
718
xiic_func(struct i2c_adapter * adap)719 static u32 xiic_func(struct i2c_adapter *adap)
720 {
721 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
722 }
723
724 static const struct i2c_algorithm xiic_algorithm = {
725 .master_xfer = xiic_xfer,
726 .functionality = xiic_func,
727 };
728
729 static const struct i2c_adapter_quirks xiic_quirks = {
730 .max_read_len = 255,
731 };
732
733 static const struct i2c_adapter xiic_adapter = {
734 .owner = THIS_MODULE,
735 .class = I2C_CLASS_DEPRECATED,
736 .algo = &xiic_algorithm,
737 .quirks = &xiic_quirks,
738 };
739
740
xiic_i2c_probe(struct platform_device * pdev)741 static int xiic_i2c_probe(struct platform_device *pdev)
742 {
743 struct xiic_i2c *i2c;
744 struct xiic_i2c_platform_data *pdata;
745 struct resource *res;
746 int ret, irq;
747 u8 i;
748 u32 sr;
749
750 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
751 if (!i2c)
752 return -ENOMEM;
753
754 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
755 i2c->base = devm_ioremap_resource(&pdev->dev, res);
756 if (IS_ERR(i2c->base))
757 return PTR_ERR(i2c->base);
758
759 irq = platform_get_irq(pdev, 0);
760 if (irq < 0)
761 return irq;
762
763 pdata = dev_get_platdata(&pdev->dev);
764
765 /* hook up driver to tree */
766 platform_set_drvdata(pdev, i2c);
767 i2c->adap = xiic_adapter;
768 i2c_set_adapdata(&i2c->adap, i2c);
769 i2c->adap.dev.parent = &pdev->dev;
770 i2c->adap.dev.of_node = pdev->dev.of_node;
771 snprintf(i2c->adap.name, sizeof(i2c->adap.name),
772 DRIVER_NAME " %s", pdev->name);
773
774 mutex_init(&i2c->lock);
775 init_waitqueue_head(&i2c->wait);
776
777 i2c->clk = devm_clk_get(&pdev->dev, NULL);
778 if (IS_ERR(i2c->clk)) {
779 dev_err(&pdev->dev, "input clock not found.\n");
780 return PTR_ERR(i2c->clk);
781 }
782 ret = clk_prepare_enable(i2c->clk);
783 if (ret) {
784 dev_err(&pdev->dev, "Unable to enable clock.\n");
785 return ret;
786 }
787 i2c->dev = &pdev->dev;
788 pm_runtime_enable(i2c->dev);
789 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
790 pm_runtime_use_autosuspend(i2c->dev);
791 pm_runtime_set_active(i2c->dev);
792 ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
793 xiic_process, IRQF_ONESHOT,
794 pdev->name, i2c);
795
796 if (ret < 0) {
797 dev_err(&pdev->dev, "Cannot claim IRQ\n");
798 goto err_clk_dis;
799 }
800
801 /*
802 * Detect endianness
803 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
804 * set, assume that the endianness was wrong and swap.
805 */
806 i2c->endianness = LITTLE;
807 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
808 /* Reset is cleared in xiic_reinit */
809 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
810 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
811 i2c->endianness = BIG;
812
813 xiic_reinit(i2c);
814
815 /* add i2c adapter to i2c tree */
816 ret = i2c_add_adapter(&i2c->adap);
817 if (ret) {
818 xiic_deinit(i2c);
819 goto err_clk_dis;
820 }
821
822 if (pdata) {
823 /* add in known devices to the bus */
824 for (i = 0; i < pdata->num_devices; i++)
825 i2c_new_device(&i2c->adap, pdata->devices + i);
826 }
827
828 return 0;
829
830 err_clk_dis:
831 pm_runtime_set_suspended(&pdev->dev);
832 pm_runtime_disable(&pdev->dev);
833 clk_disable_unprepare(i2c->clk);
834 return ret;
835 }
836
xiic_i2c_remove(struct platform_device * pdev)837 static int xiic_i2c_remove(struct platform_device *pdev)
838 {
839 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
840 int ret;
841
842 /* remove adapter & data */
843 i2c_del_adapter(&i2c->adap);
844
845 ret = clk_prepare_enable(i2c->clk);
846 if (ret) {
847 dev_err(&pdev->dev, "Unable to enable clock.\n");
848 return ret;
849 }
850 xiic_deinit(i2c);
851 clk_disable_unprepare(i2c->clk);
852 pm_runtime_disable(&pdev->dev);
853
854 return 0;
855 }
856
857 #if defined(CONFIG_OF)
858 static const struct of_device_id xiic_of_match[] = {
859 { .compatible = "xlnx,xps-iic-2.00.a", },
860 {},
861 };
862 MODULE_DEVICE_TABLE(of, xiic_of_match);
863 #endif
864
xiic_i2c_runtime_suspend(struct device * dev)865 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
866 {
867 struct xiic_i2c *i2c = dev_get_drvdata(dev);
868
869 clk_disable(i2c->clk);
870
871 return 0;
872 }
873
xiic_i2c_runtime_resume(struct device * dev)874 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
875 {
876 struct xiic_i2c *i2c = dev_get_drvdata(dev);
877 int ret;
878
879 ret = clk_enable(i2c->clk);
880 if (ret) {
881 dev_err(dev, "Cannot enable clock.\n");
882 return ret;
883 }
884
885 return 0;
886 }
887
888 static const struct dev_pm_ops xiic_dev_pm_ops = {
889 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
890 xiic_i2c_runtime_resume, NULL)
891 };
892 static struct platform_driver xiic_i2c_driver = {
893 .probe = xiic_i2c_probe,
894 .remove = xiic_i2c_remove,
895 .driver = {
896 .name = DRIVER_NAME,
897 .of_match_table = of_match_ptr(xiic_of_match),
898 .pm = &xiic_dev_pm_ops,
899 },
900 };
901
902 module_platform_driver(xiic_i2c_driver);
903
904 MODULE_ALIAS("platform:" DRIVER_NAME);
905 MODULE_AUTHOR("info@mocean-labs.com");
906 MODULE_DESCRIPTION("Xilinx I2C bus driver");
907 MODULE_LICENSE("GPL v2");
908 MODULE_ALIAS("platform:"DRIVER_NAME);
909