1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 * Inspired from: fsl-imx25-tsadc
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdesc.h>
16 #include <linux/irqdomain.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24
25 #include "stm32-adc-core.h"
26
27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
28
29 /* SYSCFG registers */
30 #define STM32MP1_SYSCFG_PMCSETR 0x04
31 #define STM32MP1_SYSCFG_PMCCLRR 0x44
32
33 /* SYSCFG bit fields */
34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
35
36 /* SYSCFG capability flags */
37 #define HAS_VBOOSTER BIT(0)
38 #define HAS_ANASWVDD BIT(1)
39
40 /**
41 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
42 * @csr: common status register offset
43 * @ccr: common control register offset
44 * @eoc1: adc1 end of conversion flag in @csr
45 * @eoc2: adc2 end of conversion flag in @csr
46 * @eoc3: adc3 end of conversion flag in @csr
47 * @ier: interrupt enable register offset for each adc
48 * @eocie_msk: end of conversion interrupt enable mask in @ier
49 */
50 struct stm32_adc_common_regs {
51 u32 csr;
52 u32 ccr;
53 u32 eoc1_msk;
54 u32 eoc2_msk;
55 u32 eoc3_msk;
56 u32 ier;
57 u32 eocie_msk;
58 };
59
60 struct stm32_adc_priv;
61
62 /**
63 * stm32_adc_priv_cfg - stm32 core compatible configuration data
64 * @regs: common registers for all instances
65 * @clk_sel: clock selection routine
66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
67 * @has_syscfg: SYSCFG capability flags
68 * @num_irqs: number of interrupt lines
69 */
70 struct stm32_adc_priv_cfg {
71 const struct stm32_adc_common_regs *regs;
72 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
73 u32 max_clk_rate_hz;
74 unsigned int has_syscfg;
75 unsigned int num_irqs;
76 };
77
78 /**
79 * struct stm32_adc_priv - stm32 ADC core private data
80 * @irq: irq(s) for ADC block
81 * @domain: irq domain reference
82 * @aclk: clock reference for the analog circuitry
83 * @bclk: bus clock common for all ADCs, depends on part used
84 * @booster: booster supply reference
85 * @vdd: vdd supply reference
86 * @vdda: vdda analog supply reference
87 * @vref: regulator reference
88 * @vdd_uv: vdd supply voltage (microvolts)
89 * @vdda_uv: vdda supply voltage (microvolts)
90 * @cfg: compatible configuration data
91 * @common: common data for all ADC instances
92 * @ccr_bak: backup CCR in low power mode
93 * @syscfg: reference to syscon, system control registers
94 */
95 struct stm32_adc_priv {
96 int irq[STM32_ADC_MAX_ADCS];
97 struct irq_domain *domain;
98 struct clk *aclk;
99 struct clk *bclk;
100 struct regulator *booster;
101 struct regulator *vdd;
102 struct regulator *vdda;
103 struct regulator *vref;
104 int vdd_uv;
105 int vdda_uv;
106 const struct stm32_adc_priv_cfg *cfg;
107 struct stm32_adc_common common;
108 u32 ccr_bak;
109 struct regmap *syscfg;
110 };
111
to_stm32_adc_priv(struct stm32_adc_common * com)112 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
113 {
114 return container_of(com, struct stm32_adc_priv, common);
115 }
116
117 /* STM32F4 ADC internal common clock prescaler division ratios */
118 static int stm32f4_pclk_div[] = {2, 4, 6, 8};
119
120 /**
121 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
122 * @priv: stm32 ADC core private data
123 * Select clock prescaler used for analog conversions, before using ADC.
124 */
stm32f4_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)125 static int stm32f4_adc_clk_sel(struct platform_device *pdev,
126 struct stm32_adc_priv *priv)
127 {
128 unsigned long rate;
129 u32 val;
130 int i;
131
132 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
133 if (!priv->aclk) {
134 dev_err(&pdev->dev, "No 'adc' clock found\n");
135 return -ENOENT;
136 }
137
138 rate = clk_get_rate(priv->aclk);
139 if (!rate) {
140 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
141 return -EINVAL;
142 }
143
144 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
145 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
146 break;
147 }
148 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
149 dev_err(&pdev->dev, "adc clk selection failed\n");
150 return -EINVAL;
151 }
152
153 priv->common.rate = rate / stm32f4_pclk_div[i];
154 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
155 val &= ~STM32F4_ADC_ADCPRE_MASK;
156 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
157 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
158
159 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
160 priv->common.rate / 1000);
161
162 return 0;
163 }
164
165 /**
166 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
167 * @ckmode: ADC clock mode, Async or sync with prescaler.
168 * @presc: prescaler bitfield for async clock mode
169 * @div: prescaler division ratio
170 */
171 struct stm32h7_adc_ck_spec {
172 u32 ckmode;
173 u32 presc;
174 int div;
175 };
176
177 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
178 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
179 { 0, 0, 1 },
180 { 0, 1, 2 },
181 { 0, 2, 4 },
182 { 0, 3, 6 },
183 { 0, 4, 8 },
184 { 0, 5, 10 },
185 { 0, 6, 12 },
186 { 0, 7, 16 },
187 { 0, 8, 32 },
188 { 0, 9, 64 },
189 { 0, 10, 128 },
190 { 0, 11, 256 },
191 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
192 { 1, 0, 1 },
193 { 2, 0, 2 },
194 { 3, 0, 4 },
195 };
196
stm32h7_adc_clk_sel(struct platform_device * pdev,struct stm32_adc_priv * priv)197 static int stm32h7_adc_clk_sel(struct platform_device *pdev,
198 struct stm32_adc_priv *priv)
199 {
200 u32 ckmode, presc, val;
201 unsigned long rate;
202 int i, div;
203
204 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
205 if (!priv->bclk) {
206 dev_err(&pdev->dev, "No 'bus' clock found\n");
207 return -ENOENT;
208 }
209
210 /*
211 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
212 * So, choice is to have bus clock mandatory and adc clock optional.
213 * If optional 'adc' clock has been found, then try to use it first.
214 */
215 if (priv->aclk) {
216 /*
217 * Asynchronous clock modes (e.g. ckmode == 0)
218 * From spec: PLL output musn't exceed max rate
219 */
220 rate = clk_get_rate(priv->aclk);
221 if (!rate) {
222 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
223 return -EINVAL;
224 }
225
226 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
227 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
228 presc = stm32h7_adc_ckmodes_spec[i].presc;
229 div = stm32h7_adc_ckmodes_spec[i].div;
230
231 if (ckmode)
232 continue;
233
234 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
235 goto out;
236 }
237 }
238
239 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
240 rate = clk_get_rate(priv->bclk);
241 if (!rate) {
242 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
243 return -EINVAL;
244 }
245
246 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
247 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
248 presc = stm32h7_adc_ckmodes_spec[i].presc;
249 div = stm32h7_adc_ckmodes_spec[i].div;
250
251 if (!ckmode)
252 continue;
253
254 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
255 goto out;
256 }
257
258 dev_err(&pdev->dev, "adc clk selection failed\n");
259 return -EINVAL;
260
261 out:
262 /* rate used later by each ADC instance to control BOOST mode */
263 priv->common.rate = rate / div;
264
265 /* Set common clock mode and prescaler */
266 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
267 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
268 val |= ckmode << STM32H7_CKMODE_SHIFT;
269 val |= presc << STM32H7_PRESC_SHIFT;
270 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
271
272 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
273 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
274
275 return 0;
276 }
277
278 /* STM32F4 common registers definitions */
279 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
280 .csr = STM32F4_ADC_CSR,
281 .ccr = STM32F4_ADC_CCR,
282 .eoc1_msk = STM32F4_EOC1,
283 .eoc2_msk = STM32F4_EOC2,
284 .eoc3_msk = STM32F4_EOC3,
285 .ier = STM32F4_ADC_CR1,
286 .eocie_msk = STM32F4_EOCIE,
287 };
288
289 /* STM32H7 common registers definitions */
290 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
291 .csr = STM32H7_ADC_CSR,
292 .ccr = STM32H7_ADC_CCR,
293 .eoc1_msk = STM32H7_EOC_MST,
294 .eoc2_msk = STM32H7_EOC_SLV,
295 .ier = STM32H7_ADC_IER,
296 .eocie_msk = STM32H7_EOCIE,
297 };
298
299 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
300 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
301 };
302
stm32_adc_eoc_enabled(struct stm32_adc_priv * priv,unsigned int adc)303 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
304 unsigned int adc)
305 {
306 u32 ier, offset = stm32_adc_offset[adc];
307
308 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
309
310 return ier & priv->cfg->regs->eocie_msk;
311 }
312
313 /* ADC common interrupt for all instances */
stm32_adc_irq_handler(struct irq_desc * desc)314 static void stm32_adc_irq_handler(struct irq_desc *desc)
315 {
316 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
317 struct irq_chip *chip = irq_desc_get_chip(desc);
318 u32 status;
319
320 chained_irq_enter(chip, desc);
321 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
322
323 /*
324 * End of conversion may be handled by using IRQ or DMA. There may be a
325 * race here when two conversions complete at the same time on several
326 * ADCs. EOC may be read 'set' for several ADCs, with:
327 * - an ADC configured to use DMA (EOC triggers the DMA request, and
328 * is then automatically cleared by DR read in hardware)
329 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
330 * be called in this case)
331 * So both EOC status bit in CSR and EOCIE control bit must be checked
332 * before invoking the interrupt handler (e.g. call ISR only for
333 * IRQ-enabled ADCs).
334 */
335 if (status & priv->cfg->regs->eoc1_msk &&
336 stm32_adc_eoc_enabled(priv, 0))
337 generic_handle_irq(irq_find_mapping(priv->domain, 0));
338
339 if (status & priv->cfg->regs->eoc2_msk &&
340 stm32_adc_eoc_enabled(priv, 1))
341 generic_handle_irq(irq_find_mapping(priv->domain, 1));
342
343 if (status & priv->cfg->regs->eoc3_msk &&
344 stm32_adc_eoc_enabled(priv, 2))
345 generic_handle_irq(irq_find_mapping(priv->domain, 2));
346
347 chained_irq_exit(chip, desc);
348 };
349
stm32_adc_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)350 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
351 irq_hw_number_t hwirq)
352 {
353 irq_set_chip_data(irq, d->host_data);
354 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
355
356 return 0;
357 }
358
stm32_adc_domain_unmap(struct irq_domain * d,unsigned int irq)359 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
360 {
361 irq_set_chip_and_handler(irq, NULL, NULL);
362 irq_set_chip_data(irq, NULL);
363 }
364
365 static const struct irq_domain_ops stm32_adc_domain_ops = {
366 .map = stm32_adc_domain_map,
367 .unmap = stm32_adc_domain_unmap,
368 .xlate = irq_domain_xlate_onecell,
369 };
370
stm32_adc_irq_probe(struct platform_device * pdev,struct stm32_adc_priv * priv)371 static int stm32_adc_irq_probe(struct platform_device *pdev,
372 struct stm32_adc_priv *priv)
373 {
374 struct device_node *np = pdev->dev.of_node;
375 unsigned int i;
376
377 /*
378 * Interrupt(s) must be provided, depending on the compatible:
379 * - stm32f4/h7 shares a common interrupt line.
380 * - stm32mp1, has one line per ADC
381 */
382 for (i = 0; i < priv->cfg->num_irqs; i++) {
383 priv->irq[i] = platform_get_irq(pdev, i);
384 if (priv->irq[i] < 0)
385 return priv->irq[i];
386 }
387
388 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
389 &stm32_adc_domain_ops,
390 priv);
391 if (!priv->domain) {
392 dev_err(&pdev->dev, "Failed to add irq domain\n");
393 return -ENOMEM;
394 }
395
396 for (i = 0; i < priv->cfg->num_irqs; i++) {
397 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
398 irq_set_handler_data(priv->irq[i], priv);
399 }
400
401 return 0;
402 }
403
stm32_adc_irq_remove(struct platform_device * pdev,struct stm32_adc_priv * priv)404 static void stm32_adc_irq_remove(struct platform_device *pdev,
405 struct stm32_adc_priv *priv)
406 {
407 int hwirq;
408 unsigned int i;
409
410 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
411 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
412 irq_domain_remove(priv->domain);
413
414 for (i = 0; i < priv->cfg->num_irqs; i++)
415 irq_set_chained_handler(priv->irq[i], NULL);
416 }
417
stm32_adc_core_switches_supply_en(struct stm32_adc_priv * priv,struct device * dev)418 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
419 struct device *dev)
420 {
421 int ret;
422
423 /*
424 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
425 * switches (via PCSEL) which have reduced performances when their
426 * supply is below 2.7V (vdda by default):
427 * - Voltage booster can be used, to get full ADC performances
428 * (increases power consumption).
429 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
430 *
431 * Recommended settings for ANASWVDD and EN_BOOSTER:
432 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
433 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
434 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
435 */
436 if (priv->vdda_uv < 2700000) {
437 if (priv->syscfg && priv->vdd_uv > 2700000) {
438 ret = regulator_enable(priv->vdd);
439 if (ret < 0) {
440 dev_err(dev, "vdd enable failed %d\n", ret);
441 return ret;
442 }
443
444 ret = regmap_write(priv->syscfg,
445 STM32MP1_SYSCFG_PMCSETR,
446 STM32MP1_SYSCFG_ANASWVDD_MASK);
447 if (ret < 0) {
448 regulator_disable(priv->vdd);
449 dev_err(dev, "vdd select failed, %d\n", ret);
450 return ret;
451 }
452 dev_dbg(dev, "analog switches supplied by vdd\n");
453
454 return 0;
455 }
456
457 if (priv->booster) {
458 /*
459 * This is optional, as this is a trade-off between
460 * analog performance and power consumption.
461 */
462 ret = regulator_enable(priv->booster);
463 if (ret < 0) {
464 dev_err(dev, "booster enable failed %d\n", ret);
465 return ret;
466 }
467 dev_dbg(dev, "analog switches supplied by booster\n");
468
469 return 0;
470 }
471 }
472
473 /* Fallback using vdda (default), nothing to do */
474 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
475 priv->vdda_uv);
476
477 return 0;
478 }
479
stm32_adc_core_switches_supply_dis(struct stm32_adc_priv * priv)480 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
481 {
482 if (priv->vdda_uv < 2700000) {
483 if (priv->syscfg && priv->vdd_uv > 2700000) {
484 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
485 STM32MP1_SYSCFG_ANASWVDD_MASK);
486 regulator_disable(priv->vdd);
487 return;
488 }
489 if (priv->booster)
490 regulator_disable(priv->booster);
491 }
492 }
493
stm32_adc_core_hw_start(struct device * dev)494 static int stm32_adc_core_hw_start(struct device *dev)
495 {
496 struct stm32_adc_common *common = dev_get_drvdata(dev);
497 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
498 int ret;
499
500 ret = regulator_enable(priv->vdda);
501 if (ret < 0) {
502 dev_err(dev, "vdda enable failed %d\n", ret);
503 return ret;
504 }
505
506 ret = regulator_get_voltage(priv->vdda);
507 if (ret < 0) {
508 dev_err(dev, "vdda get voltage failed, %d\n", ret);
509 goto err_vdda_disable;
510 }
511 priv->vdda_uv = ret;
512
513 ret = stm32_adc_core_switches_supply_en(priv, dev);
514 if (ret < 0)
515 goto err_vdda_disable;
516
517 ret = regulator_enable(priv->vref);
518 if (ret < 0) {
519 dev_err(dev, "vref enable failed\n");
520 goto err_switches_dis;
521 }
522
523 if (priv->bclk) {
524 ret = clk_prepare_enable(priv->bclk);
525 if (ret < 0) {
526 dev_err(dev, "bus clk enable failed\n");
527 goto err_regulator_disable;
528 }
529 }
530
531 if (priv->aclk) {
532 ret = clk_prepare_enable(priv->aclk);
533 if (ret < 0) {
534 dev_err(dev, "adc clk enable failed\n");
535 goto err_bclk_disable;
536 }
537 }
538
539 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
540
541 return 0;
542
543 err_bclk_disable:
544 if (priv->bclk)
545 clk_disable_unprepare(priv->bclk);
546 err_regulator_disable:
547 regulator_disable(priv->vref);
548 err_switches_dis:
549 stm32_adc_core_switches_supply_dis(priv);
550 err_vdda_disable:
551 regulator_disable(priv->vdda);
552
553 return ret;
554 }
555
stm32_adc_core_hw_stop(struct device * dev)556 static void stm32_adc_core_hw_stop(struct device *dev)
557 {
558 struct stm32_adc_common *common = dev_get_drvdata(dev);
559 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
560
561 /* Backup CCR that may be lost (depends on power state to achieve) */
562 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
563 if (priv->aclk)
564 clk_disable_unprepare(priv->aclk);
565 if (priv->bclk)
566 clk_disable_unprepare(priv->bclk);
567 regulator_disable(priv->vref);
568 stm32_adc_core_switches_supply_dis(priv);
569 regulator_disable(priv->vdda);
570 }
571
stm32_adc_core_switches_probe(struct device * dev,struct stm32_adc_priv * priv)572 static int stm32_adc_core_switches_probe(struct device *dev,
573 struct stm32_adc_priv *priv)
574 {
575 struct device_node *np = dev->of_node;
576 int ret;
577
578 /* Analog switches supply can be controlled by syscfg (optional) */
579 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
580 if (IS_ERR(priv->syscfg)) {
581 ret = PTR_ERR(priv->syscfg);
582 if (ret != -ENODEV) {
583 if (ret != -EPROBE_DEFER)
584 dev_err(dev, "Can't probe syscfg: %d\n", ret);
585 return ret;
586 }
587 priv->syscfg = NULL;
588 }
589
590 /* Booster can be used to supply analog switches (optional) */
591 if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
592 of_property_read_bool(np, "booster-supply")) {
593 priv->booster = devm_regulator_get_optional(dev, "booster");
594 if (IS_ERR(priv->booster)) {
595 ret = PTR_ERR(priv->booster);
596 if (ret != -ENODEV) {
597 if (ret != -EPROBE_DEFER)
598 dev_err(dev, "can't get booster %d\n",
599 ret);
600 return ret;
601 }
602 priv->booster = NULL;
603 }
604 }
605
606 /* Vdd can be used to supply analog switches (optional) */
607 if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
608 of_property_read_bool(np, "vdd-supply")) {
609 priv->vdd = devm_regulator_get_optional(dev, "vdd");
610 if (IS_ERR(priv->vdd)) {
611 ret = PTR_ERR(priv->vdd);
612 if (ret != -ENODEV) {
613 if (ret != -EPROBE_DEFER)
614 dev_err(dev, "can't get vdd %d\n", ret);
615 return ret;
616 }
617 priv->vdd = NULL;
618 }
619 }
620
621 if (priv->vdd) {
622 ret = regulator_enable(priv->vdd);
623 if (ret < 0) {
624 dev_err(dev, "vdd enable failed %d\n", ret);
625 return ret;
626 }
627
628 ret = regulator_get_voltage(priv->vdd);
629 if (ret < 0) {
630 dev_err(dev, "vdd get voltage failed %d\n", ret);
631 regulator_disable(priv->vdd);
632 return ret;
633 }
634 priv->vdd_uv = ret;
635
636 regulator_disable(priv->vdd);
637 }
638
639 return 0;
640 }
641
stm32_adc_probe(struct platform_device * pdev)642 static int stm32_adc_probe(struct platform_device *pdev)
643 {
644 struct stm32_adc_priv *priv;
645 struct device *dev = &pdev->dev;
646 struct device_node *np = pdev->dev.of_node;
647 struct resource *res;
648 int ret;
649
650 if (!pdev->dev.of_node)
651 return -ENODEV;
652
653 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
654 if (!priv)
655 return -ENOMEM;
656 platform_set_drvdata(pdev, &priv->common);
657
658 priv->cfg = (const struct stm32_adc_priv_cfg *)
659 of_match_device(dev->driver->of_match_table, dev)->data;
660
661 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
662 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
663 if (IS_ERR(priv->common.base))
664 return PTR_ERR(priv->common.base);
665 priv->common.phys_base = res->start;
666
667 priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
668 if (IS_ERR(priv->vdda)) {
669 ret = PTR_ERR(priv->vdda);
670 if (ret != -EPROBE_DEFER)
671 dev_err(&pdev->dev, "vdda get failed, %d\n", ret);
672 return ret;
673 }
674
675 priv->vref = devm_regulator_get(&pdev->dev, "vref");
676 if (IS_ERR(priv->vref)) {
677 ret = PTR_ERR(priv->vref);
678 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
679 return ret;
680 }
681
682 priv->aclk = devm_clk_get(&pdev->dev, "adc");
683 if (IS_ERR(priv->aclk)) {
684 ret = PTR_ERR(priv->aclk);
685 if (ret != -ENOENT) {
686 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
687 return ret;
688 }
689 priv->aclk = NULL;
690 }
691
692 priv->bclk = devm_clk_get(&pdev->dev, "bus");
693 if (IS_ERR(priv->bclk)) {
694 ret = PTR_ERR(priv->bclk);
695 if (ret != -ENOENT) {
696 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
697 return ret;
698 }
699 priv->bclk = NULL;
700 }
701
702 ret = stm32_adc_core_switches_probe(dev, priv);
703 if (ret)
704 return ret;
705
706 pm_runtime_get_noresume(dev);
707 pm_runtime_set_active(dev);
708 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
709 pm_runtime_use_autosuspend(dev);
710 pm_runtime_enable(dev);
711
712 ret = stm32_adc_core_hw_start(dev);
713 if (ret)
714 goto err_pm_stop;
715
716 ret = regulator_get_voltage(priv->vref);
717 if (ret < 0) {
718 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
719 goto err_hw_stop;
720 }
721 priv->common.vref_mv = ret / 1000;
722 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
723
724 ret = priv->cfg->clk_sel(pdev, priv);
725 if (ret < 0)
726 goto err_hw_stop;
727
728 ret = stm32_adc_irq_probe(pdev, priv);
729 if (ret < 0)
730 goto err_hw_stop;
731
732 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
733 if (ret < 0) {
734 dev_err(&pdev->dev, "failed to populate DT children\n");
735 goto err_irq_remove;
736 }
737
738 pm_runtime_mark_last_busy(dev);
739 pm_runtime_put_autosuspend(dev);
740
741 return 0;
742
743 err_irq_remove:
744 stm32_adc_irq_remove(pdev, priv);
745 err_hw_stop:
746 stm32_adc_core_hw_stop(dev);
747 err_pm_stop:
748 pm_runtime_disable(dev);
749 pm_runtime_set_suspended(dev);
750 pm_runtime_put_noidle(dev);
751
752 return ret;
753 }
754
stm32_adc_remove(struct platform_device * pdev)755 static int stm32_adc_remove(struct platform_device *pdev)
756 {
757 struct stm32_adc_common *common = platform_get_drvdata(pdev);
758 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
759
760 pm_runtime_get_sync(&pdev->dev);
761 of_platform_depopulate(&pdev->dev);
762 stm32_adc_irq_remove(pdev, priv);
763 stm32_adc_core_hw_stop(&pdev->dev);
764 pm_runtime_disable(&pdev->dev);
765 pm_runtime_set_suspended(&pdev->dev);
766 pm_runtime_put_noidle(&pdev->dev);
767
768 return 0;
769 }
770
771 #if defined(CONFIG_PM)
stm32_adc_core_runtime_suspend(struct device * dev)772 static int stm32_adc_core_runtime_suspend(struct device *dev)
773 {
774 stm32_adc_core_hw_stop(dev);
775
776 return 0;
777 }
778
stm32_adc_core_runtime_resume(struct device * dev)779 static int stm32_adc_core_runtime_resume(struct device *dev)
780 {
781 return stm32_adc_core_hw_start(dev);
782 }
783
stm32_adc_core_runtime_idle(struct device * dev)784 static int stm32_adc_core_runtime_idle(struct device *dev)
785 {
786 pm_runtime_mark_last_busy(dev);
787
788 return 0;
789 }
790 #endif
791
792 static const struct dev_pm_ops stm32_adc_core_pm_ops = {
793 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
794 pm_runtime_force_resume)
795 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
796 stm32_adc_core_runtime_resume,
797 stm32_adc_core_runtime_idle)
798 };
799
800 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
801 .regs = &stm32f4_adc_common_regs,
802 .clk_sel = stm32f4_adc_clk_sel,
803 .max_clk_rate_hz = 36000000,
804 .num_irqs = 1,
805 };
806
807 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
808 .regs = &stm32h7_adc_common_regs,
809 .clk_sel = stm32h7_adc_clk_sel,
810 .max_clk_rate_hz = 36000000,
811 .has_syscfg = HAS_VBOOSTER,
812 .num_irqs = 1,
813 };
814
815 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
816 .regs = &stm32h7_adc_common_regs,
817 .clk_sel = stm32h7_adc_clk_sel,
818 .max_clk_rate_hz = 36000000,
819 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
820 .num_irqs = 2,
821 };
822
823 static const struct of_device_id stm32_adc_of_match[] = {
824 {
825 .compatible = "st,stm32f4-adc-core",
826 .data = (void *)&stm32f4_adc_priv_cfg
827 }, {
828 .compatible = "st,stm32h7-adc-core",
829 .data = (void *)&stm32h7_adc_priv_cfg
830 }, {
831 .compatible = "st,stm32mp1-adc-core",
832 .data = (void *)&stm32mp1_adc_priv_cfg
833 }, {
834 },
835 };
836 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
837
838 static struct platform_driver stm32_adc_driver = {
839 .probe = stm32_adc_probe,
840 .remove = stm32_adc_remove,
841 .driver = {
842 .name = "stm32-adc-core",
843 .of_match_table = stm32_adc_of_match,
844 .pm = &stm32_adc_core_pm_ops,
845 },
846 };
847 module_platform_driver(stm32_adc_driver);
848
849 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
850 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
851 MODULE_LICENSE("GPL v2");
852 MODULE_ALIAS("platform:stm32-adc-core");
853