1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADS1015 - Texas Instruments Analog-to-Digital Converter
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 *
7 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
8 * * 0x48 - ADDR connected to Ground
9 * * 0x49 - ADDR connected to Vdd
10 * * 0x4A - ADDR connected to SDA
11 * * 0x4B - ADDR connected to SCL
12 */
13
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/mutex.h>
22 #include <linux/delay.h>
23
24 #include <linux/platform_data/ads1015.h>
25
26 #include <linux/iio/iio.h>
27 #include <linux/iio/types.h>
28 #include <linux/iio/sysfs.h>
29 #include <linux/iio/events.h>
30 #include <linux/iio/buffer.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/trigger_consumer.h>
33
34 #define ADS1015_DRV_NAME "ads1015"
35
36 #define ADS1015_CONV_REG 0x00
37 #define ADS1015_CFG_REG 0x01
38 #define ADS1015_LO_THRESH_REG 0x02
39 #define ADS1015_HI_THRESH_REG 0x03
40
41 #define ADS1015_CFG_COMP_QUE_SHIFT 0
42 #define ADS1015_CFG_COMP_LAT_SHIFT 2
43 #define ADS1015_CFG_COMP_POL_SHIFT 3
44 #define ADS1015_CFG_COMP_MODE_SHIFT 4
45 #define ADS1015_CFG_DR_SHIFT 5
46 #define ADS1015_CFG_MOD_SHIFT 8
47 #define ADS1015_CFG_PGA_SHIFT 9
48 #define ADS1015_CFG_MUX_SHIFT 12
49
50 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
51 #define ADS1015_CFG_COMP_LAT_MASK BIT(2)
52 #define ADS1015_CFG_COMP_POL_MASK BIT(3)
53 #define ADS1015_CFG_COMP_MODE_MASK BIT(4)
54 #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
55 #define ADS1015_CFG_MOD_MASK BIT(8)
56 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
57 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
58
59 /* Comparator queue and disable field */
60 #define ADS1015_CFG_COMP_DISABLE 3
61
62 /* Comparator polarity field */
63 #define ADS1015_CFG_COMP_POL_LOW 0
64 #define ADS1015_CFG_COMP_POL_HIGH 1
65
66 /* Comparator mode field */
67 #define ADS1015_CFG_COMP_MODE_TRAD 0
68 #define ADS1015_CFG_COMP_MODE_WINDOW 1
69
70 /* device operating modes */
71 #define ADS1015_CONTINUOUS 0
72 #define ADS1015_SINGLESHOT 1
73
74 #define ADS1015_SLEEP_DELAY_MS 2000
75 #define ADS1015_DEFAULT_PGA 2
76 #define ADS1015_DEFAULT_DATA_RATE 4
77 #define ADS1015_DEFAULT_CHAN 0
78
79 enum chip_ids {
80 ADS1015,
81 ADS1115,
82 };
83
84 enum ads1015_channels {
85 ADS1015_AIN0_AIN1 = 0,
86 ADS1015_AIN0_AIN3,
87 ADS1015_AIN1_AIN3,
88 ADS1015_AIN2_AIN3,
89 ADS1015_AIN0,
90 ADS1015_AIN1,
91 ADS1015_AIN2,
92 ADS1015_AIN3,
93 ADS1015_TIMESTAMP,
94 };
95
96 static const unsigned int ads1015_data_rate[] = {
97 128, 250, 490, 920, 1600, 2400, 3300, 3300
98 };
99
100 static const unsigned int ads1115_data_rate[] = {
101 8, 16, 32, 64, 128, 250, 475, 860
102 };
103
104 /*
105 * Translation from PGA bits to full-scale positive and negative input voltage
106 * range in mV
107 */
108 static int ads1015_fullscale_range[] = {
109 6144, 4096, 2048, 1024, 512, 256, 256, 256
110 };
111
112 /*
113 * Translation from COMP_QUE field value to the number of successive readings
114 * exceed the threshold values before an interrupt is generated
115 */
116 static const int ads1015_comp_queue[] = { 1, 2, 4 };
117
118 static const struct iio_event_spec ads1015_events[] = {
119 {
120 .type = IIO_EV_TYPE_THRESH,
121 .dir = IIO_EV_DIR_RISING,
122 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
123 BIT(IIO_EV_INFO_ENABLE),
124 }, {
125 .type = IIO_EV_TYPE_THRESH,
126 .dir = IIO_EV_DIR_FALLING,
127 .mask_separate = BIT(IIO_EV_INFO_VALUE),
128 }, {
129 .type = IIO_EV_TYPE_THRESH,
130 .dir = IIO_EV_DIR_EITHER,
131 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
132 BIT(IIO_EV_INFO_PERIOD),
133 },
134 };
135
136 #define ADS1015_V_CHAN(_chan, _addr) { \
137 .type = IIO_VOLTAGE, \
138 .indexed = 1, \
139 .address = _addr, \
140 .channel = _chan, \
141 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
142 BIT(IIO_CHAN_INFO_SCALE) | \
143 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
144 .scan_index = _addr, \
145 .scan_type = { \
146 .sign = 's', \
147 .realbits = 12, \
148 .storagebits = 16, \
149 .shift = 4, \
150 .endianness = IIO_CPU, \
151 }, \
152 .event_spec = ads1015_events, \
153 .num_event_specs = ARRAY_SIZE(ads1015_events), \
154 .datasheet_name = "AIN"#_chan, \
155 }
156
157 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
158 .type = IIO_VOLTAGE, \
159 .differential = 1, \
160 .indexed = 1, \
161 .address = _addr, \
162 .channel = _chan, \
163 .channel2 = _chan2, \
164 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
165 BIT(IIO_CHAN_INFO_SCALE) | \
166 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
167 .scan_index = _addr, \
168 .scan_type = { \
169 .sign = 's', \
170 .realbits = 12, \
171 .storagebits = 16, \
172 .shift = 4, \
173 .endianness = IIO_CPU, \
174 }, \
175 .event_spec = ads1015_events, \
176 .num_event_specs = ARRAY_SIZE(ads1015_events), \
177 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
178 }
179
180 #define ADS1115_V_CHAN(_chan, _addr) { \
181 .type = IIO_VOLTAGE, \
182 .indexed = 1, \
183 .address = _addr, \
184 .channel = _chan, \
185 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
186 BIT(IIO_CHAN_INFO_SCALE) | \
187 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
188 .scan_index = _addr, \
189 .scan_type = { \
190 .sign = 's', \
191 .realbits = 16, \
192 .storagebits = 16, \
193 .endianness = IIO_CPU, \
194 }, \
195 .event_spec = ads1015_events, \
196 .num_event_specs = ARRAY_SIZE(ads1015_events), \
197 .datasheet_name = "AIN"#_chan, \
198 }
199
200 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
201 .type = IIO_VOLTAGE, \
202 .differential = 1, \
203 .indexed = 1, \
204 .address = _addr, \
205 .channel = _chan, \
206 .channel2 = _chan2, \
207 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
208 BIT(IIO_CHAN_INFO_SCALE) | \
209 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
210 .scan_index = _addr, \
211 .scan_type = { \
212 .sign = 's', \
213 .realbits = 16, \
214 .storagebits = 16, \
215 .endianness = IIO_CPU, \
216 }, \
217 .event_spec = ads1015_events, \
218 .num_event_specs = ARRAY_SIZE(ads1015_events), \
219 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
220 }
221
222 struct ads1015_thresh_data {
223 unsigned int comp_queue;
224 int high_thresh;
225 int low_thresh;
226 };
227
228 struct ads1015_data {
229 struct regmap *regmap;
230 /*
231 * Protects ADC ops, e.g: concurrent sysfs/buffered
232 * data reads, configuration updates
233 */
234 struct mutex lock;
235 struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
236
237 unsigned int event_channel;
238 unsigned int comp_mode;
239 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
240
241 unsigned int *data_rate;
242 /*
243 * Set to true when the ADC is switched to the continuous-conversion
244 * mode and exits from a power-down state. This flag is used to avoid
245 * getting the stale result from the conversion register.
246 */
247 bool conv_invalid;
248 };
249
ads1015_event_channel_enabled(struct ads1015_data * data)250 static bool ads1015_event_channel_enabled(struct ads1015_data *data)
251 {
252 return (data->event_channel != ADS1015_CHANNELS);
253 }
254
ads1015_event_channel_enable(struct ads1015_data * data,int chan,int comp_mode)255 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
256 int comp_mode)
257 {
258 WARN_ON(ads1015_event_channel_enabled(data));
259
260 data->event_channel = chan;
261 data->comp_mode = comp_mode;
262 }
263
ads1015_event_channel_disable(struct ads1015_data * data,int chan)264 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
265 {
266 data->event_channel = ADS1015_CHANNELS;
267 }
268
ads1015_is_writeable_reg(struct device * dev,unsigned int reg)269 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
270 {
271 switch (reg) {
272 case ADS1015_CFG_REG:
273 case ADS1015_LO_THRESH_REG:
274 case ADS1015_HI_THRESH_REG:
275 return true;
276 default:
277 return false;
278 }
279 }
280
281 static const struct regmap_config ads1015_regmap_config = {
282 .reg_bits = 8,
283 .val_bits = 16,
284 .max_register = ADS1015_HI_THRESH_REG,
285 .writeable_reg = ads1015_is_writeable_reg,
286 };
287
288 static const struct iio_chan_spec ads1015_channels[] = {
289 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
290 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
291 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
292 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
293 ADS1015_V_CHAN(0, ADS1015_AIN0),
294 ADS1015_V_CHAN(1, ADS1015_AIN1),
295 ADS1015_V_CHAN(2, ADS1015_AIN2),
296 ADS1015_V_CHAN(3, ADS1015_AIN3),
297 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
298 };
299
300 static const struct iio_chan_spec ads1115_channels[] = {
301 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
302 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
303 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
304 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
305 ADS1115_V_CHAN(0, ADS1015_AIN0),
306 ADS1115_V_CHAN(1, ADS1015_AIN1),
307 ADS1115_V_CHAN(2, ADS1015_AIN2),
308 ADS1115_V_CHAN(3, ADS1015_AIN3),
309 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
310 };
311
312 #ifdef CONFIG_PM
ads1015_set_power_state(struct ads1015_data * data,bool on)313 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
314 {
315 int ret;
316 struct device *dev = regmap_get_device(data->regmap);
317
318 if (on) {
319 ret = pm_runtime_get_sync(dev);
320 if (ret < 0)
321 pm_runtime_put_noidle(dev);
322 } else {
323 pm_runtime_mark_last_busy(dev);
324 ret = pm_runtime_put_autosuspend(dev);
325 }
326
327 return ret < 0 ? ret : 0;
328 }
329
330 #else /* !CONFIG_PM */
331
ads1015_set_power_state(struct ads1015_data * data,bool on)332 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
333 {
334 return 0;
335 }
336
337 #endif /* !CONFIG_PM */
338
339 static
ads1015_get_adc_result(struct ads1015_data * data,int chan,int * val)340 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
341 {
342 int ret, pga, dr, dr_old, conv_time;
343 unsigned int old, mask, cfg;
344
345 if (chan < 0 || chan >= ADS1015_CHANNELS)
346 return -EINVAL;
347
348 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
349 if (ret)
350 return ret;
351
352 pga = data->channel_data[chan].pga;
353 dr = data->channel_data[chan].data_rate;
354 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
355 ADS1015_CFG_DR_MASK;
356 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
357 dr << ADS1015_CFG_DR_SHIFT;
358
359 if (ads1015_event_channel_enabled(data)) {
360 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
361 cfg |= data->thresh_data[chan].comp_queue <<
362 ADS1015_CFG_COMP_QUE_SHIFT |
363 data->comp_mode <<
364 ADS1015_CFG_COMP_MODE_SHIFT;
365 }
366
367 cfg = (old & ~mask) | (cfg & mask);
368 if (old != cfg) {
369 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
370 if (ret)
371 return ret;
372 data->conv_invalid = true;
373 }
374 if (data->conv_invalid) {
375 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
376 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
377 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
378 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
379 usleep_range(conv_time, conv_time + 1);
380 data->conv_invalid = false;
381 }
382
383 return regmap_read(data->regmap, ADS1015_CONV_REG, val);
384 }
385
ads1015_trigger_handler(int irq,void * p)386 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
387 {
388 struct iio_poll_func *pf = p;
389 struct iio_dev *indio_dev = pf->indio_dev;
390 struct ads1015_data *data = iio_priv(indio_dev);
391 /* Ensure natural alignment of timestamp */
392 struct {
393 s16 chan;
394 s64 timestamp __aligned(8);
395 } scan;
396 int chan, ret, res;
397
398 memset(&scan, 0, sizeof(scan));
399
400 mutex_lock(&data->lock);
401 chan = find_first_bit(indio_dev->active_scan_mask,
402 indio_dev->masklength);
403 ret = ads1015_get_adc_result(data, chan, &res);
404 if (ret < 0) {
405 mutex_unlock(&data->lock);
406 goto err;
407 }
408
409 scan.chan = res;
410 mutex_unlock(&data->lock);
411
412 iio_push_to_buffers_with_timestamp(indio_dev, &scan,
413 iio_get_time_ns(indio_dev));
414
415 err:
416 iio_trigger_notify_done(indio_dev->trig);
417
418 return IRQ_HANDLED;
419 }
420
ads1015_set_scale(struct ads1015_data * data,struct iio_chan_spec const * chan,int scale,int uscale)421 static int ads1015_set_scale(struct ads1015_data *data,
422 struct iio_chan_spec const *chan,
423 int scale, int uscale)
424 {
425 int i;
426 int fullscale = div_s64((scale * 1000000LL + uscale) <<
427 (chan->scan_type.realbits - 1), 1000000);
428
429 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
430 if (ads1015_fullscale_range[i] == fullscale) {
431 data->channel_data[chan->address].pga = i;
432 return 0;
433 }
434 }
435
436 return -EINVAL;
437 }
438
ads1015_set_data_rate(struct ads1015_data * data,int chan,int rate)439 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
440 {
441 int i;
442
443 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
444 if (data->data_rate[i] == rate) {
445 data->channel_data[chan].data_rate = i;
446 return 0;
447 }
448 }
449
450 return -EINVAL;
451 }
452
ads1015_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)453 static int ads1015_read_raw(struct iio_dev *indio_dev,
454 struct iio_chan_spec const *chan, int *val,
455 int *val2, long mask)
456 {
457 int ret, idx;
458 struct ads1015_data *data = iio_priv(indio_dev);
459
460 mutex_lock(&data->lock);
461 switch (mask) {
462 case IIO_CHAN_INFO_RAW: {
463 int shift = chan->scan_type.shift;
464
465 ret = iio_device_claim_direct_mode(indio_dev);
466 if (ret)
467 break;
468
469 if (ads1015_event_channel_enabled(data) &&
470 data->event_channel != chan->address) {
471 ret = -EBUSY;
472 goto release_direct;
473 }
474
475 ret = ads1015_set_power_state(data, true);
476 if (ret < 0)
477 goto release_direct;
478
479 ret = ads1015_get_adc_result(data, chan->address, val);
480 if (ret < 0) {
481 ads1015_set_power_state(data, false);
482 goto release_direct;
483 }
484
485 *val = sign_extend32(*val >> shift, 15 - shift);
486
487 ret = ads1015_set_power_state(data, false);
488 if (ret < 0)
489 goto release_direct;
490
491 ret = IIO_VAL_INT;
492 release_direct:
493 iio_device_release_direct_mode(indio_dev);
494 break;
495 }
496 case IIO_CHAN_INFO_SCALE:
497 idx = data->channel_data[chan->address].pga;
498 *val = ads1015_fullscale_range[idx];
499 *val2 = chan->scan_type.realbits - 1;
500 ret = IIO_VAL_FRACTIONAL_LOG2;
501 break;
502 case IIO_CHAN_INFO_SAMP_FREQ:
503 idx = data->channel_data[chan->address].data_rate;
504 *val = data->data_rate[idx];
505 ret = IIO_VAL_INT;
506 break;
507 default:
508 ret = -EINVAL;
509 break;
510 }
511 mutex_unlock(&data->lock);
512
513 return ret;
514 }
515
ads1015_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)516 static int ads1015_write_raw(struct iio_dev *indio_dev,
517 struct iio_chan_spec const *chan, int val,
518 int val2, long mask)
519 {
520 struct ads1015_data *data = iio_priv(indio_dev);
521 int ret;
522
523 mutex_lock(&data->lock);
524 switch (mask) {
525 case IIO_CHAN_INFO_SCALE:
526 ret = ads1015_set_scale(data, chan, val, val2);
527 break;
528 case IIO_CHAN_INFO_SAMP_FREQ:
529 ret = ads1015_set_data_rate(data, chan->address, val);
530 break;
531 default:
532 ret = -EINVAL;
533 break;
534 }
535 mutex_unlock(&data->lock);
536
537 return ret;
538 }
539
ads1015_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)540 static int ads1015_read_event(struct iio_dev *indio_dev,
541 const struct iio_chan_spec *chan, enum iio_event_type type,
542 enum iio_event_direction dir, enum iio_event_info info, int *val,
543 int *val2)
544 {
545 struct ads1015_data *data = iio_priv(indio_dev);
546 int ret;
547 unsigned int comp_queue;
548 int period;
549 int dr;
550
551 mutex_lock(&data->lock);
552
553 switch (info) {
554 case IIO_EV_INFO_VALUE:
555 *val = (dir == IIO_EV_DIR_RISING) ?
556 data->thresh_data[chan->address].high_thresh :
557 data->thresh_data[chan->address].low_thresh;
558 ret = IIO_VAL_INT;
559 break;
560 case IIO_EV_INFO_PERIOD:
561 dr = data->channel_data[chan->address].data_rate;
562 comp_queue = data->thresh_data[chan->address].comp_queue;
563 period = ads1015_comp_queue[comp_queue] *
564 USEC_PER_SEC / data->data_rate[dr];
565
566 *val = period / USEC_PER_SEC;
567 *val2 = period % USEC_PER_SEC;
568 ret = IIO_VAL_INT_PLUS_MICRO;
569 break;
570 default:
571 ret = -EINVAL;
572 break;
573 }
574
575 mutex_unlock(&data->lock);
576
577 return ret;
578 }
579
ads1015_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)580 static int ads1015_write_event(struct iio_dev *indio_dev,
581 const struct iio_chan_spec *chan, enum iio_event_type type,
582 enum iio_event_direction dir, enum iio_event_info info, int val,
583 int val2)
584 {
585 struct ads1015_data *data = iio_priv(indio_dev);
586 int realbits = chan->scan_type.realbits;
587 int ret = 0;
588 long long period;
589 int i;
590 int dr;
591
592 mutex_lock(&data->lock);
593
594 switch (info) {
595 case IIO_EV_INFO_VALUE:
596 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
597 ret = -EINVAL;
598 break;
599 }
600 if (dir == IIO_EV_DIR_RISING)
601 data->thresh_data[chan->address].high_thresh = val;
602 else
603 data->thresh_data[chan->address].low_thresh = val;
604 break;
605 case IIO_EV_INFO_PERIOD:
606 dr = data->channel_data[chan->address].data_rate;
607 period = val * USEC_PER_SEC + val2;
608
609 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
610 if (period <= ads1015_comp_queue[i] *
611 USEC_PER_SEC / data->data_rate[dr])
612 break;
613 }
614 data->thresh_data[chan->address].comp_queue = i;
615 break;
616 default:
617 ret = -EINVAL;
618 break;
619 }
620
621 mutex_unlock(&data->lock);
622
623 return ret;
624 }
625
ads1015_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)626 static int ads1015_read_event_config(struct iio_dev *indio_dev,
627 const struct iio_chan_spec *chan, enum iio_event_type type,
628 enum iio_event_direction dir)
629 {
630 struct ads1015_data *data = iio_priv(indio_dev);
631 int ret = 0;
632
633 mutex_lock(&data->lock);
634 if (data->event_channel == chan->address) {
635 switch (dir) {
636 case IIO_EV_DIR_RISING:
637 ret = 1;
638 break;
639 case IIO_EV_DIR_EITHER:
640 ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
641 break;
642 default:
643 ret = -EINVAL;
644 break;
645 }
646 }
647 mutex_unlock(&data->lock);
648
649 return ret;
650 }
651
ads1015_enable_event_config(struct ads1015_data * data,const struct iio_chan_spec * chan,int comp_mode)652 static int ads1015_enable_event_config(struct ads1015_data *data,
653 const struct iio_chan_spec *chan, int comp_mode)
654 {
655 int low_thresh = data->thresh_data[chan->address].low_thresh;
656 int high_thresh = data->thresh_data[chan->address].high_thresh;
657 int ret;
658 unsigned int val;
659
660 if (ads1015_event_channel_enabled(data)) {
661 if (data->event_channel != chan->address ||
662 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
663 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
664 return -EBUSY;
665
666 return 0;
667 }
668
669 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
670 low_thresh = max(-1 << (chan->scan_type.realbits - 1),
671 high_thresh - 1);
672 }
673 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
674 low_thresh << chan->scan_type.shift);
675 if (ret)
676 return ret;
677
678 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
679 high_thresh << chan->scan_type.shift);
680 if (ret)
681 return ret;
682
683 ret = ads1015_set_power_state(data, true);
684 if (ret < 0)
685 return ret;
686
687 ads1015_event_channel_enable(data, chan->address, comp_mode);
688
689 ret = ads1015_get_adc_result(data, chan->address, &val);
690 if (ret) {
691 ads1015_event_channel_disable(data, chan->address);
692 ads1015_set_power_state(data, false);
693 }
694
695 return ret;
696 }
697
ads1015_disable_event_config(struct ads1015_data * data,const struct iio_chan_spec * chan,int comp_mode)698 static int ads1015_disable_event_config(struct ads1015_data *data,
699 const struct iio_chan_spec *chan, int comp_mode)
700 {
701 int ret;
702
703 if (!ads1015_event_channel_enabled(data))
704 return 0;
705
706 if (data->event_channel != chan->address)
707 return 0;
708
709 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
710 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
711 return 0;
712
713 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
714 ADS1015_CFG_COMP_QUE_MASK,
715 ADS1015_CFG_COMP_DISABLE <<
716 ADS1015_CFG_COMP_QUE_SHIFT);
717 if (ret)
718 return ret;
719
720 ads1015_event_channel_disable(data, chan->address);
721
722 return ads1015_set_power_state(data, false);
723 }
724
ads1015_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)725 static int ads1015_write_event_config(struct iio_dev *indio_dev,
726 const struct iio_chan_spec *chan, enum iio_event_type type,
727 enum iio_event_direction dir, int state)
728 {
729 struct ads1015_data *data = iio_priv(indio_dev);
730 int ret;
731 int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
732 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
733
734 mutex_lock(&data->lock);
735
736 /* Prevent from enabling both buffer and event at a time */
737 ret = iio_device_claim_direct_mode(indio_dev);
738 if (ret) {
739 mutex_unlock(&data->lock);
740 return ret;
741 }
742
743 if (state)
744 ret = ads1015_enable_event_config(data, chan, comp_mode);
745 else
746 ret = ads1015_disable_event_config(data, chan, comp_mode);
747
748 iio_device_release_direct_mode(indio_dev);
749 mutex_unlock(&data->lock);
750
751 return ret;
752 }
753
ads1015_event_handler(int irq,void * priv)754 static irqreturn_t ads1015_event_handler(int irq, void *priv)
755 {
756 struct iio_dev *indio_dev = priv;
757 struct ads1015_data *data = iio_priv(indio_dev);
758 int val;
759 int ret;
760
761 /* Clear the latched ALERT/RDY pin */
762 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
763 if (ret)
764 return IRQ_HANDLED;
765
766 if (ads1015_event_channel_enabled(data)) {
767 enum iio_event_direction dir;
768 u64 code;
769
770 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
771 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
772 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
773 IIO_EV_TYPE_THRESH, dir);
774 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
775 }
776
777 return IRQ_HANDLED;
778 }
779
ads1015_buffer_preenable(struct iio_dev * indio_dev)780 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
781 {
782 struct ads1015_data *data = iio_priv(indio_dev);
783
784 /* Prevent from enabling both buffer and event at a time */
785 if (ads1015_event_channel_enabled(data))
786 return -EBUSY;
787
788 return ads1015_set_power_state(iio_priv(indio_dev), true);
789 }
790
ads1015_buffer_postdisable(struct iio_dev * indio_dev)791 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
792 {
793 return ads1015_set_power_state(iio_priv(indio_dev), false);
794 }
795
796 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
797 .preenable = ads1015_buffer_preenable,
798 .postenable = iio_triggered_buffer_postenable,
799 .predisable = iio_triggered_buffer_predisable,
800 .postdisable = ads1015_buffer_postdisable,
801 .validate_scan_mask = &iio_validate_scan_mask_onehot,
802 };
803
804 static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
805 "3 2 1 0.5 0.25 0.125");
806 static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
807 "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
808
809 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
810 sampling_frequency_available, "128 250 490 920 1600 2400 3300");
811 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
812 sampling_frequency_available, "8 16 32 64 128 250 475 860");
813
814 static struct attribute *ads1015_attributes[] = {
815 &iio_const_attr_ads1015_scale_available.dev_attr.attr,
816 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
817 NULL,
818 };
819
820 static const struct attribute_group ads1015_attribute_group = {
821 .attrs = ads1015_attributes,
822 };
823
824 static struct attribute *ads1115_attributes[] = {
825 &iio_const_attr_ads1115_scale_available.dev_attr.attr,
826 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
827 NULL,
828 };
829
830 static const struct attribute_group ads1115_attribute_group = {
831 .attrs = ads1115_attributes,
832 };
833
834 static const struct iio_info ads1015_info = {
835 .read_raw = ads1015_read_raw,
836 .write_raw = ads1015_write_raw,
837 .read_event_value = ads1015_read_event,
838 .write_event_value = ads1015_write_event,
839 .read_event_config = ads1015_read_event_config,
840 .write_event_config = ads1015_write_event_config,
841 .attrs = &ads1015_attribute_group,
842 };
843
844 static const struct iio_info ads1115_info = {
845 .read_raw = ads1015_read_raw,
846 .write_raw = ads1015_write_raw,
847 .read_event_value = ads1015_read_event,
848 .write_event_value = ads1015_write_event,
849 .read_event_config = ads1015_read_event_config,
850 .write_event_config = ads1015_write_event_config,
851 .attrs = &ads1115_attribute_group,
852 };
853
854 #ifdef CONFIG_OF
ads1015_get_channels_config_of(struct i2c_client * client)855 static int ads1015_get_channels_config_of(struct i2c_client *client)
856 {
857 struct iio_dev *indio_dev = i2c_get_clientdata(client);
858 struct ads1015_data *data = iio_priv(indio_dev);
859 struct device_node *node;
860
861 if (!client->dev.of_node ||
862 !of_get_next_child(client->dev.of_node, NULL))
863 return -EINVAL;
864
865 for_each_child_of_node(client->dev.of_node, node) {
866 u32 pval;
867 unsigned int channel;
868 unsigned int pga = ADS1015_DEFAULT_PGA;
869 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
870
871 if (of_property_read_u32(node, "reg", &pval)) {
872 dev_err(&client->dev, "invalid reg on %pOF\n",
873 node);
874 continue;
875 }
876
877 channel = pval;
878 if (channel >= ADS1015_CHANNELS) {
879 dev_err(&client->dev,
880 "invalid channel index %d on %pOF\n",
881 channel, node);
882 continue;
883 }
884
885 if (!of_property_read_u32(node, "ti,gain", &pval)) {
886 pga = pval;
887 if (pga > 6) {
888 dev_err(&client->dev, "invalid gain on %pOF\n",
889 node);
890 of_node_put(node);
891 return -EINVAL;
892 }
893 }
894
895 if (!of_property_read_u32(node, "ti,datarate", &pval)) {
896 data_rate = pval;
897 if (data_rate > 7) {
898 dev_err(&client->dev,
899 "invalid data_rate on %pOF\n",
900 node);
901 of_node_put(node);
902 return -EINVAL;
903 }
904 }
905
906 data->channel_data[channel].pga = pga;
907 data->channel_data[channel].data_rate = data_rate;
908 }
909
910 return 0;
911 }
912 #endif
913
ads1015_get_channels_config(struct i2c_client * client)914 static void ads1015_get_channels_config(struct i2c_client *client)
915 {
916 unsigned int k;
917
918 struct iio_dev *indio_dev = i2c_get_clientdata(client);
919 struct ads1015_data *data = iio_priv(indio_dev);
920 struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
921
922 /* prefer platform data */
923 if (pdata) {
924 memcpy(data->channel_data, pdata->channel_data,
925 sizeof(data->channel_data));
926 return;
927 }
928
929 #ifdef CONFIG_OF
930 if (!ads1015_get_channels_config_of(client))
931 return;
932 #endif
933 /* fallback on default configuration */
934 for (k = 0; k < ADS1015_CHANNELS; ++k) {
935 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
936 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
937 }
938 }
939
ads1015_set_conv_mode(struct ads1015_data * data,int mode)940 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
941 {
942 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
943 ADS1015_CFG_MOD_MASK,
944 mode << ADS1015_CFG_MOD_SHIFT);
945 }
946
ads1015_probe(struct i2c_client * client,const struct i2c_device_id * id)947 static int ads1015_probe(struct i2c_client *client,
948 const struct i2c_device_id *id)
949 {
950 struct iio_dev *indio_dev;
951 struct ads1015_data *data;
952 int ret;
953 enum chip_ids chip;
954 int i;
955
956 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
957 if (!indio_dev)
958 return -ENOMEM;
959
960 data = iio_priv(indio_dev);
961 i2c_set_clientdata(client, indio_dev);
962
963 mutex_init(&data->lock);
964
965 indio_dev->dev.parent = &client->dev;
966 indio_dev->dev.of_node = client->dev.of_node;
967 indio_dev->name = ADS1015_DRV_NAME;
968 indio_dev->modes = INDIO_DIRECT_MODE;
969
970 if (client->dev.of_node)
971 chip = (enum chip_ids)of_device_get_match_data(&client->dev);
972 else
973 chip = id->driver_data;
974 switch (chip) {
975 case ADS1015:
976 indio_dev->channels = ads1015_channels;
977 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
978 indio_dev->info = &ads1015_info;
979 data->data_rate = (unsigned int *) &ads1015_data_rate;
980 break;
981 case ADS1115:
982 indio_dev->channels = ads1115_channels;
983 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
984 indio_dev->info = &ads1115_info;
985 data->data_rate = (unsigned int *) &ads1115_data_rate;
986 break;
987 }
988
989 data->event_channel = ADS1015_CHANNELS;
990 /*
991 * Set default lower and upper threshold to min and max value
992 * respectively.
993 */
994 for (i = 0; i < ADS1015_CHANNELS; i++) {
995 int realbits = indio_dev->channels[i].scan_type.realbits;
996
997 data->thresh_data[i].low_thresh = -1 << (realbits - 1);
998 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
999 }
1000
1001 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
1002 ads1015_get_channels_config(client);
1003
1004 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
1005 if (IS_ERR(data->regmap)) {
1006 dev_err(&client->dev, "Failed to allocate register map\n");
1007 return PTR_ERR(data->regmap);
1008 }
1009
1010 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1011 ads1015_trigger_handler,
1012 &ads1015_buffer_setup_ops);
1013 if (ret < 0) {
1014 dev_err(&client->dev, "iio triggered buffer setup failed\n");
1015 return ret;
1016 }
1017
1018 if (client->irq) {
1019 unsigned long irq_trig =
1020 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1021 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
1022 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
1023 unsigned int cfg_comp =
1024 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1025 1 << ADS1015_CFG_COMP_LAT_SHIFT;
1026
1027 switch (irq_trig) {
1028 case IRQF_TRIGGER_LOW:
1029 cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1030 ADS1015_CFG_COMP_POL_SHIFT;
1031 break;
1032 case IRQF_TRIGGER_HIGH:
1033 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1034 ADS1015_CFG_COMP_POL_SHIFT;
1035 break;
1036 default:
1037 return -EINVAL;
1038 }
1039
1040 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1041 cfg_comp_mask, cfg_comp);
1042 if (ret)
1043 return ret;
1044
1045 ret = devm_request_threaded_irq(&client->dev, client->irq,
1046 NULL, ads1015_event_handler,
1047 irq_trig | IRQF_ONESHOT,
1048 client->name, indio_dev);
1049 if (ret)
1050 return ret;
1051 }
1052
1053 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1054 if (ret)
1055 return ret;
1056
1057 data->conv_invalid = true;
1058
1059 ret = pm_runtime_set_active(&client->dev);
1060 if (ret)
1061 return ret;
1062 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1063 pm_runtime_use_autosuspend(&client->dev);
1064 pm_runtime_enable(&client->dev);
1065
1066 ret = iio_device_register(indio_dev);
1067 if (ret < 0) {
1068 dev_err(&client->dev, "Failed to register IIO device\n");
1069 return ret;
1070 }
1071
1072 return 0;
1073 }
1074
ads1015_remove(struct i2c_client * client)1075 static int ads1015_remove(struct i2c_client *client)
1076 {
1077 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1078 struct ads1015_data *data = iio_priv(indio_dev);
1079
1080 iio_device_unregister(indio_dev);
1081
1082 pm_runtime_disable(&client->dev);
1083 pm_runtime_set_suspended(&client->dev);
1084 pm_runtime_put_noidle(&client->dev);
1085
1086 /* power down single shot mode */
1087 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1088 }
1089
1090 #ifdef CONFIG_PM
ads1015_runtime_suspend(struct device * dev)1091 static int ads1015_runtime_suspend(struct device *dev)
1092 {
1093 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1094 struct ads1015_data *data = iio_priv(indio_dev);
1095
1096 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1097 }
1098
ads1015_runtime_resume(struct device * dev)1099 static int ads1015_runtime_resume(struct device *dev)
1100 {
1101 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1102 struct ads1015_data *data = iio_priv(indio_dev);
1103 int ret;
1104
1105 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1106 if (!ret)
1107 data->conv_invalid = true;
1108
1109 return ret;
1110 }
1111 #endif
1112
1113 static const struct dev_pm_ops ads1015_pm_ops = {
1114 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1115 ads1015_runtime_resume, NULL)
1116 };
1117
1118 static const struct i2c_device_id ads1015_id[] = {
1119 {"ads1015", ADS1015},
1120 {"ads1115", ADS1115},
1121 {}
1122 };
1123 MODULE_DEVICE_TABLE(i2c, ads1015_id);
1124
1125 static const struct of_device_id ads1015_of_match[] = {
1126 {
1127 .compatible = "ti,ads1015",
1128 .data = (void *)ADS1015
1129 },
1130 {
1131 .compatible = "ti,ads1115",
1132 .data = (void *)ADS1115
1133 },
1134 {}
1135 };
1136 MODULE_DEVICE_TABLE(of, ads1015_of_match);
1137
1138 static struct i2c_driver ads1015_driver = {
1139 .driver = {
1140 .name = ADS1015_DRV_NAME,
1141 .of_match_table = ads1015_of_match,
1142 .pm = &ads1015_pm_ops,
1143 },
1144 .probe = ads1015_probe,
1145 .remove = ads1015_remove,
1146 .id_table = ads1015_id,
1147 };
1148
1149 module_i2c_driver(ads1015_driver);
1150
1151 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1152 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1153 MODULE_LICENSE("GPL v2");
1154