1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * intel-pasid.c - PASID idr, table and entry manipulation
4 *
5 * Copyright (C) 2018 Intel Corporation
6 *
7 * Author: Lu Baolu <baolu.lu@linux.intel.com>
8 */
9
10 #define pr_fmt(fmt) "DMAR: " fmt
11
12 #include <linux/bitops.h>
13 #include <linux/cpufeature.h>
14 #include <linux/dmar.h>
15 #include <linux/intel-iommu.h>
16 #include <linux/iommu.h>
17 #include <linux/memory.h>
18 #include <linux/pci.h>
19 #include <linux/pci-ats.h>
20 #include <linux/spinlock.h>
21
22 #include "intel-pasid.h"
23
24 /*
25 * Intel IOMMU system wide PASID name space:
26 */
27 static DEFINE_SPINLOCK(pasid_lock);
28 u32 intel_pasid_max_id = PASID_MAX;
29 static DEFINE_IDR(pasid_idr);
30
intel_pasid_alloc_id(void * ptr,int start,int end,gfp_t gfp)31 int intel_pasid_alloc_id(void *ptr, int start, int end, gfp_t gfp)
32 {
33 int ret, min, max;
34
35 min = max_t(int, start, PASID_MIN);
36 max = min_t(int, end, intel_pasid_max_id);
37
38 WARN_ON(in_interrupt());
39 idr_preload(gfp);
40 spin_lock(&pasid_lock);
41 ret = idr_alloc(&pasid_idr, ptr, min, max, GFP_ATOMIC);
42 spin_unlock(&pasid_lock);
43 idr_preload_end();
44
45 return ret;
46 }
47
intel_pasid_free_id(int pasid)48 void intel_pasid_free_id(int pasid)
49 {
50 spin_lock(&pasid_lock);
51 idr_remove(&pasid_idr, pasid);
52 spin_unlock(&pasid_lock);
53 }
54
intel_pasid_lookup_id(int pasid)55 void *intel_pasid_lookup_id(int pasid)
56 {
57 void *p;
58
59 spin_lock(&pasid_lock);
60 p = idr_find(&pasid_idr, pasid);
61 spin_unlock(&pasid_lock);
62
63 return p;
64 }
65
66 /*
67 * Per device pasid table management:
68 */
69 static inline void
device_attach_pasid_table(struct device_domain_info * info,struct pasid_table * pasid_table)70 device_attach_pasid_table(struct device_domain_info *info,
71 struct pasid_table *pasid_table)
72 {
73 info->pasid_table = pasid_table;
74 list_add(&info->table, &pasid_table->dev);
75 }
76
77 static inline void
device_detach_pasid_table(struct device_domain_info * info,struct pasid_table * pasid_table)78 device_detach_pasid_table(struct device_domain_info *info,
79 struct pasid_table *pasid_table)
80 {
81 info->pasid_table = NULL;
82 list_del(&info->table);
83 }
84
85 struct pasid_table_opaque {
86 struct pasid_table **pasid_table;
87 int segment;
88 int bus;
89 int devfn;
90 };
91
search_pasid_table(struct device_domain_info * info,void * opaque)92 static int search_pasid_table(struct device_domain_info *info, void *opaque)
93 {
94 struct pasid_table_opaque *data = opaque;
95
96 if (info->iommu->segment == data->segment &&
97 info->bus == data->bus &&
98 info->devfn == data->devfn &&
99 info->pasid_table) {
100 *data->pasid_table = info->pasid_table;
101 return 1;
102 }
103
104 return 0;
105 }
106
get_alias_pasid_table(struct pci_dev * pdev,u16 alias,void * opaque)107 static int get_alias_pasid_table(struct pci_dev *pdev, u16 alias, void *opaque)
108 {
109 struct pasid_table_opaque *data = opaque;
110
111 data->segment = pci_domain_nr(pdev->bus);
112 data->bus = PCI_BUS_NUM(alias);
113 data->devfn = alias & 0xff;
114
115 return for_each_device_domain(&search_pasid_table, data);
116 }
117
118 /*
119 * Allocate a pasid table for @dev. It should be called in a
120 * single-thread context.
121 */
intel_pasid_alloc_table(struct device * dev)122 int intel_pasid_alloc_table(struct device *dev)
123 {
124 struct device_domain_info *info;
125 struct pasid_table *pasid_table;
126 struct pasid_table_opaque data;
127 struct page *pages;
128 int max_pasid = 0;
129 int ret, order;
130 int size;
131
132 might_sleep();
133 info = dev->archdata.iommu;
134 if (WARN_ON(!info || !dev_is_pci(dev) || info->pasid_table))
135 return -EINVAL;
136
137 /* DMA alias device already has a pasid table, use it: */
138 data.pasid_table = &pasid_table;
139 ret = pci_for_each_dma_alias(to_pci_dev(dev),
140 &get_alias_pasid_table, &data);
141 if (ret)
142 goto attach_out;
143
144 pasid_table = kzalloc(sizeof(*pasid_table), GFP_KERNEL);
145 if (!pasid_table)
146 return -ENOMEM;
147 INIT_LIST_HEAD(&pasid_table->dev);
148
149 if (info->pasid_supported)
150 max_pasid = min_t(int, pci_max_pasids(to_pci_dev(dev)),
151 intel_pasid_max_id);
152
153 size = max_pasid >> (PASID_PDE_SHIFT - 3);
154 order = size ? get_order(size) : 0;
155 pages = alloc_pages_node(info->iommu->node,
156 GFP_KERNEL | __GFP_ZERO, order);
157 if (!pages) {
158 kfree(pasid_table);
159 return -ENOMEM;
160 }
161
162 pasid_table->table = page_address(pages);
163 pasid_table->order = order;
164 pasid_table->max_pasid = 1 << (order + PAGE_SHIFT + 3);
165
166 attach_out:
167 device_attach_pasid_table(info, pasid_table);
168
169 if (!ecap_coherent(info->iommu->ecap))
170 clflush_cache_range(pasid_table->table, (1 << order) * PAGE_SIZE);
171
172 return 0;
173 }
174
intel_pasid_free_table(struct device * dev)175 void intel_pasid_free_table(struct device *dev)
176 {
177 struct device_domain_info *info;
178 struct pasid_table *pasid_table;
179 struct pasid_dir_entry *dir;
180 struct pasid_entry *table;
181 int i, max_pde;
182
183 info = dev->archdata.iommu;
184 if (!info || !dev_is_pci(dev) || !info->pasid_table)
185 return;
186
187 pasid_table = info->pasid_table;
188 device_detach_pasid_table(info, pasid_table);
189
190 if (!list_empty(&pasid_table->dev))
191 return;
192
193 /* Free scalable mode PASID directory tables: */
194 dir = pasid_table->table;
195 max_pde = pasid_table->max_pasid >> PASID_PDE_SHIFT;
196 for (i = 0; i < max_pde; i++) {
197 table = get_pasid_table_from_pde(&dir[i]);
198 free_pgtable_page(table);
199 }
200
201 free_pages((unsigned long)pasid_table->table, pasid_table->order);
202 kfree(pasid_table);
203 }
204
intel_pasid_get_table(struct device * dev)205 struct pasid_table *intel_pasid_get_table(struct device *dev)
206 {
207 struct device_domain_info *info;
208
209 info = dev->archdata.iommu;
210 if (!info)
211 return NULL;
212
213 return info->pasid_table;
214 }
215
intel_pasid_get_dev_max_id(struct device * dev)216 int intel_pasid_get_dev_max_id(struct device *dev)
217 {
218 struct device_domain_info *info;
219
220 info = dev->archdata.iommu;
221 if (!info || !info->pasid_table)
222 return 0;
223
224 return info->pasid_table->max_pasid;
225 }
226
intel_pasid_get_entry(struct device * dev,int pasid)227 struct pasid_entry *intel_pasid_get_entry(struct device *dev, int pasid)
228 {
229 struct device_domain_info *info;
230 struct pasid_table *pasid_table;
231 struct pasid_dir_entry *dir;
232 struct pasid_entry *entries;
233 int dir_index, index;
234
235 pasid_table = intel_pasid_get_table(dev);
236 if (WARN_ON(!pasid_table || pasid < 0 ||
237 pasid >= intel_pasid_get_dev_max_id(dev)))
238 return NULL;
239
240 dir = pasid_table->table;
241 info = dev->archdata.iommu;
242 dir_index = pasid >> PASID_PDE_SHIFT;
243 index = pasid & PASID_PTE_MASK;
244
245 spin_lock(&pasid_lock);
246 entries = get_pasid_table_from_pde(&dir[dir_index]);
247 if (!entries) {
248 entries = alloc_pgtable_page(info->iommu->node);
249 if (!entries) {
250 spin_unlock(&pasid_lock);
251 return NULL;
252 }
253
254 WRITE_ONCE(dir[dir_index].val,
255 (u64)virt_to_phys(entries) | PASID_PTE_PRESENT);
256 if (!ecap_coherent(info->iommu->ecap)) {
257 clflush_cache_range(entries, VTD_PAGE_SIZE);
258 clflush_cache_range(&dir[dir_index].val, sizeof(*dir));
259 }
260 }
261 spin_unlock(&pasid_lock);
262
263 return &entries[index];
264 }
265
266 /*
267 * Interfaces for PASID table entry manipulation:
268 */
pasid_clear_entry(struct pasid_entry * pe)269 static inline void pasid_clear_entry(struct pasid_entry *pe)
270 {
271 WRITE_ONCE(pe->val[0], 0);
272 WRITE_ONCE(pe->val[1], 0);
273 WRITE_ONCE(pe->val[2], 0);
274 WRITE_ONCE(pe->val[3], 0);
275 WRITE_ONCE(pe->val[4], 0);
276 WRITE_ONCE(pe->val[5], 0);
277 WRITE_ONCE(pe->val[6], 0);
278 WRITE_ONCE(pe->val[7], 0);
279 }
280
intel_pasid_clear_entry(struct device * dev,int pasid)281 static void intel_pasid_clear_entry(struct device *dev, int pasid)
282 {
283 struct pasid_entry *pe;
284
285 pe = intel_pasid_get_entry(dev, pasid);
286 if (WARN_ON(!pe))
287 return;
288
289 pasid_clear_entry(pe);
290 }
291
pasid_set_bits(u64 * ptr,u64 mask,u64 bits)292 static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits)
293 {
294 u64 old;
295
296 old = READ_ONCE(*ptr);
297 WRITE_ONCE(*ptr, (old & ~mask) | bits);
298 }
299
300 /*
301 * Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode
302 * PASID entry.
303 */
304 static inline void
pasid_set_domain_id(struct pasid_entry * pe,u64 value)305 pasid_set_domain_id(struct pasid_entry *pe, u64 value)
306 {
307 pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value);
308 }
309
310 /*
311 * Get domain ID value of a scalable mode PASID entry.
312 */
313 static inline u16
pasid_get_domain_id(struct pasid_entry * pe)314 pasid_get_domain_id(struct pasid_entry *pe)
315 {
316 return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0));
317 }
318
319 /*
320 * Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63)
321 * of a scalable mode PASID entry.
322 */
323 static inline void
pasid_set_slptr(struct pasid_entry * pe,u64 value)324 pasid_set_slptr(struct pasid_entry *pe, u64 value)
325 {
326 pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value);
327 }
328
329 /*
330 * Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID
331 * entry.
332 */
333 static inline void
pasid_set_address_width(struct pasid_entry * pe,u64 value)334 pasid_set_address_width(struct pasid_entry *pe, u64 value)
335 {
336 pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2);
337 }
338
339 /*
340 * Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8)
341 * of a scalable mode PASID entry.
342 */
343 static inline void
pasid_set_translation_type(struct pasid_entry * pe,u64 value)344 pasid_set_translation_type(struct pasid_entry *pe, u64 value)
345 {
346 pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6);
347 }
348
349 /*
350 * Enable fault processing by clearing the FPD(Fault Processing
351 * Disable) field (Bit 1) of a scalable mode PASID entry.
352 */
pasid_set_fault_enable(struct pasid_entry * pe)353 static inline void pasid_set_fault_enable(struct pasid_entry *pe)
354 {
355 pasid_set_bits(&pe->val[0], 1 << 1, 0);
356 }
357
358 /*
359 * Setup the SRE(Supervisor Request Enable) field (Bit 128) of a
360 * scalable mode PASID entry.
361 */
pasid_set_sre(struct pasid_entry * pe)362 static inline void pasid_set_sre(struct pasid_entry *pe)
363 {
364 pasid_set_bits(&pe->val[2], 1 << 0, 1);
365 }
366
367 /*
368 * Setup the P(Present) field (Bit 0) of a scalable mode PASID
369 * entry.
370 */
pasid_set_present(struct pasid_entry * pe)371 static inline void pasid_set_present(struct pasid_entry *pe)
372 {
373 pasid_set_bits(&pe->val[0], 1 << 0, 1);
374 }
375
376 /*
377 * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID
378 * entry.
379 */
pasid_set_page_snoop(struct pasid_entry * pe,bool value)380 static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)
381 {
382 pasid_set_bits(&pe->val[1], 1 << 23, value << 23);
383 }
384
385 /*
386 * Setup the First Level Page table Pointer field (Bit 140~191)
387 * of a scalable mode PASID entry.
388 */
389 static inline void
pasid_set_flptr(struct pasid_entry * pe,u64 value)390 pasid_set_flptr(struct pasid_entry *pe, u64 value)
391 {
392 pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value);
393 }
394
395 /*
396 * Setup the First Level Paging Mode field (Bit 130~131) of a
397 * scalable mode PASID entry.
398 */
399 static inline void
pasid_set_flpm(struct pasid_entry * pe,u64 value)400 pasid_set_flpm(struct pasid_entry *pe, u64 value)
401 {
402 pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2);
403 }
404
405 static void
pasid_cache_invalidation_with_pasid(struct intel_iommu * iommu,u16 did,int pasid)406 pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu,
407 u16 did, int pasid)
408 {
409 struct qi_desc desc;
410
411 desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
412 desc.qw1 = 0;
413 desc.qw2 = 0;
414 desc.qw3 = 0;
415
416 qi_submit_sync(&desc, iommu);
417 }
418
419 static void
iotlb_invalidation_with_pasid(struct intel_iommu * iommu,u16 did,u32 pasid)420 iotlb_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid)
421 {
422 struct qi_desc desc;
423
424 desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
425 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
426 desc.qw1 = 0;
427 desc.qw2 = 0;
428 desc.qw3 = 0;
429
430 qi_submit_sync(&desc, iommu);
431 }
432
433 static void
devtlb_invalidation_with_pasid(struct intel_iommu * iommu,struct device * dev,int pasid)434 devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
435 struct device *dev, int pasid)
436 {
437 struct device_domain_info *info;
438 u16 sid, qdep, pfsid;
439
440 info = dev->archdata.iommu;
441 if (!info || !info->ats_enabled)
442 return;
443
444 sid = info->bus << 8 | info->devfn;
445 qdep = info->ats_qdep;
446 pfsid = info->pfsid;
447
448 qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
449 }
450
intel_pasid_tear_down_entry(struct intel_iommu * iommu,struct device * dev,int pasid)451 void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
452 struct device *dev, int pasid)
453 {
454 struct pasid_entry *pte;
455 u16 did;
456
457 pte = intel_pasid_get_entry(dev, pasid);
458 if (WARN_ON(!pte))
459 return;
460
461 did = pasid_get_domain_id(pte);
462 intel_pasid_clear_entry(dev, pasid);
463
464 if (!ecap_coherent(iommu->ecap))
465 clflush_cache_range(pte, sizeof(*pte));
466
467 pasid_cache_invalidation_with_pasid(iommu, did, pasid);
468 iotlb_invalidation_with_pasid(iommu, did, pasid);
469
470 /* Device IOTLB doesn't need to be flushed in caching mode. */
471 if (!cap_caching_mode(iommu->cap))
472 devtlb_invalidation_with_pasid(iommu, dev, pasid);
473 }
474
475 /*
476 * Set up the scalable mode pasid table entry for first only
477 * translation type.
478 */
intel_pasid_setup_first_level(struct intel_iommu * iommu,struct device * dev,pgd_t * pgd,int pasid,u16 did,int flags)479 int intel_pasid_setup_first_level(struct intel_iommu *iommu,
480 struct device *dev, pgd_t *pgd,
481 int pasid, u16 did, int flags)
482 {
483 struct pasid_entry *pte;
484
485 if (!ecap_flts(iommu->ecap)) {
486 pr_err("No first level translation support on %s\n",
487 iommu->name);
488 return -EINVAL;
489 }
490
491 pte = intel_pasid_get_entry(dev, pasid);
492 if (WARN_ON(!pte))
493 return -EINVAL;
494
495 pasid_clear_entry(pte);
496
497 /* Setup the first level page table pointer: */
498 pasid_set_flptr(pte, (u64)__pa(pgd));
499 if (flags & PASID_FLAG_SUPERVISOR_MODE) {
500 if (!ecap_srs(iommu->ecap)) {
501 pr_err("No supervisor request support on %s\n",
502 iommu->name);
503 return -EINVAL;
504 }
505 pasid_set_sre(pte);
506 }
507
508 #ifdef CONFIG_X86
509 /* Both CPU and IOMMU paging mode need to match */
510 if (cpu_feature_enabled(X86_FEATURE_LA57)) {
511 if (cap_5lp_support(iommu->cap)) {
512 pasid_set_flpm(pte, 1);
513 } else {
514 pr_err("VT-d has no 5-level paging support for CPU\n");
515 pasid_clear_entry(pte);
516 return -EINVAL;
517 }
518 }
519 #endif /* CONFIG_X86 */
520
521 pasid_set_domain_id(pte, did);
522 pasid_set_address_width(pte, iommu->agaw);
523 pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
524
525 /* Setup Present and PASID Granular Transfer Type: */
526 pasid_set_translation_type(pte, 1);
527 pasid_set_present(pte);
528
529 if (!ecap_coherent(iommu->ecap))
530 clflush_cache_range(pte, sizeof(*pte));
531
532 if (cap_caching_mode(iommu->cap)) {
533 pasid_cache_invalidation_with_pasid(iommu, did, pasid);
534 iotlb_invalidation_with_pasid(iommu, did, pasid);
535 } else {
536 iommu_flush_write_buffer(iommu);
537 }
538
539 return 0;
540 }
541
542 /*
543 * Set up the scalable mode pasid entry for second only translation type.
544 */
intel_pasid_setup_second_level(struct intel_iommu * iommu,struct dmar_domain * domain,struct device * dev,int pasid)545 int intel_pasid_setup_second_level(struct intel_iommu *iommu,
546 struct dmar_domain *domain,
547 struct device *dev, int pasid)
548 {
549 struct pasid_entry *pte;
550 struct dma_pte *pgd;
551 u64 pgd_val;
552 int agaw;
553 u16 did;
554
555 /*
556 * If hardware advertises no support for second level
557 * translation, return directly.
558 */
559 if (!ecap_slts(iommu->ecap)) {
560 pr_err("No second level translation support on %s\n",
561 iommu->name);
562 return -EINVAL;
563 }
564
565 /*
566 * Skip top levels of page tables for iommu which has less agaw
567 * than default. Unnecessary for PT mode.
568 */
569 pgd = domain->pgd;
570 for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
571 pgd = phys_to_virt(dma_pte_addr(pgd));
572 if (!dma_pte_present(pgd)) {
573 dev_err(dev, "Invalid domain page table\n");
574 return -EINVAL;
575 }
576 }
577
578 pgd_val = virt_to_phys(pgd);
579 did = domain->iommu_did[iommu->seq_id];
580
581 pte = intel_pasid_get_entry(dev, pasid);
582 if (!pte) {
583 dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid);
584 return -ENODEV;
585 }
586
587 pasid_clear_entry(pte);
588 pasid_set_domain_id(pte, did);
589 pasid_set_slptr(pte, pgd_val);
590 pasid_set_address_width(pte, agaw);
591 pasid_set_translation_type(pte, 2);
592 pasid_set_fault_enable(pte);
593 pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
594
595 /*
596 * Since it is a second level only translation setup, we should
597 * set SRE bit as well (addresses are expected to be GPAs).
598 */
599 pasid_set_sre(pte);
600 pasid_set_present(pte);
601
602 if (!ecap_coherent(iommu->ecap))
603 clflush_cache_range(pte, sizeof(*pte));
604
605 if (cap_caching_mode(iommu->cap)) {
606 pasid_cache_invalidation_with_pasid(iommu, did, pasid);
607 iotlb_invalidation_with_pasid(iommu, did, pasid);
608 } else {
609 iommu_flush_write_buffer(iommu);
610 }
611
612 return 0;
613 }
614
615 /*
616 * Set up the scalable mode pasid entry for passthrough translation type.
617 */
intel_pasid_setup_pass_through(struct intel_iommu * iommu,struct dmar_domain * domain,struct device * dev,int pasid)618 int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
619 struct dmar_domain *domain,
620 struct device *dev, int pasid)
621 {
622 u16 did = FLPT_DEFAULT_DID;
623 struct pasid_entry *pte;
624
625 pte = intel_pasid_get_entry(dev, pasid);
626 if (!pte) {
627 dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid);
628 return -ENODEV;
629 }
630
631 pasid_clear_entry(pte);
632 pasid_set_domain_id(pte, did);
633 pasid_set_address_width(pte, iommu->agaw);
634 pasid_set_translation_type(pte, 4);
635 pasid_set_fault_enable(pte);
636 pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
637
638 /*
639 * We should set SRE bit as well since the addresses are expected
640 * to be GPAs.
641 */
642 pasid_set_sre(pte);
643 pasid_set_present(pte);
644
645 if (!ecap_coherent(iommu->ecap))
646 clflush_cache_range(pte, sizeof(*pte));
647
648 if (cap_caching_mode(iommu->cap)) {
649 pasid_cache_invalidation_with_pasid(iommu, did, pasid);
650 iotlb_invalidation_with_pasid(iommu, did, pasid);
651 } else {
652 iommu_flush_write_buffer(iommu);
653 }
654
655 return 0;
656 }
657