1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Atmel SDMMC controller driver.
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/mmc/host.h>
15 #include <linux/mmc/slot-gpio.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21
22 #include "sdhci-pltfm.h"
23
24 #define SDMMC_MC1R 0x204
25 #define SDMMC_MC1R_DDR BIT(3)
26 #define SDMMC_MC1R_FCD BIT(7)
27 #define SDMMC_CACR 0x230
28 #define SDMMC_CACR_CAPWREN BIT(0)
29 #define SDMMC_CACR_KEY (0x46 << 8)
30
31 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
32
33 struct sdhci_at91_priv {
34 struct clk *hclock;
35 struct clk *gck;
36 struct clk *mainck;
37 bool restore_needed;
38 };
39
sdhci_at91_set_force_card_detect(struct sdhci_host * host)40 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
41 {
42 u8 mc1r;
43
44 mc1r = readb(host->ioaddr + SDMMC_MC1R);
45 mc1r |= SDMMC_MC1R_FCD;
46 writeb(mc1r, host->ioaddr + SDMMC_MC1R);
47 }
48
sdhci_at91_set_clock(struct sdhci_host * host,unsigned int clock)49 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
50 {
51 u16 clk;
52 unsigned long timeout;
53
54 host->mmc->actual_clock = 0;
55
56 /*
57 * There is no requirement to disable the internal clock before
58 * changing the SD clock configuration. Moreover, disabling the
59 * internal clock, changing the configuration and re-enabling the
60 * internal clock causes some bugs. It can prevent to get the internal
61 * clock stable flag ready and an unexpected switch to the base clock
62 * when using presets.
63 */
64 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
65 clk &= SDHCI_CLOCK_INT_EN;
66 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
67
68 if (clock == 0)
69 return;
70
71 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
72
73 clk |= SDHCI_CLOCK_INT_EN;
74 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
75
76 /* Wait max 20 ms */
77 timeout = 20;
78 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
79 & SDHCI_CLOCK_INT_STABLE)) {
80 if (timeout == 0) {
81 pr_err("%s: Internal clock never stabilised.\n",
82 mmc_hostname(host->mmc));
83 return;
84 }
85 timeout--;
86 mdelay(1);
87 }
88
89 clk |= SDHCI_CLOCK_CARD_EN;
90 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
91 }
92
93 /*
94 * In this specific implementation of the SDHCI controller, the power register
95 * needs to have a valid voltage set even when the power supply is managed by
96 * an external regulator.
97 */
sdhci_at91_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)98 static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
99 unsigned short vdd)
100 {
101 if (!IS_ERR(host->mmc->supply.vmmc)) {
102 struct mmc_host *mmc = host->mmc;
103
104 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
105 }
106 sdhci_set_power_noreg(host, mode, vdd);
107 }
108
sdhci_at91_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)109 static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
110 unsigned int timing)
111 {
112 u8 mc1r;
113
114 if (timing == MMC_TIMING_MMC_DDR52) {
115 mc1r = sdhci_readb(host, SDMMC_MC1R);
116 mc1r |= SDMMC_MC1R_DDR;
117 sdhci_writeb(host, mc1r, SDMMC_MC1R);
118 }
119 sdhci_set_uhs_signaling(host, timing);
120 }
121
sdhci_at91_reset(struct sdhci_host * host,u8 mask)122 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
123 {
124 sdhci_reset(host, mask);
125
126 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
127 || mmc_gpio_get_cd(host->mmc) >= 0)
128 sdhci_at91_set_force_card_detect(host);
129 }
130
131 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
132 .set_clock = sdhci_at91_set_clock,
133 .set_bus_width = sdhci_set_bus_width,
134 .reset = sdhci_at91_reset,
135 .set_uhs_signaling = sdhci_at91_set_uhs_signaling,
136 .set_power = sdhci_at91_set_power,
137 };
138
139 static const struct sdhci_pltfm_data soc_data_sama5d2 = {
140 .ops = &sdhci_at91_sama5d2_ops,
141 };
142
143 static const struct of_device_id sdhci_at91_dt_match[] = {
144 { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
145 {}
146 };
147 MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
148
sdhci_at91_set_clks_presets(struct device * dev)149 static int sdhci_at91_set_clks_presets(struct device *dev)
150 {
151 struct sdhci_host *host = dev_get_drvdata(dev);
152 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
153 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
154 int ret;
155 unsigned int caps0, caps1;
156 unsigned int clk_base, clk_mul;
157 unsigned int gck_rate, real_gck_rate;
158 unsigned int preset_div;
159
160 /*
161 * The mult clock is provided by as a generated clock by the PMC
162 * controller. In order to set the rate of gck, we have to get the
163 * base clock rate and the clock mult from capabilities.
164 */
165 clk_prepare_enable(priv->hclock);
166 caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
167 caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
168 clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
169 clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
170 gck_rate = clk_base * 1000000 * (clk_mul + 1);
171 ret = clk_set_rate(priv->gck, gck_rate);
172 if (ret < 0) {
173 dev_err(dev, "failed to set gck");
174 clk_disable_unprepare(priv->hclock);
175 return ret;
176 }
177 /*
178 * We need to check if we have the requested rate for gck because in
179 * some cases this rate could be not supported. If it happens, the rate
180 * is the closest one gck can provide. We have to update the value
181 * of clk mul.
182 */
183 real_gck_rate = clk_get_rate(priv->gck);
184 if (real_gck_rate != gck_rate) {
185 clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
186 caps1 &= (~SDHCI_CLOCK_MUL_MASK);
187 caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) &
188 SDHCI_CLOCK_MUL_MASK);
189 /* Set capabilities in r/w mode. */
190 writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN,
191 host->ioaddr + SDMMC_CACR);
192 writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
193 /* Set capabilities in ro mode. */
194 writel(0, host->ioaddr + SDMMC_CACR);
195 dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n",
196 clk_mul, real_gck_rate);
197 }
198
199 /*
200 * We have to set preset values because it depends on the clk_mul
201 * value. Moreover, SDR104 is supported in a degraded mode since the
202 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
203 * reason, we need to use presets to support SDR104.
204 */
205 preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
206 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
207 host->ioaddr + SDHCI_PRESET_FOR_SDR12);
208 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
209 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
210 host->ioaddr + SDHCI_PRESET_FOR_SDR25);
211 preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
212 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
213 host->ioaddr + SDHCI_PRESET_FOR_SDR50);
214 preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
215 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
216 host->ioaddr + SDHCI_PRESET_FOR_SDR104);
217 preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
218 writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
219 host->ioaddr + SDHCI_PRESET_FOR_DDR50);
220
221 clk_prepare_enable(priv->mainck);
222 clk_prepare_enable(priv->gck);
223
224 return 0;
225 }
226
227 #ifdef CONFIG_PM_SLEEP
sdhci_at91_suspend(struct device * dev)228 static int sdhci_at91_suspend(struct device *dev)
229 {
230 struct sdhci_host *host = dev_get_drvdata(dev);
231 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
232 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
233 int ret;
234
235 ret = pm_runtime_force_suspend(dev);
236
237 priv->restore_needed = true;
238
239 return ret;
240 }
241 #endif /* CONFIG_PM_SLEEP */
242
243 #ifdef CONFIG_PM
sdhci_at91_runtime_suspend(struct device * dev)244 static int sdhci_at91_runtime_suspend(struct device *dev)
245 {
246 struct sdhci_host *host = dev_get_drvdata(dev);
247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
248 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
249 int ret;
250
251 ret = sdhci_runtime_suspend_host(host);
252
253 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
254 mmc_retune_needed(host->mmc);
255
256 clk_disable_unprepare(priv->gck);
257 clk_disable_unprepare(priv->hclock);
258 clk_disable_unprepare(priv->mainck);
259
260 return ret;
261 }
262
sdhci_at91_runtime_resume(struct device * dev)263 static int sdhci_at91_runtime_resume(struct device *dev)
264 {
265 struct sdhci_host *host = dev_get_drvdata(dev);
266 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
267 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
268 int ret;
269
270 if (priv->restore_needed) {
271 ret = sdhci_at91_set_clks_presets(dev);
272 if (ret)
273 return ret;
274
275 priv->restore_needed = false;
276 goto out;
277 }
278
279 ret = clk_prepare_enable(priv->mainck);
280 if (ret) {
281 dev_err(dev, "can't enable mainck\n");
282 return ret;
283 }
284
285 ret = clk_prepare_enable(priv->hclock);
286 if (ret) {
287 dev_err(dev, "can't enable hclock\n");
288 return ret;
289 }
290
291 ret = clk_prepare_enable(priv->gck);
292 if (ret) {
293 dev_err(dev, "can't enable gck\n");
294 return ret;
295 }
296
297 out:
298 return sdhci_runtime_resume_host(host, 0);
299 }
300 #endif /* CONFIG_PM */
301
302 static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
303 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
304 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
305 sdhci_at91_runtime_resume,
306 NULL)
307 };
308
sdhci_at91_probe(struct platform_device * pdev)309 static int sdhci_at91_probe(struct platform_device *pdev)
310 {
311 const struct of_device_id *match;
312 const struct sdhci_pltfm_data *soc_data;
313 struct sdhci_host *host;
314 struct sdhci_pltfm_host *pltfm_host;
315 struct sdhci_at91_priv *priv;
316 int ret;
317
318 match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
319 if (!match)
320 return -EINVAL;
321 soc_data = match->data;
322
323 host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
324 if (IS_ERR(host))
325 return PTR_ERR(host);
326
327 pltfm_host = sdhci_priv(host);
328 priv = sdhci_pltfm_priv(pltfm_host);
329
330 priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
331 if (IS_ERR(priv->mainck)) {
332 dev_err(&pdev->dev, "failed to get baseclk\n");
333 ret = PTR_ERR(priv->mainck);
334 goto sdhci_pltfm_free;
335 }
336
337 priv->hclock = devm_clk_get(&pdev->dev, "hclock");
338 if (IS_ERR(priv->hclock)) {
339 dev_err(&pdev->dev, "failed to get hclock\n");
340 ret = PTR_ERR(priv->hclock);
341 goto sdhci_pltfm_free;
342 }
343
344 priv->gck = devm_clk_get(&pdev->dev, "multclk");
345 if (IS_ERR(priv->gck)) {
346 dev_err(&pdev->dev, "failed to get multclk\n");
347 ret = PTR_ERR(priv->gck);
348 goto sdhci_pltfm_free;
349 }
350
351 ret = sdhci_at91_set_clks_presets(&pdev->dev);
352 if (ret)
353 goto sdhci_pltfm_free;
354
355 priv->restore_needed = false;
356
357 ret = mmc_of_parse(host->mmc);
358 if (ret)
359 goto clocks_disable_unprepare;
360
361 sdhci_get_of_property(pdev);
362
363 pm_runtime_get_noresume(&pdev->dev);
364 pm_runtime_set_active(&pdev->dev);
365 pm_runtime_enable(&pdev->dev);
366 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
367 pm_runtime_use_autosuspend(&pdev->dev);
368
369 /* HS200 is broken at this moment */
370 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
371
372 ret = sdhci_add_host(host);
373 if (ret)
374 goto pm_runtime_disable;
375
376 /*
377 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
378 * the assumption that all the clocks of the controller are disabled.
379 * It means we can't get irq from it when it is runtime suspended.
380 * For that reason, it is not planned to wake-up on a card detect irq
381 * from the controller.
382 * If we want to use runtime PM and to be able to wake-up on card
383 * insertion, we have to use a GPIO for the card detection or we can
384 * use polling. Be aware that using polling will resume/suspend the
385 * controller between each attempt.
386 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
387 * to enable polling via device tree with broken-cd property.
388 */
389 if (mmc_card_is_removable(host->mmc) &&
390 mmc_gpio_get_cd(host->mmc) < 0) {
391 host->mmc->caps |= MMC_CAP_NEEDS_POLL;
392 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
393 }
394
395 /*
396 * If the device attached to the MMC bus is not removable, it is safer
397 * to set the Force Card Detect bit. People often don't connect the
398 * card detect signal and use this pin for another purpose. If the card
399 * detect pin is not muxed to SDHCI controller, a default value is
400 * used. This value can be different from a SoC revision to another
401 * one. Problems come when this default value is not card present. To
402 * avoid this case, if the device is non removable then the card
403 * detection procedure using the SDMCC_CD signal is bypassed.
404 * This bit is reset when a software reset for all command is performed
405 * so we need to implement our own reset function to set back this bit.
406 *
407 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
408 */
409 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
410 || mmc_gpio_get_cd(host->mmc) >= 0)
411 sdhci_at91_set_force_card_detect(host);
412
413 pm_runtime_put_autosuspend(&pdev->dev);
414
415 return 0;
416
417 pm_runtime_disable:
418 pm_runtime_disable(&pdev->dev);
419 pm_runtime_set_suspended(&pdev->dev);
420 pm_runtime_put_noidle(&pdev->dev);
421 clocks_disable_unprepare:
422 clk_disable_unprepare(priv->gck);
423 clk_disable_unprepare(priv->mainck);
424 clk_disable_unprepare(priv->hclock);
425 sdhci_pltfm_free:
426 sdhci_pltfm_free(pdev);
427 return ret;
428 }
429
sdhci_at91_remove(struct platform_device * pdev)430 static int sdhci_at91_remove(struct platform_device *pdev)
431 {
432 struct sdhci_host *host = platform_get_drvdata(pdev);
433 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
434 struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
435 struct clk *gck = priv->gck;
436 struct clk *hclock = priv->hclock;
437 struct clk *mainck = priv->mainck;
438
439 pm_runtime_get_sync(&pdev->dev);
440 pm_runtime_disable(&pdev->dev);
441 pm_runtime_put_noidle(&pdev->dev);
442
443 sdhci_pltfm_unregister(pdev);
444
445 clk_disable_unprepare(gck);
446 clk_disable_unprepare(hclock);
447 clk_disable_unprepare(mainck);
448
449 return 0;
450 }
451
452 static struct platform_driver sdhci_at91_driver = {
453 .driver = {
454 .name = "sdhci-at91",
455 .of_match_table = sdhci_at91_dt_match,
456 .pm = &sdhci_at91_dev_pm_ops,
457 },
458 .probe = sdhci_at91_probe,
459 .remove = sdhci_at91_remove,
460 };
461
462 module_platform_driver(sdhci_at91_driver);
463
464 MODULE_DESCRIPTION("SDHCI driver for at91");
465 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
466 MODULE_LICENSE("GPL v2");
467