1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 BayHub Technology Ltd.
4 *
5 * Authors: Peter Guo <peter.guo@bayhubtech.com>
6 * Adam Lee <adam.lee@canonical.com>
7 * Ernest Zhang <ernest.zhang@bayhubtech.com>
8 */
9
10 #include <linux/pci.h>
11 #include <linux/mmc/host.h>
12 #include <linux/mmc/mmc.h>
13 #include <linux/delay.h>
14 #include <linux/iopoll.h>
15
16 #include "sdhci.h"
17 #include "sdhci-pci.h"
18
19 /*
20 * O2Micro device registers
21 */
22
23 #define O2_SD_MISC_REG5 0x64
24 #define O2_SD_LD0_CTRL 0x68
25 #define O2_SD_DEV_CTRL 0x88
26 #define O2_SD_LOCK_WP 0xD3
27 #define O2_SD_TEST_REG 0xD4
28 #define O2_SD_FUNC_REG0 0xDC
29 #define O2_SD_MULTI_VCC3V 0xEE
30 #define O2_SD_CLKREQ 0xEC
31 #define O2_SD_CAPS 0xE0
32 #define O2_SD_ADMA1 0xE2
33 #define O2_SD_ADMA2 0xE7
34 #define O2_SD_MISC_CTRL2 0xF0
35 #define O2_SD_INF_MOD 0xF1
36 #define O2_SD_MISC_CTRL4 0xFC
37 #define O2_SD_TUNING_CTRL 0x300
38 #define O2_SD_PLL_SETTING 0x304
39 #define O2_SD_MISC_SETTING 0x308
40 #define O2_SD_CLK_SETTING 0x328
41 #define O2_SD_CAP_REG2 0x330
42 #define O2_SD_CAP_REG0 0x334
43 #define O2_SD_UHS1_CAP_SETTING 0x33C
44 #define O2_SD_DELAY_CTRL 0x350
45 #define O2_SD_UHS2_L1_CTRL 0x35C
46 #define O2_SD_FUNC_REG3 0x3E0
47 #define O2_SD_FUNC_REG4 0x3E4
48 #define O2_SD_LED_ENABLE BIT(6)
49 #define O2_SD_FREG0_LEDOFF BIT(13)
50 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
51
52 #define O2_SD_VENDOR_SETTING 0x110
53 #define O2_SD_VENDOR_SETTING2 0x1C8
54 #define O2_SD_HW_TUNING_DISABLE BIT(4)
55
56 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC
57 #define O2_PLL_FORCE_ACTIVE BIT(18)
58 #define O2_PLL_LOCK_STATUS BIT(14)
59 #define O2_PLL_SOFT_RESET BIT(12)
60 #define O2_DLL_LOCK_STATUS BIT(11)
61
62 #define O2_SD_DETECT_SETTING 0x324
63
64 static const u32 dmdn_table[] = {0x2B1C0000,
65 0x2C1A0000, 0x371B0000, 0x35100000};
66 #define DMDN_SZ ARRAY_SIZE(dmdn_table)
67
68 struct o2_host {
69 u8 dll_adjust_count;
70 };
71
sdhci_o2_wait_card_detect_stable(struct sdhci_host * host)72 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
73 {
74 ktime_t timeout;
75 u32 scratch32;
76
77 /* Wait max 50 ms */
78 timeout = ktime_add_ms(ktime_get(), 50);
79 while (1) {
80 bool timedout = ktime_after(ktime_get(), timeout);
81
82 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
83 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
84 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
85 break;
86
87 if (timedout) {
88 pr_err("%s: Card Detect debounce never finished.\n",
89 mmc_hostname(host->mmc));
90 sdhci_dumpregs(host);
91 return;
92 }
93 udelay(10);
94 }
95 }
96
sdhci_o2_enable_internal_clock(struct sdhci_host * host)97 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
98 {
99 ktime_t timeout;
100 u16 scratch;
101 u32 scratch32;
102
103 /* PLL software reset */
104 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
105 scratch32 |= O2_PLL_SOFT_RESET;
106 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
107 udelay(1);
108 scratch32 &= ~(O2_PLL_SOFT_RESET);
109 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
110
111 /* PLL force active */
112 scratch32 |= O2_PLL_FORCE_ACTIVE;
113 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
114
115 /* Wait max 20 ms */
116 timeout = ktime_add_ms(ktime_get(), 20);
117 while (1) {
118 bool timedout = ktime_after(ktime_get(), timeout);
119
120 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
121 if (scratch & O2_PLL_LOCK_STATUS)
122 break;
123 if (timedout) {
124 pr_err("%s: Internal clock never stabilised.\n",
125 mmc_hostname(host->mmc));
126 sdhci_dumpregs(host);
127 goto out;
128 }
129 udelay(10);
130 }
131
132 /* Wait for card detect finish */
133 udelay(1);
134 sdhci_o2_wait_card_detect_stable(host);
135
136 out:
137 /* Cancel PLL force active */
138 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
139 scratch32 &= ~O2_PLL_FORCE_ACTIVE;
140 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
141 }
142
sdhci_o2_get_cd(struct mmc_host * mmc)143 static int sdhci_o2_get_cd(struct mmc_host *mmc)
144 {
145 struct sdhci_host *host = mmc_priv(mmc);
146
147 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
148 sdhci_o2_enable_internal_clock(host);
149 else
150 sdhci_o2_wait_card_detect_stable(host);
151
152 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
153 }
154
o2_pci_set_baseclk(struct sdhci_pci_chip * chip,u32 value)155 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
156 {
157 u32 scratch_32;
158
159 pci_read_config_dword(chip->pdev,
160 O2_SD_PLL_SETTING, &scratch_32);
161
162 scratch_32 &= 0x0000FFFF;
163 scratch_32 |= value;
164
165 pci_write_config_dword(chip->pdev,
166 O2_SD_PLL_SETTING, scratch_32);
167 }
168
sdhci_o2_pll_dll_wdt_control(struct sdhci_host * host)169 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
170 {
171 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
172 }
173
174 /*
175 * This function is used to detect dll lock status.
176 * Since the dll lock status bit will toggle randomly
177 * with very short interval which needs to be polled
178 * as fast as possible. Set sleep_us as 1 microsecond.
179 */
sdhci_o2_wait_dll_detect_lock(struct sdhci_host * host)180 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
181 {
182 u32 scratch32 = 0;
183
184 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
185 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
186 }
187
sdhci_o2_set_tuning_mode(struct sdhci_host * host)188 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
189 {
190 u16 reg;
191
192 /* enable hardware tuning */
193 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
194 reg &= ~O2_SD_HW_TUNING_DISABLE;
195 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
196 }
197
__sdhci_o2_execute_tuning(struct sdhci_host * host,u32 opcode)198 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
199 {
200 int i;
201
202 sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
203
204 for (i = 0; i < 150; i++) {
205 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
206
207 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
208 if (ctrl & SDHCI_CTRL_TUNED_CLK) {
209 host->tuning_done = true;
210 return;
211 }
212 pr_warn("%s: HW tuning failed !\n",
213 mmc_hostname(host->mmc));
214 break;
215 }
216
217 mdelay(1);
218 }
219
220 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
221 mmc_hostname(host->mmc));
222 sdhci_reset_tuning(host);
223 }
224
225 /*
226 * This function is used to fix o2 dll shift issue.
227 * It isn't necessary to detect card present before recovery.
228 * Firstly, it is used by bht emmc card, which is embedded.
229 * Second, before call recovery card present will be detected
230 * outside of the execute tuning function.
231 */
sdhci_o2_dll_recovery(struct sdhci_host * host)232 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
233 {
234 int ret = 0;
235 u8 scratch_8 = 0;
236 u32 scratch_32 = 0;
237 struct sdhci_pci_slot *slot = sdhci_priv(host);
238 struct sdhci_pci_chip *chip = slot->chip;
239 struct o2_host *o2_host = sdhci_pci_priv(slot);
240
241 /* UnLock WP */
242 pci_read_config_byte(chip->pdev,
243 O2_SD_LOCK_WP, &scratch_8);
244 scratch_8 &= 0x7f;
245 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
246 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
247 /* Disable clock */
248 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
249
250 /* PLL software reset */
251 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
252 scratch_32 |= O2_PLL_SOFT_RESET;
253 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
254
255 pci_read_config_dword(chip->pdev,
256 O2_SD_FUNC_REG4,
257 &scratch_32);
258 /* Enable Base Clk setting change */
259 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
260 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
261 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
262
263 /* Enable internal clock */
264 scratch_8 = SDHCI_CLOCK_INT_EN;
265 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
266
267 if (sdhci_o2_get_cd(host->mmc)) {
268 /*
269 * need wait at least 5ms for dll status stable,
270 * after enable internal clock
271 */
272 usleep_range(5000, 6000);
273 if (sdhci_o2_wait_dll_detect_lock(host)) {
274 scratch_8 |= SDHCI_CLOCK_CARD_EN;
275 sdhci_writeb(host, scratch_8,
276 SDHCI_CLOCK_CONTROL);
277 ret = 1;
278 } else {
279 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
280 mmc_hostname(host->mmc),
281 o2_host->dll_adjust_count);
282 }
283 } else {
284 pr_err("%s: card present detect failed.\n",
285 mmc_hostname(host->mmc));
286 break;
287 }
288
289 o2_host->dll_adjust_count++;
290 }
291 if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
292 pr_err("%s: DLL adjust over max times\n",
293 mmc_hostname(host->mmc));
294 /* Lock WP */
295 pci_read_config_byte(chip->pdev,
296 O2_SD_LOCK_WP, &scratch_8);
297 scratch_8 |= 0x80;
298 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
299 return ret;
300 }
301
sdhci_o2_execute_tuning(struct mmc_host * mmc,u32 opcode)302 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
303 {
304 struct sdhci_host *host = mmc_priv(mmc);
305 int current_bus_width = 0;
306
307 /*
308 * This handler only implements the eMMC tuning that is specific to
309 * this controller. Fall back to the standard method for other TIMING.
310 */
311 if (host->timing != MMC_TIMING_MMC_HS200)
312 return sdhci_execute_tuning(mmc, opcode);
313
314 if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
315 return -EINVAL;
316 /*
317 * Judge the tuning reason, whether caused by dll shift
318 * If cause by dll shift, should call sdhci_o2_dll_recovery
319 */
320 if (!sdhci_o2_wait_dll_detect_lock(host))
321 if (!sdhci_o2_dll_recovery(host)) {
322 pr_err("%s: o2 dll recovery failed\n",
323 mmc_hostname(host->mmc));
324 return -EINVAL;
325 }
326 /*
327 * o2 sdhci host didn't support 8bit emmc tuning
328 */
329 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
330 current_bus_width = mmc->ios.bus_width;
331 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
332 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
333 }
334
335 sdhci_o2_set_tuning_mode(host);
336
337 sdhci_start_tuning(host);
338
339 __sdhci_o2_execute_tuning(host, opcode);
340
341 sdhci_end_tuning(host);
342
343 if (current_bus_width == MMC_BUS_WIDTH_8) {
344 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
345 sdhci_set_bus_width(host, current_bus_width);
346 }
347
348 host->flags &= ~SDHCI_HS400_TUNING;
349 return 0;
350 }
351
o2_pci_led_enable(struct sdhci_pci_chip * chip)352 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
353 {
354 int ret;
355 u32 scratch_32;
356
357 /* Set led of SD host function enable */
358 ret = pci_read_config_dword(chip->pdev,
359 O2_SD_FUNC_REG0, &scratch_32);
360 if (ret)
361 return;
362
363 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
364 pci_write_config_dword(chip->pdev,
365 O2_SD_FUNC_REG0, scratch_32);
366
367 ret = pci_read_config_dword(chip->pdev,
368 O2_SD_TEST_REG, &scratch_32);
369 if (ret)
370 return;
371
372 scratch_32 |= O2_SD_LED_ENABLE;
373 pci_write_config_dword(chip->pdev,
374 O2_SD_TEST_REG, scratch_32);
375
376 }
377
sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip * chip)378 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
379 {
380 u32 scratch_32;
381 int ret;
382 /* Improve write performance for SD3.0 */
383 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
384 if (ret)
385 return;
386 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
387 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
388
389 /* Enable Link abnormal reset generating Reset */
390 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
391 if (ret)
392 return;
393 scratch_32 &= ~((1 << 19) | (1 << 11));
394 scratch_32 |= (1 << 10);
395 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
396
397 /* set card power over current protection */
398 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
399 if (ret)
400 return;
401 scratch_32 |= (1 << 4);
402 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
403
404 /* adjust the output delay for SD mode */
405 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
406
407 /* Set the output voltage setting of Aux 1.2v LDO */
408 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
409 if (ret)
410 return;
411 scratch_32 &= ~(3 << 12);
412 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
413
414 /* Set Max power supply capability of SD host */
415 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
416 if (ret)
417 return;
418 scratch_32 &= ~(0x01FE);
419 scratch_32 |= 0x00CC;
420 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
421 /* Set DLL Tuning Window */
422 ret = pci_read_config_dword(chip->pdev,
423 O2_SD_TUNING_CTRL, &scratch_32);
424 if (ret)
425 return;
426 scratch_32 &= ~(0x000000FF);
427 scratch_32 |= 0x00000066;
428 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
429
430 /* Set UHS2 T_EIDLE */
431 ret = pci_read_config_dword(chip->pdev,
432 O2_SD_UHS2_L1_CTRL, &scratch_32);
433 if (ret)
434 return;
435 scratch_32 &= ~(0x000000FC);
436 scratch_32 |= 0x00000084;
437 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
438
439 /* Set UHS2 Termination */
440 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
441 if (ret)
442 return;
443 scratch_32 &= ~((1 << 21) | (1 << 30));
444
445 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
446
447 /* Set L1 Entrance Timer */
448 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
449 if (ret)
450 return;
451 scratch_32 &= ~(0xf0000000);
452 scratch_32 |= 0x30000000;
453 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
454
455 ret = pci_read_config_dword(chip->pdev,
456 O2_SD_MISC_CTRL4, &scratch_32);
457 if (ret)
458 return;
459 scratch_32 &= ~(0x000f0000);
460 scratch_32 |= 0x00080000;
461 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
462 }
463
sdhci_pci_o2_enable_msi(struct sdhci_pci_chip * chip,struct sdhci_host * host)464 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
465 struct sdhci_host *host)
466 {
467 int ret;
468
469 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
470 if (!ret) {
471 pr_info("%s: unsupport msi, use INTx irq\n",
472 mmc_hostname(host->mmc));
473 return;
474 }
475
476 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
477 PCI_IRQ_MSI | PCI_IRQ_MSIX);
478 if (ret < 0) {
479 pr_err("%s: enable PCI MSI failed, err=%d\n",
480 mmc_hostname(host->mmc), ret);
481 return;
482 }
483
484 host->irq = pci_irq_vector(chip->pdev, 0);
485 }
486
sdhci_o2_enable_clk(struct sdhci_host * host,u16 clk)487 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
488 {
489 /* Enable internal clock */
490 clk |= SDHCI_CLOCK_INT_EN;
491 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
492
493 sdhci_o2_enable_internal_clock(host);
494 if (sdhci_o2_get_cd(host->mmc)) {
495 clk |= SDHCI_CLOCK_CARD_EN;
496 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
497 }
498 }
499
sdhci_pci_o2_set_clock(struct sdhci_host * host,unsigned int clock)500 void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
501 {
502 u16 clk;
503
504 host->mmc->actual_clock = 0;
505
506 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
507
508 if (clock == 0)
509 return;
510
511 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
512 sdhci_o2_enable_clk(host, clk);
513 }
514
sdhci_pci_o2_probe_slot(struct sdhci_pci_slot * slot)515 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
516 {
517 struct sdhci_pci_chip *chip;
518 struct sdhci_host *host;
519 struct o2_host *o2_host = sdhci_pci_priv(slot);
520 u32 reg, caps;
521 int ret;
522
523 chip = slot->chip;
524 host = slot->host;
525
526 o2_host->dll_adjust_count = 0;
527 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
528
529 /*
530 * mmc_select_bus_width() will test the bus to determine the actual bus
531 * width.
532 */
533 if (caps & SDHCI_CAN_DO_8BIT)
534 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
535
536 switch (chip->pdev->device) {
537 case PCI_DEVICE_ID_O2_SDS0:
538 case PCI_DEVICE_ID_O2_SEABIRD0:
539 case PCI_DEVICE_ID_O2_SEABIRD1:
540 case PCI_DEVICE_ID_O2_SDS1:
541 case PCI_DEVICE_ID_O2_FUJIN2:
542 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
543 if (reg & 0x1)
544 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
545
546 sdhci_pci_o2_enable_msi(chip, host);
547
548 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
549 ret = pci_read_config_dword(chip->pdev,
550 O2_SD_MISC_SETTING, ®);
551 if (ret)
552 return -EIO;
553 if (reg & (1 << 4)) {
554 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
555 mmc_hostname(host->mmc));
556 host->flags &= ~SDHCI_SIGNALING_330;
557 host->flags |= SDHCI_SIGNALING_180;
558 host->mmc->caps2 |= MMC_CAP2_NO_SD;
559 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
560 pci_write_config_dword(chip->pdev,
561 O2_SD_DETECT_SETTING, 3);
562 }
563
564 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
565 }
566
567 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
568 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
569 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
570 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
571 }
572
573 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
574
575 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
576 break;
577 /* set dll watch dog timer */
578 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
579 reg |= (1 << 12);
580 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
581
582 break;
583 default:
584 break;
585 }
586
587 return 0;
588 }
589
sdhci_pci_o2_probe(struct sdhci_pci_chip * chip)590 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
591 {
592 int ret;
593 u8 scratch;
594 u32 scratch_32;
595
596 switch (chip->pdev->device) {
597 case PCI_DEVICE_ID_O2_8220:
598 case PCI_DEVICE_ID_O2_8221:
599 case PCI_DEVICE_ID_O2_8320:
600 case PCI_DEVICE_ID_O2_8321:
601 /* This extra setup is required due to broken ADMA. */
602 ret = pci_read_config_byte(chip->pdev,
603 O2_SD_LOCK_WP, &scratch);
604 if (ret)
605 return ret;
606 scratch &= 0x7f;
607 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
608
609 /* Set Multi 3 to VCC3V# */
610 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
611
612 /* Disable CLK_REQ# support after media DET */
613 ret = pci_read_config_byte(chip->pdev,
614 O2_SD_CLKREQ, &scratch);
615 if (ret)
616 return ret;
617 scratch |= 0x20;
618 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
619
620 /* Choose capabilities, enable SDMA. We have to write 0x01
621 * to the capabilities register first to unlock it.
622 */
623 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
624 if (ret)
625 return ret;
626 scratch |= 0x01;
627 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
628 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
629
630 /* Disable ADMA1/2 */
631 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
632 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
633
634 /* Disable the infinite transfer mode */
635 ret = pci_read_config_byte(chip->pdev,
636 O2_SD_INF_MOD, &scratch);
637 if (ret)
638 return ret;
639 scratch |= 0x08;
640 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
641
642 /* Lock WP */
643 ret = pci_read_config_byte(chip->pdev,
644 O2_SD_LOCK_WP, &scratch);
645 if (ret)
646 return ret;
647 scratch |= 0x80;
648 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
649 break;
650 case PCI_DEVICE_ID_O2_SDS0:
651 case PCI_DEVICE_ID_O2_SDS1:
652 case PCI_DEVICE_ID_O2_FUJIN2:
653 /* UnLock WP */
654 ret = pci_read_config_byte(chip->pdev,
655 O2_SD_LOCK_WP, &scratch);
656 if (ret)
657 return ret;
658
659 scratch &= 0x7f;
660 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
661
662 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
663 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
664 ret = pci_read_config_dword(chip->pdev,
665 O2_SD_FUNC_REG0,
666 &scratch_32);
667 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
668
669 /* Check Whether subId is 0x11 or 0x12 */
670 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
671 scratch_32 = 0x25100000;
672
673 o2_pci_set_baseclk(chip, scratch_32);
674 ret = pci_read_config_dword(chip->pdev,
675 O2_SD_FUNC_REG4,
676 &scratch_32);
677
678 /* Enable Base Clk setting change */
679 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
680 pci_write_config_dword(chip->pdev,
681 O2_SD_FUNC_REG4,
682 scratch_32);
683
684 /* Set Tuning Window to 4 */
685 pci_write_config_byte(chip->pdev,
686 O2_SD_TUNING_CTRL, 0x44);
687
688 break;
689 }
690 }
691
692 /* Enable 8520 led function */
693 o2_pci_led_enable(chip);
694
695 /* Set timeout CLK */
696 ret = pci_read_config_dword(chip->pdev,
697 O2_SD_CLK_SETTING, &scratch_32);
698 if (ret)
699 return ret;
700
701 scratch_32 &= ~(0xFF00);
702 scratch_32 |= 0x07E0C800;
703 pci_write_config_dword(chip->pdev,
704 O2_SD_CLK_SETTING, scratch_32);
705
706 ret = pci_read_config_dword(chip->pdev,
707 O2_SD_CLKREQ, &scratch_32);
708 if (ret)
709 return ret;
710 scratch_32 |= 0x3;
711 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
712
713 ret = pci_read_config_dword(chip->pdev,
714 O2_SD_PLL_SETTING, &scratch_32);
715 if (ret)
716 return ret;
717
718 scratch_32 &= ~(0x1F3F070E);
719 scratch_32 |= 0x18270106;
720 pci_write_config_dword(chip->pdev,
721 O2_SD_PLL_SETTING, scratch_32);
722
723 /* Disable UHS1 funciton */
724 ret = pci_read_config_dword(chip->pdev,
725 O2_SD_CAP_REG2, &scratch_32);
726 if (ret)
727 return ret;
728 scratch_32 &= ~(0xE0);
729 pci_write_config_dword(chip->pdev,
730 O2_SD_CAP_REG2, scratch_32);
731
732 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
733 sdhci_pci_o2_fujin2_pci_init(chip);
734
735 /* Lock WP */
736 ret = pci_read_config_byte(chip->pdev,
737 O2_SD_LOCK_WP, &scratch);
738 if (ret)
739 return ret;
740 scratch |= 0x80;
741 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
742 break;
743 case PCI_DEVICE_ID_O2_SEABIRD0:
744 case PCI_DEVICE_ID_O2_SEABIRD1:
745 /* UnLock WP */
746 ret = pci_read_config_byte(chip->pdev,
747 O2_SD_LOCK_WP, &scratch);
748 if (ret)
749 return ret;
750
751 scratch &= 0x7f;
752 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
753
754 ret = pci_read_config_dword(chip->pdev,
755 O2_SD_PLL_SETTING, &scratch_32);
756
757 if ((scratch_32 & 0xff000000) == 0x01000000) {
758 scratch_32 &= 0x0000FFFF;
759 scratch_32 |= 0x1F340000;
760
761 pci_write_config_dword(chip->pdev,
762 O2_SD_PLL_SETTING, scratch_32);
763 } else {
764 scratch_32 &= 0x0000FFFF;
765 scratch_32 |= 0x25100000;
766
767 pci_write_config_dword(chip->pdev,
768 O2_SD_PLL_SETTING, scratch_32);
769
770 ret = pci_read_config_dword(chip->pdev,
771 O2_SD_FUNC_REG4,
772 &scratch_32);
773 scratch_32 |= (1 << 22);
774 pci_write_config_dword(chip->pdev,
775 O2_SD_FUNC_REG4, scratch_32);
776 }
777
778 /* Set Tuning Windows to 5 */
779 pci_write_config_byte(chip->pdev,
780 O2_SD_TUNING_CTRL, 0x55);
781 //Adjust 1st and 2nd CD debounce time
782 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
783 scratch_32 &= 0xFFE7FFFF;
784 scratch_32 |= 0x00180000;
785 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);
786 pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1);
787 /* Lock WP */
788 ret = pci_read_config_byte(chip->pdev,
789 O2_SD_LOCK_WP, &scratch);
790 if (ret)
791 return ret;
792 scratch |= 0x80;
793 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
794 break;
795 }
796
797 return 0;
798 }
799
800 #ifdef CONFIG_PM_SLEEP
sdhci_pci_o2_resume(struct sdhci_pci_chip * chip)801 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
802 {
803 sdhci_pci_o2_probe(chip);
804 return sdhci_pci_resume_host(chip);
805 }
806 #endif
807
808 static const struct sdhci_ops sdhci_pci_o2_ops = {
809 .set_clock = sdhci_pci_o2_set_clock,
810 .enable_dma = sdhci_pci_enable_dma,
811 .set_bus_width = sdhci_set_bus_width,
812 .reset = sdhci_reset,
813 .set_uhs_signaling = sdhci_set_uhs_signaling,
814 };
815
816 const struct sdhci_pci_fixes sdhci_o2 = {
817 .probe = sdhci_pci_o2_probe,
818 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
819 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
820 .probe_slot = sdhci_pci_o2_probe_slot,
821 #ifdef CONFIG_PM_SLEEP
822 .resume = sdhci_pci_o2_resume,
823 #endif
824 .ops = &sdhci_pci_o2_ops,
825 .priv_size = sizeof(struct o2_host),
826 };
827