1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/mmc/host/sdhci_f_sdh30.c
4 *
5 * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
6 * Vincent Yang <vincent.yang@tw.fujitsu.com>
7 * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/err.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/property.h>
16 #include <linux/clk.h>
17
18 #include "sdhci-pltfm.h"
19
20 /* F_SDH30 extended Controller registers */
21 #define F_SDH30_AHB_CONFIG 0x100
22 #define F_SDH30_AHB_BIGED 0x00000040
23 #define F_SDH30_BUSLOCK_DMA 0x00000020
24 #define F_SDH30_BUSLOCK_EN 0x00000010
25 #define F_SDH30_SIN 0x00000008
26 #define F_SDH30_AHB_INCR_16 0x00000004
27 #define F_SDH30_AHB_INCR_8 0x00000002
28 #define F_SDH30_AHB_INCR_4 0x00000001
29
30 #define F_SDH30_TUNING_SETTING 0x108
31 #define F_SDH30_CMD_CHK_DIS 0x00010000
32
33 #define F_SDH30_IO_CONTROL2 0x114
34 #define F_SDH30_CRES_O_DN 0x00080000
35 #define F_SDH30_MSEL_O_1_8 0x00040000
36
37 #define F_SDH30_ESD_CONTROL 0x124
38 #define F_SDH30_EMMC_RST 0x00000002
39 #define F_SDH30_EMMC_HS200 0x01000000
40
41 #define F_SDH30_CMD_DAT_DELAY 0x200
42
43 #define F_SDH30_MIN_CLOCK 400000
44
45 struct f_sdhost_priv {
46 struct clk *clk_iface;
47 struct clk *clk;
48 u32 vendor_hs200;
49 struct device *dev;
50 bool enable_cmd_dat_delay;
51 };
52
sdhci_f_sdhost_priv(struct sdhci_host * host)53 static void *sdhci_f_sdhost_priv(struct sdhci_host *host)
54 {
55 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
56
57 return sdhci_pltfm_priv(pltfm_host);
58 }
59
sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host * host)60 static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
61 {
62 struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
63 u32 ctrl = 0;
64
65 usleep_range(2500, 3000);
66 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
67 ctrl |= F_SDH30_CRES_O_DN;
68 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
69 ctrl |= F_SDH30_MSEL_O_1_8;
70 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
71
72 ctrl &= ~F_SDH30_CRES_O_DN;
73 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
74 usleep_range(2500, 3000);
75
76 if (priv->vendor_hs200) {
77 dev_info(priv->dev, "%s: setting hs200\n", __func__);
78 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
79 ctrl |= priv->vendor_hs200;
80 sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
81 }
82
83 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
84 ctrl |= F_SDH30_CMD_CHK_DIS;
85 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
86 }
87
sdhci_f_sdh30_get_min_clock(struct sdhci_host * host)88 static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
89 {
90 return F_SDH30_MIN_CLOCK;
91 }
92
sdhci_f_sdh30_reset(struct sdhci_host * host,u8 mask)93 static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
94 {
95 struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
96 u32 ctl;
97
98 if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
99 sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
100
101 sdhci_reset(host, mask);
102
103 if (priv->enable_cmd_dat_delay) {
104 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
105 ctl |= F_SDH30_CMD_DAT_DELAY;
106 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
107 }
108 }
109
110 static const struct sdhci_ops sdhci_f_sdh30_ops = {
111 .voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
112 .get_min_clock = sdhci_f_sdh30_get_min_clock,
113 .reset = sdhci_f_sdh30_reset,
114 .set_clock = sdhci_set_clock,
115 .set_bus_width = sdhci_set_bus_width,
116 .set_uhs_signaling = sdhci_set_uhs_signaling,
117 };
118
119 static const struct sdhci_pltfm_data sdhci_f_sdh30_pltfm_data = {
120 .ops = &sdhci_f_sdh30_ops,
121 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
122 | SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
123 .quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE
124 | SDHCI_QUIRK2_TUNING_WORK_AROUND,
125 };
126
sdhci_f_sdh30_probe(struct platform_device * pdev)127 static int sdhci_f_sdh30_probe(struct platform_device *pdev)
128 {
129 struct sdhci_host *host;
130 struct device *dev = &pdev->dev;
131 int ctrl = 0, ret = 0;
132 struct f_sdhost_priv *priv;
133 struct sdhci_pltfm_host *pltfm_host;
134 u32 reg = 0;
135
136 host = sdhci_pltfm_init(pdev, &sdhci_f_sdh30_pltfm_data,
137 sizeof(struct f_sdhost_priv));
138 if (IS_ERR(host))
139 return PTR_ERR(host);
140
141 pltfm_host = sdhci_priv(host);
142 priv = sdhci_pltfm_priv(pltfm_host);
143 priv->dev = dev;
144
145 priv->enable_cmd_dat_delay = device_property_read_bool(dev,
146 "fujitsu,cmd-dat-delay-select");
147
148 ret = mmc_of_parse(host->mmc);
149 if (ret)
150 goto err;
151
152 if (dev_of_node(dev)) {
153 sdhci_get_of_property(pdev);
154
155 priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
156 if (IS_ERR(priv->clk_iface)) {
157 ret = PTR_ERR(priv->clk_iface);
158 goto err;
159 }
160
161 ret = clk_prepare_enable(priv->clk_iface);
162 if (ret)
163 goto err;
164
165 priv->clk = devm_clk_get(&pdev->dev, "core");
166 if (IS_ERR(priv->clk)) {
167 ret = PTR_ERR(priv->clk);
168 goto err_clk;
169 }
170
171 ret = clk_prepare_enable(priv->clk);
172 if (ret)
173 goto err_clk;
174 }
175
176 /* init vendor specific regs */
177 ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
178 ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
179 F_SDH30_AHB_INCR_4;
180 ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
181 sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
182
183 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
184 sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
185 msleep(20);
186 sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
187
188 reg = sdhci_readl(host, SDHCI_CAPABILITIES);
189 if (reg & SDHCI_CAN_DO_8BIT)
190 priv->vendor_hs200 = F_SDH30_EMMC_HS200;
191
192 if (!(reg & SDHCI_TIMEOUT_CLK_MASK))
193 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
194
195 ret = sdhci_add_host(host);
196 if (ret)
197 goto err_add_host;
198
199 return 0;
200
201 err_add_host:
202 clk_disable_unprepare(priv->clk);
203 err_clk:
204 clk_disable_unprepare(priv->clk_iface);
205 err:
206 sdhci_pltfm_free(pdev);
207
208 return ret;
209 }
210
sdhci_f_sdh30_remove(struct platform_device * pdev)211 static int sdhci_f_sdh30_remove(struct platform_device *pdev)
212 {
213 struct sdhci_host *host = platform_get_drvdata(pdev);
214 struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
215 struct clk *clk_iface = priv->clk_iface;
216 struct clk *clk = priv->clk;
217
218 sdhci_pltfm_unregister(pdev);
219
220 clk_disable_unprepare(clk_iface);
221 clk_disable_unprepare(clk);
222
223 return 0;
224 }
225
226 #ifdef CONFIG_OF
227 static const struct of_device_id f_sdh30_dt_ids[] = {
228 { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
229 { /* sentinel */ }
230 };
231 MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
232 #endif
233
234 #ifdef CONFIG_ACPI
235 static const struct acpi_device_id f_sdh30_acpi_ids[] = {
236 { "SCX0002" },
237 { /* sentinel */ }
238 };
239 MODULE_DEVICE_TABLE(acpi, f_sdh30_acpi_ids);
240 #endif
241
242 static struct platform_driver sdhci_f_sdh30_driver = {
243 .driver = {
244 .name = "f_sdh30",
245 .of_match_table = of_match_ptr(f_sdh30_dt_ids),
246 .acpi_match_table = ACPI_PTR(f_sdh30_acpi_ids),
247 .pm = &sdhci_pltfm_pmops,
248 },
249 .probe = sdhci_f_sdh30_probe,
250 .remove = sdhci_f_sdh30_remove,
251 };
252
253 module_platform_driver(sdhci_f_sdh30_driver);
254
255 MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
256 MODULE_LICENSE("GPL v2");
257 MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD.");
258 MODULE_ALIAS("platform:f_sdh30");
259