1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for NAND MLC Controller in LPC32xx
4 *
5 * Author: Roland Stigge <stigge@antcom.de>
6 *
7 * Copyright © 2011 WORK Microwave GmbH
8 * Copyright © 2011, 2012 Roland Stigge
9 *
10 * NAND Flash Controller Operation:
11 * - Read: Auto Decode
12 * - Write: Auto Encode
13 * - Tested Page Sizes: 2048, 4096
14 */
15
16 #include <linux/slab.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/rawnand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/delay.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/of.h>
28 #include <linux/of_gpio.h>
29 #include <linux/mtd/lpc32xx_mlc.h>
30 #include <linux/io.h>
31 #include <linux/mm.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34 #include <linux/mtd/nand_ecc.h>
35
36 #define DRV_NAME "lpc32xx_mlc"
37
38 /**********************************************************************
39 * MLC NAND controller register offsets
40 **********************************************************************/
41
42 #define MLC_BUFF(x) (x + 0x00000)
43 #define MLC_DATA(x) (x + 0x08000)
44 #define MLC_CMD(x) (x + 0x10000)
45 #define MLC_ADDR(x) (x + 0x10004)
46 #define MLC_ECC_ENC_REG(x) (x + 0x10008)
47 #define MLC_ECC_DEC_REG(x) (x + 0x1000C)
48 #define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010)
49 #define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014)
50 #define MLC_RPR(x) (x + 0x10018)
51 #define MLC_WPR(x) (x + 0x1001C)
52 #define MLC_RUBP(x) (x + 0x10020)
53 #define MLC_ROBP(x) (x + 0x10024)
54 #define MLC_SW_WP_ADD_LOW(x) (x + 0x10028)
55 #define MLC_SW_WP_ADD_HIG(x) (x + 0x1002C)
56 #define MLC_ICR(x) (x + 0x10030)
57 #define MLC_TIME_REG(x) (x + 0x10034)
58 #define MLC_IRQ_MR(x) (x + 0x10038)
59 #define MLC_IRQ_SR(x) (x + 0x1003C)
60 #define MLC_LOCK_PR(x) (x + 0x10044)
61 #define MLC_ISR(x) (x + 0x10048)
62 #define MLC_CEH(x) (x + 0x1004C)
63
64 /**********************************************************************
65 * MLC_CMD bit definitions
66 **********************************************************************/
67 #define MLCCMD_RESET 0xFF
68
69 /**********************************************************************
70 * MLC_ICR bit definitions
71 **********************************************************************/
72 #define MLCICR_WPROT (1 << 3)
73 #define MLCICR_LARGEBLOCK (1 << 2)
74 #define MLCICR_LONGADDR (1 << 1)
75 #define MLCICR_16BIT (1 << 0) /* unsupported by LPC32x0! */
76
77 /**********************************************************************
78 * MLC_TIME_REG bit definitions
79 **********************************************************************/
80 #define MLCTIMEREG_TCEA_DELAY(n) (((n) & 0x03) << 24)
81 #define MLCTIMEREG_BUSY_DELAY(n) (((n) & 0x1F) << 19)
82 #define MLCTIMEREG_NAND_TA(n) (((n) & 0x07) << 16)
83 #define MLCTIMEREG_RD_HIGH(n) (((n) & 0x0F) << 12)
84 #define MLCTIMEREG_RD_LOW(n) (((n) & 0x0F) << 8)
85 #define MLCTIMEREG_WR_HIGH(n) (((n) & 0x0F) << 4)
86 #define MLCTIMEREG_WR_LOW(n) (((n) & 0x0F) << 0)
87
88 /**********************************************************************
89 * MLC_IRQ_MR and MLC_IRQ_SR bit definitions
90 **********************************************************************/
91 #define MLCIRQ_NAND_READY (1 << 5)
92 #define MLCIRQ_CONTROLLER_READY (1 << 4)
93 #define MLCIRQ_DECODE_FAILURE (1 << 3)
94 #define MLCIRQ_DECODE_ERROR (1 << 2)
95 #define MLCIRQ_ECC_READY (1 << 1)
96 #define MLCIRQ_WRPROT_FAULT (1 << 0)
97
98 /**********************************************************************
99 * MLC_LOCK_PR bit definitions
100 **********************************************************************/
101 #define MLCLOCKPR_MAGIC 0xA25E
102
103 /**********************************************************************
104 * MLC_ISR bit definitions
105 **********************************************************************/
106 #define MLCISR_DECODER_FAILURE (1 << 6)
107 #define MLCISR_ERRORS ((1 << 4) | (1 << 5))
108 #define MLCISR_ERRORS_DETECTED (1 << 3)
109 #define MLCISR_ECC_READY (1 << 2)
110 #define MLCISR_CONTROLLER_READY (1 << 1)
111 #define MLCISR_NAND_READY (1 << 0)
112
113 /**********************************************************************
114 * MLC_CEH bit definitions
115 **********************************************************************/
116 #define MLCCEH_NORMAL (1 << 0)
117
118 struct lpc32xx_nand_cfg_mlc {
119 uint32_t tcea_delay;
120 uint32_t busy_delay;
121 uint32_t nand_ta;
122 uint32_t rd_high;
123 uint32_t rd_low;
124 uint32_t wr_high;
125 uint32_t wr_low;
126 int wp_gpio;
127 struct mtd_partition *parts;
128 unsigned num_parts;
129 };
130
lpc32xx_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)131 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
132 struct mtd_oob_region *oobregion)
133 {
134 struct nand_chip *nand_chip = mtd_to_nand(mtd);
135
136 if (section >= nand_chip->ecc.steps)
137 return -ERANGE;
138
139 oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes;
140 oobregion->length = nand_chip->ecc.bytes;
141
142 return 0;
143 }
144
lpc32xx_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)145 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
146 struct mtd_oob_region *oobregion)
147 {
148 struct nand_chip *nand_chip = mtd_to_nand(mtd);
149
150 if (section >= nand_chip->ecc.steps)
151 return -ERANGE;
152
153 oobregion->offset = 16 * section;
154 oobregion->length = 16 - nand_chip->ecc.bytes;
155
156 return 0;
157 }
158
159 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
160 .ecc = lpc32xx_ooblayout_ecc,
161 .free = lpc32xx_ooblayout_free,
162 };
163
164 static struct nand_bbt_descr lpc32xx_nand_bbt = {
165 .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
166 NAND_BBT_WRITE,
167 .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 },
168 };
169
170 static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = {
171 .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
172 NAND_BBT_WRITE,
173 .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 },
174 };
175
176 struct lpc32xx_nand_host {
177 struct platform_device *pdev;
178 struct nand_chip nand_chip;
179 struct lpc32xx_mlc_platform_data *pdata;
180 struct clk *clk;
181 void __iomem *io_base;
182 int irq;
183 struct lpc32xx_nand_cfg_mlc *ncfg;
184 struct completion comp_nand;
185 struct completion comp_controller;
186 uint32_t llptr;
187 /*
188 * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer
189 */
190 dma_addr_t oob_buf_phy;
191 /*
192 * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer
193 */
194 uint8_t *oob_buf;
195 /* Physical address of DMA base address */
196 dma_addr_t io_base_phy;
197
198 struct completion comp_dma;
199 struct dma_chan *dma_chan;
200 struct dma_slave_config dma_slave_config;
201 struct scatterlist sgl;
202 uint8_t *dma_buf;
203 uint8_t *dummy_buf;
204 int mlcsubpages; /* number of 512bytes-subpages */
205 };
206
207 /*
208 * Activate/Deactivate DMA Operation:
209 *
210 * Using the PL080 DMA Controller for transferring the 512 byte subpages
211 * instead of doing readl() / writel() in a loop slows it down significantly.
212 * Measurements via getnstimeofday() upon 512 byte subpage reads reveal:
213 *
214 * - readl() of 128 x 32 bits in a loop: ~20us
215 * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us
216 * - DMA read of 512 bytes (32 bit, no bursts): ~100us
217 *
218 * This applies to the transfer itself. In the DMA case: only the
219 * wait_for_completion() (DMA setup _not_ included).
220 *
221 * Note that the 512 bytes subpage transfer is done directly from/to a
222 * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a
223 * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND
224 * controller transferring data between its internal buffer to/from the NAND
225 * chip.)
226 *
227 * Therefore, using the PL080 DMA is disabled by default, for now.
228 *
229 */
230 static int use_dma;
231
lpc32xx_nand_setup(struct lpc32xx_nand_host * host)232 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
233 {
234 uint32_t clkrate, tmp;
235
236 /* Reset MLC controller */
237 writel(MLCCMD_RESET, MLC_CMD(host->io_base));
238 udelay(1000);
239
240 /* Get base clock for MLC block */
241 clkrate = clk_get_rate(host->clk);
242 if (clkrate == 0)
243 clkrate = 104000000;
244
245 /* Unlock MLC_ICR
246 * (among others, will be locked again automatically) */
247 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
248
249 /* Configure MLC Controller: Large Block, 5 Byte Address */
250 tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR;
251 writel(tmp, MLC_ICR(host->io_base));
252
253 /* Unlock MLC_TIME_REG
254 * (among others, will be locked again automatically) */
255 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
256
257 /* Compute clock setup values, see LPC and NAND manual */
258 tmp = 0;
259 tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
260 tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
261 tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
262 tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
263 tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
264 tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
265 tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
266 writel(tmp, MLC_TIME_REG(host->io_base));
267
268 /* Enable IRQ for CONTROLLER_READY and NAND_READY */
269 writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY,
270 MLC_IRQ_MR(host->io_base));
271
272 /* Normal nCE operation: nCE controlled by controller */
273 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
274 }
275
276 /*
277 * Hardware specific access to control lines
278 */
lpc32xx_nand_cmd_ctrl(struct nand_chip * nand_chip,int cmd,unsigned int ctrl)279 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
280 unsigned int ctrl)
281 {
282 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
283
284 if (cmd != NAND_CMD_NONE) {
285 if (ctrl & NAND_CLE)
286 writel(cmd, MLC_CMD(host->io_base));
287 else
288 writel(cmd, MLC_ADDR(host->io_base));
289 }
290 }
291
292 /*
293 * Read Device Ready (NAND device _and_ controller ready)
294 */
lpc32xx_nand_device_ready(struct nand_chip * nand_chip)295 static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip)
296 {
297 struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
298
299 if ((readb(MLC_ISR(host->io_base)) &
300 (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) ==
301 (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY))
302 return 1;
303
304 return 0;
305 }
306
lpc3xxx_nand_irq(int irq,void * data)307 static irqreturn_t lpc3xxx_nand_irq(int irq, void *data)
308 {
309 struct lpc32xx_nand_host *host = data;
310 uint8_t sr;
311
312 /* Clear interrupt flag by reading status */
313 sr = readb(MLC_IRQ_SR(host->io_base));
314 if (sr & MLCIRQ_NAND_READY)
315 complete(&host->comp_nand);
316 if (sr & MLCIRQ_CONTROLLER_READY)
317 complete(&host->comp_controller);
318
319 return IRQ_HANDLED;
320 }
321
lpc32xx_waitfunc_nand(struct nand_chip * chip)322 static int lpc32xx_waitfunc_nand(struct nand_chip *chip)
323 {
324 struct mtd_info *mtd = nand_to_mtd(chip);
325 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
326
327 if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
328 goto exit;
329
330 wait_for_completion(&host->comp_nand);
331
332 while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
333 /* Seems to be delayed sometimes by controller */
334 dev_dbg(&mtd->dev, "Warning: NAND not ready.\n");
335 cpu_relax();
336 }
337
338 exit:
339 return NAND_STATUS_READY;
340 }
341
lpc32xx_waitfunc_controller(struct nand_chip * chip)342 static int lpc32xx_waitfunc_controller(struct nand_chip *chip)
343 {
344 struct mtd_info *mtd = nand_to_mtd(chip);
345 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
346
347 if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
348 goto exit;
349
350 wait_for_completion(&host->comp_controller);
351
352 while (!(readb(MLC_ISR(host->io_base)) &
353 MLCISR_CONTROLLER_READY)) {
354 dev_dbg(&mtd->dev, "Warning: Controller not ready.\n");
355 cpu_relax();
356 }
357
358 exit:
359 return NAND_STATUS_READY;
360 }
361
lpc32xx_waitfunc(struct nand_chip * chip)362 static int lpc32xx_waitfunc(struct nand_chip *chip)
363 {
364 lpc32xx_waitfunc_nand(chip);
365 lpc32xx_waitfunc_controller(chip);
366
367 return NAND_STATUS_READY;
368 }
369
370 /*
371 * Enable NAND write protect
372 */
lpc32xx_wp_enable(struct lpc32xx_nand_host * host)373 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
374 {
375 if (gpio_is_valid(host->ncfg->wp_gpio))
376 gpio_set_value(host->ncfg->wp_gpio, 0);
377 }
378
379 /*
380 * Disable NAND write protect
381 */
lpc32xx_wp_disable(struct lpc32xx_nand_host * host)382 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
383 {
384 if (gpio_is_valid(host->ncfg->wp_gpio))
385 gpio_set_value(host->ncfg->wp_gpio, 1);
386 }
387
lpc32xx_dma_complete_func(void * completion)388 static void lpc32xx_dma_complete_func(void *completion)
389 {
390 complete(completion);
391 }
392
lpc32xx_xmit_dma(struct mtd_info * mtd,void * mem,int len,enum dma_transfer_direction dir)393 static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
394 enum dma_transfer_direction dir)
395 {
396 struct nand_chip *chip = mtd_to_nand(mtd);
397 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
398 struct dma_async_tx_descriptor *desc;
399 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
400 int res;
401
402 sg_init_one(&host->sgl, mem, len);
403
404 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
405 DMA_BIDIRECTIONAL);
406 if (res != 1) {
407 dev_err(mtd->dev.parent, "Failed to map sg list\n");
408 return -ENXIO;
409 }
410 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
411 flags);
412 if (!desc) {
413 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
414 goto out1;
415 }
416
417 init_completion(&host->comp_dma);
418 desc->callback = lpc32xx_dma_complete_func;
419 desc->callback_param = &host->comp_dma;
420
421 dmaengine_submit(desc);
422 dma_async_issue_pending(host->dma_chan);
423
424 wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
425
426 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
427 DMA_BIDIRECTIONAL);
428 return 0;
429 out1:
430 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
431 DMA_BIDIRECTIONAL);
432 return -ENXIO;
433 }
434
lpc32xx_read_page(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)435 static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,
436 int oob_required, int page)
437 {
438 struct mtd_info *mtd = nand_to_mtd(chip);
439 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
440 int i, j;
441 uint8_t *oobbuf = chip->oob_poi;
442 uint32_t mlc_isr;
443 int res;
444 uint8_t *dma_buf;
445 bool dma_mapped;
446
447 if ((void *)buf <= high_memory) {
448 dma_buf = buf;
449 dma_mapped = true;
450 } else {
451 dma_buf = host->dma_buf;
452 dma_mapped = false;
453 }
454
455 /* Writing Command and Address */
456 nand_read_page_op(chip, page, 0, NULL, 0);
457
458 /* For all sub-pages */
459 for (i = 0; i < host->mlcsubpages; i++) {
460 /* Start Auto Decode Command */
461 writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
462
463 /* Wait for Controller Ready */
464 lpc32xx_waitfunc_controller(chip);
465
466 /* Check ECC Error status */
467 mlc_isr = readl(MLC_ISR(host->io_base));
468 if (mlc_isr & MLCISR_DECODER_FAILURE) {
469 mtd->ecc_stats.failed++;
470 dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__);
471 } else if (mlc_isr & MLCISR_ERRORS_DETECTED) {
472 mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1;
473 }
474
475 /* Read 512 + 16 Bytes */
476 if (use_dma) {
477 res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
478 DMA_DEV_TO_MEM);
479 if (res)
480 return res;
481 } else {
482 for (j = 0; j < (512 >> 2); j++) {
483 *((uint32_t *)(buf)) =
484 readl(MLC_BUFF(host->io_base));
485 buf += 4;
486 }
487 }
488 for (j = 0; j < (16 >> 2); j++) {
489 *((uint32_t *)(oobbuf)) =
490 readl(MLC_BUFF(host->io_base));
491 oobbuf += 4;
492 }
493 }
494
495 if (use_dma && !dma_mapped)
496 memcpy(buf, dma_buf, mtd->writesize);
497
498 return 0;
499 }
500
lpc32xx_write_page_lowlevel(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)501 static int lpc32xx_write_page_lowlevel(struct nand_chip *chip,
502 const uint8_t *buf, int oob_required,
503 int page)
504 {
505 struct mtd_info *mtd = nand_to_mtd(chip);
506 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
507 const uint8_t *oobbuf = chip->oob_poi;
508 uint8_t *dma_buf = (uint8_t *)buf;
509 int res;
510 int i, j;
511
512 if (use_dma && (void *)buf >= high_memory) {
513 dma_buf = host->dma_buf;
514 memcpy(dma_buf, buf, mtd->writesize);
515 }
516
517 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
518
519 for (i = 0; i < host->mlcsubpages; i++) {
520 /* Start Encode */
521 writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
522
523 /* Write 512 + 6 Bytes to Buffer */
524 if (use_dma) {
525 res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
526 DMA_MEM_TO_DEV);
527 if (res)
528 return res;
529 } else {
530 for (j = 0; j < (512 >> 2); j++) {
531 writel(*((uint32_t *)(buf)),
532 MLC_BUFF(host->io_base));
533 buf += 4;
534 }
535 }
536 writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
537 oobbuf += 4;
538 writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
539 oobbuf += 12;
540
541 /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */
542 writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
543
544 /* Wait for Controller Ready */
545 lpc32xx_waitfunc_controller(chip);
546 }
547
548 return nand_prog_page_end_op(chip);
549 }
550
lpc32xx_read_oob(struct nand_chip * chip,int page)551 static int lpc32xx_read_oob(struct nand_chip *chip, int page)
552 {
553 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
554
555 /* Read whole page - necessary with MLC controller! */
556 lpc32xx_read_page(chip, host->dummy_buf, 1, page);
557
558 return 0;
559 }
560
lpc32xx_write_oob(struct nand_chip * chip,int page)561 static int lpc32xx_write_oob(struct nand_chip *chip, int page)
562 {
563 /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */
564 return 0;
565 }
566
567 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
lpc32xx_ecc_enable(struct nand_chip * chip,int mode)568 static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode)
569 {
570 /* Always enabled! */
571 }
572
lpc32xx_dma_setup(struct lpc32xx_nand_host * host)573 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
574 {
575 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
576 dma_cap_mask_t mask;
577
578 if (!host->pdata || !host->pdata->dma_filter) {
579 dev_err(mtd->dev.parent, "no DMA platform data\n");
580 return -ENOENT;
581 }
582
583 dma_cap_zero(mask);
584 dma_cap_set(DMA_SLAVE, mask);
585 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
586 "nand-mlc");
587 if (!host->dma_chan) {
588 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
589 return -EBUSY;
590 }
591
592 /*
593 * Set direction to a sensible value even if the dmaengine driver
594 * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x
595 * driver criticizes it as "alien transfer direction".
596 */
597 host->dma_slave_config.direction = DMA_DEV_TO_MEM;
598 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
599 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
600 host->dma_slave_config.src_maxburst = 128;
601 host->dma_slave_config.dst_maxburst = 128;
602 /* DMA controller does flow control: */
603 host->dma_slave_config.device_fc = false;
604 host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
605 host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
606 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
607 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
608 goto out1;
609 }
610
611 return 0;
612 out1:
613 dma_release_channel(host->dma_chan);
614 return -ENXIO;
615 }
616
lpc32xx_parse_dt(struct device * dev)617 static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
618 {
619 struct lpc32xx_nand_cfg_mlc *ncfg;
620 struct device_node *np = dev->of_node;
621
622 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
623 if (!ncfg)
624 return NULL;
625
626 of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay);
627 of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay);
628 of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta);
629 of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high);
630 of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low);
631 of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high);
632 of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low);
633
634 if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta ||
635 !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high ||
636 !ncfg->wr_low) {
637 dev_err(dev, "chip parameters not specified correctly\n");
638 return NULL;
639 }
640
641 ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
642
643 return ncfg;
644 }
645
lpc32xx_nand_attach_chip(struct nand_chip * chip)646 static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
647 {
648 struct mtd_info *mtd = nand_to_mtd(chip);
649 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
650 struct device *dev = &host->pdev->dev;
651
652 host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
653 if (!host->dma_buf)
654 return -ENOMEM;
655
656 host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
657 if (!host->dummy_buf)
658 return -ENOMEM;
659
660 chip->ecc.mode = NAND_ECC_HW;
661 chip->ecc.size = 512;
662 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
663 host->mlcsubpages = mtd->writesize / 512;
664
665 return 0;
666 }
667
668 static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
669 .attach_chip = lpc32xx_nand_attach_chip,
670 };
671
672 /*
673 * Probe for NAND controller
674 */
lpc32xx_nand_probe(struct platform_device * pdev)675 static int lpc32xx_nand_probe(struct platform_device *pdev)
676 {
677 struct lpc32xx_nand_host *host;
678 struct mtd_info *mtd;
679 struct nand_chip *nand_chip;
680 struct resource *rc;
681 int res;
682
683 /* Allocate memory for the device structure (and zero it) */
684 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
685 if (!host)
686 return -ENOMEM;
687
688 host->pdev = pdev;
689
690 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
691 host->io_base = devm_ioremap_resource(&pdev->dev, rc);
692 if (IS_ERR(host->io_base))
693 return PTR_ERR(host->io_base);
694
695 host->io_base_phy = rc->start;
696
697 nand_chip = &host->nand_chip;
698 mtd = nand_to_mtd(nand_chip);
699 if (pdev->dev.of_node)
700 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
701 if (!host->ncfg) {
702 dev_err(&pdev->dev,
703 "Missing or bad NAND config from device tree\n");
704 return -ENOENT;
705 }
706 if (host->ncfg->wp_gpio == -EPROBE_DEFER)
707 return -EPROBE_DEFER;
708 if (gpio_is_valid(host->ncfg->wp_gpio) &&
709 gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
710 dev_err(&pdev->dev, "GPIO not available\n");
711 return -EBUSY;
712 }
713 lpc32xx_wp_disable(host);
714
715 host->pdata = dev_get_platdata(&pdev->dev);
716
717 /* link the private data structures */
718 nand_set_controller_data(nand_chip, host);
719 nand_set_flash_node(nand_chip, pdev->dev.of_node);
720 mtd->dev.parent = &pdev->dev;
721
722 /* Get NAND clock */
723 host->clk = clk_get(&pdev->dev, NULL);
724 if (IS_ERR(host->clk)) {
725 dev_err(&pdev->dev, "Clock initialization failure\n");
726 res = -ENOENT;
727 goto free_gpio;
728 }
729 res = clk_prepare_enable(host->clk);
730 if (res)
731 goto put_clk;
732
733 nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
734 nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
735 nand_chip->legacy.chip_delay = 25; /* us */
736 nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
737 nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
738
739 /* Init NAND controller */
740 lpc32xx_nand_setup(host);
741
742 platform_set_drvdata(pdev, host);
743
744 /* Initialize function pointers */
745 nand_chip->ecc.hwctl = lpc32xx_ecc_enable;
746 nand_chip->ecc.read_page_raw = lpc32xx_read_page;
747 nand_chip->ecc.read_page = lpc32xx_read_page;
748 nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
749 nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel;
750 nand_chip->ecc.write_oob = lpc32xx_write_oob;
751 nand_chip->ecc.read_oob = lpc32xx_read_oob;
752 nand_chip->ecc.strength = 4;
753 nand_chip->ecc.bytes = 10;
754 nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
755
756 nand_chip->options = NAND_NO_SUBPAGE_WRITE;
757 nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
758 nand_chip->bbt_td = &lpc32xx_nand_bbt;
759 nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
760
761 if (use_dma) {
762 res = lpc32xx_dma_setup(host);
763 if (res) {
764 res = -EIO;
765 goto unprepare_clk;
766 }
767 }
768
769 /* initially clear interrupt status */
770 readb(MLC_IRQ_SR(host->io_base));
771
772 init_completion(&host->comp_nand);
773 init_completion(&host->comp_controller);
774
775 host->irq = platform_get_irq(pdev, 0);
776 if (host->irq < 0) {
777 dev_err(&pdev->dev, "failed to get platform irq\n");
778 res = -EINVAL;
779 goto release_dma_chan;
780 }
781
782 if (request_irq(host->irq, &lpc3xxx_nand_irq,
783 IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
784 dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
785 res = -ENXIO;
786 goto release_dma_chan;
787 }
788
789 /*
790 * Scan to find existence of the device and get the type of NAND device:
791 * SMALL block or LARGE block.
792 */
793 nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
794 res = nand_scan(nand_chip, 1);
795 if (res)
796 goto free_irq;
797
798 mtd->name = DRV_NAME;
799
800 res = mtd_device_register(mtd, host->ncfg->parts,
801 host->ncfg->num_parts);
802 if (res)
803 goto cleanup_nand;
804
805 return 0;
806
807 cleanup_nand:
808 nand_cleanup(nand_chip);
809 free_irq:
810 free_irq(host->irq, host);
811 release_dma_chan:
812 if (use_dma)
813 dma_release_channel(host->dma_chan);
814 unprepare_clk:
815 clk_disable_unprepare(host->clk);
816 put_clk:
817 clk_put(host->clk);
818 free_gpio:
819 lpc32xx_wp_enable(host);
820 gpio_free(host->ncfg->wp_gpio);
821
822 return res;
823 }
824
825 /*
826 * Remove NAND device
827 */
lpc32xx_nand_remove(struct platform_device * pdev)828 static int lpc32xx_nand_remove(struct platform_device *pdev)
829 {
830 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
831
832 nand_release(&host->nand_chip);
833 free_irq(host->irq, host);
834 if (use_dma)
835 dma_release_channel(host->dma_chan);
836
837 clk_disable_unprepare(host->clk);
838 clk_put(host->clk);
839
840 lpc32xx_wp_enable(host);
841 gpio_free(host->ncfg->wp_gpio);
842
843 return 0;
844 }
845
846 #ifdef CONFIG_PM
lpc32xx_nand_resume(struct platform_device * pdev)847 static int lpc32xx_nand_resume(struct platform_device *pdev)
848 {
849 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
850 int ret;
851
852 /* Re-enable NAND clock */
853 ret = clk_prepare_enable(host->clk);
854 if (ret)
855 return ret;
856
857 /* Fresh init of NAND controller */
858 lpc32xx_nand_setup(host);
859
860 /* Disable write protect */
861 lpc32xx_wp_disable(host);
862
863 return 0;
864 }
865
lpc32xx_nand_suspend(struct platform_device * pdev,pm_message_t pm)866 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
867 {
868 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
869
870 /* Enable write protect for safety */
871 lpc32xx_wp_enable(host);
872
873 /* Disable clock */
874 clk_disable_unprepare(host->clk);
875 return 0;
876 }
877
878 #else
879 #define lpc32xx_nand_resume NULL
880 #define lpc32xx_nand_suspend NULL
881 #endif
882
883 static const struct of_device_id lpc32xx_nand_match[] = {
884 { .compatible = "nxp,lpc3220-mlc" },
885 { /* sentinel */ },
886 };
887 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
888
889 static struct platform_driver lpc32xx_nand_driver = {
890 .probe = lpc32xx_nand_probe,
891 .remove = lpc32xx_nand_remove,
892 .resume = lpc32xx_nand_resume,
893 .suspend = lpc32xx_nand_suspend,
894 .driver = {
895 .name = DRV_NAME,
896 .of_match_table = lpc32xx_nand_match,
897 },
898 };
899
900 module_platform_driver(lpc32xx_nand_driver);
901
902 MODULE_LICENSE("GPL");
903 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
904 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller");
905