1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Bayi Cheng <bayi.cheng@mediatek.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/math64.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/partitions.h>
23 #include <linux/mtd/spi-nor.h>
24
25 #define MTK_NOR_CMD_REG 0x00
26 #define MTK_NOR_CNT_REG 0x04
27 #define MTK_NOR_RDSR_REG 0x08
28 #define MTK_NOR_RDATA_REG 0x0c
29 #define MTK_NOR_RADR0_REG 0x10
30 #define MTK_NOR_RADR1_REG 0x14
31 #define MTK_NOR_RADR2_REG 0x18
32 #define MTK_NOR_WDATA_REG 0x1c
33 #define MTK_NOR_PRGDATA0_REG 0x20
34 #define MTK_NOR_PRGDATA1_REG 0x24
35 #define MTK_NOR_PRGDATA2_REG 0x28
36 #define MTK_NOR_PRGDATA3_REG 0x2c
37 #define MTK_NOR_PRGDATA4_REG 0x30
38 #define MTK_NOR_PRGDATA5_REG 0x34
39 #define MTK_NOR_SHREG0_REG 0x38
40 #define MTK_NOR_SHREG1_REG 0x3c
41 #define MTK_NOR_SHREG2_REG 0x40
42 #define MTK_NOR_SHREG3_REG 0x44
43 #define MTK_NOR_SHREG4_REG 0x48
44 #define MTK_NOR_SHREG5_REG 0x4c
45 #define MTK_NOR_SHREG6_REG 0x50
46 #define MTK_NOR_SHREG7_REG 0x54
47 #define MTK_NOR_SHREG8_REG 0x58
48 #define MTK_NOR_SHREG9_REG 0x5c
49 #define MTK_NOR_CFG1_REG 0x60
50 #define MTK_NOR_CFG2_REG 0x64
51 #define MTK_NOR_CFG3_REG 0x68
52 #define MTK_NOR_STATUS0_REG 0x70
53 #define MTK_NOR_STATUS1_REG 0x74
54 #define MTK_NOR_STATUS2_REG 0x78
55 #define MTK_NOR_STATUS3_REG 0x7c
56 #define MTK_NOR_FLHCFG_REG 0x84
57 #define MTK_NOR_TIME_REG 0x94
58 #define MTK_NOR_PP_DATA_REG 0x98
59 #define MTK_NOR_PREBUF_STUS_REG 0x9c
60 #define MTK_NOR_DELSEL0_REG 0xa0
61 #define MTK_NOR_DELSEL1_REG 0xa4
62 #define MTK_NOR_INTRSTUS_REG 0xa8
63 #define MTK_NOR_INTREN_REG 0xac
64 #define MTK_NOR_CHKSUM_CTL_REG 0xb8
65 #define MTK_NOR_CHKSUM_REG 0xbc
66 #define MTK_NOR_CMD2_REG 0xc0
67 #define MTK_NOR_WRPROT_REG 0xc4
68 #define MTK_NOR_RADR3_REG 0xc8
69 #define MTK_NOR_DUAL_REG 0xcc
70 #define MTK_NOR_DELSEL2_REG 0xd0
71 #define MTK_NOR_DELSEL3_REG 0xd4
72 #define MTK_NOR_DELSEL4_REG 0xd8
73
74 /* commands for mtk nor controller */
75 #define MTK_NOR_READ_CMD 0x0
76 #define MTK_NOR_RDSR_CMD 0x2
77 #define MTK_NOR_PRG_CMD 0x4
78 #define MTK_NOR_WR_CMD 0x10
79 #define MTK_NOR_PIO_WR_CMD 0x90
80 #define MTK_NOR_WRSR_CMD 0x20
81 #define MTK_NOR_PIO_READ_CMD 0x81
82 #define MTK_NOR_WR_BUF_ENABLE 0x1
83 #define MTK_NOR_WR_BUF_DISABLE 0x0
84 #define MTK_NOR_ENABLE_SF_CMD 0x30
85 #define MTK_NOR_DUAD_ADDR_EN 0x8
86 #define MTK_NOR_QUAD_READ_EN 0x4
87 #define MTK_NOR_DUAL_ADDR_EN 0x2
88 #define MTK_NOR_DUAL_READ_EN 0x1
89 #define MTK_NOR_DUAL_DISABLE 0x0
90 #define MTK_NOR_FAST_READ 0x1
91
92 #define SFLASH_WRBUF_SIZE 128
93
94 /* Can shift up to 48 bits (6 bytes) of TX/RX */
95 #define MTK_NOR_MAX_RX_TX_SHIFT 6
96 /* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
97 #define MTK_NOR_MAX_SHIFT 7
98 /* nor controller 4-byte address mode enable bit */
99 #define MTK_NOR_4B_ADDR_EN BIT(4)
100
101 /* Helpers for accessing the program data / shift data registers */
102 #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
103 #define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
104
105 struct mtk_nor {
106 struct spi_nor nor;
107 struct device *dev;
108 void __iomem *base; /* nor flash base address */
109 struct clk *spi_clk;
110 struct clk *nor_clk;
111 };
112
mtk_nor_set_read_mode(struct mtk_nor * mtk_nor)113 static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor)
114 {
115 struct spi_nor *nor = &mtk_nor->nor;
116
117 switch (nor->read_proto) {
118 case SNOR_PROTO_1_1_1:
119 writeb(nor->read_opcode, mtk_nor->base +
120 MTK_NOR_PRGDATA3_REG);
121 writeb(MTK_NOR_FAST_READ, mtk_nor->base +
122 MTK_NOR_CFG1_REG);
123 break;
124 case SNOR_PROTO_1_1_2:
125 writeb(nor->read_opcode, mtk_nor->base +
126 MTK_NOR_PRGDATA3_REG);
127 writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base +
128 MTK_NOR_DUAL_REG);
129 break;
130 case SNOR_PROTO_1_1_4:
131 writeb(nor->read_opcode, mtk_nor->base +
132 MTK_NOR_PRGDATA4_REG);
133 writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base +
134 MTK_NOR_DUAL_REG);
135 break;
136 default:
137 writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base +
138 MTK_NOR_DUAL_REG);
139 break;
140 }
141 }
142
mtk_nor_execute_cmd(struct mtk_nor * mtk_nor,u8 cmdval)143 static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
144 {
145 int reg;
146 u8 val = cmdval & 0x1f;
147
148 writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG);
149 return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg,
150 !(reg & val), 100, 10000);
151 }
152
mtk_nor_do_tx_rx(struct mtk_nor * mtk_nor,u8 op,u8 * tx,int txlen,u8 * rx,int rxlen)153 static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
154 u8 *tx, int txlen, u8 *rx, int rxlen)
155 {
156 int len = 1 + txlen + rxlen;
157 int i, ret, idx;
158
159 if (len > MTK_NOR_MAX_SHIFT)
160 return -EINVAL;
161
162 writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG);
163
164 /* start at PRGDATA5, go down to PRGDATA0 */
165 idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
166
167 /* opcode */
168 writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx));
169 idx--;
170
171 /* program TX data */
172 for (i = 0; i < txlen; i++, idx--)
173 writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx));
174
175 /* clear out rest of TX registers */
176 while (idx >= 0) {
177 writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx));
178 idx--;
179 }
180
181 ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD);
182 if (ret)
183 return ret;
184
185 /* restart at first RX byte */
186 idx = rxlen - 1;
187
188 /* read out RX data */
189 for (i = 0; i < rxlen; i++, idx--)
190 rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx));
191
192 return 0;
193 }
194
195 /* Do a WRSR (Write Status Register) command */
mtk_nor_wr_sr(struct mtk_nor * mtk_nor,u8 sr)196 static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr)
197 {
198 writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
199 writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
200 return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD);
201 }
202
mtk_nor_write_buffer_enable(struct mtk_nor * mtk_nor)203 static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor)
204 {
205 u8 reg;
206
207 /* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
208 * 0: pre-fetch buffer use for read
209 * 1: pre-fetch buffer use for page program
210 */
211 writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
212 return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
213 0x01 == (reg & 0x01), 100, 10000);
214 }
215
mtk_nor_write_buffer_disable(struct mtk_nor * mtk_nor)216 static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor)
217 {
218 u8 reg;
219
220 writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
221 return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
222 MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
223 10000);
224 }
225
mtk_nor_set_addr_width(struct mtk_nor * mtk_nor)226 static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor)
227 {
228 u8 val;
229 struct spi_nor *nor = &mtk_nor->nor;
230
231 val = readb(mtk_nor->base + MTK_NOR_DUAL_REG);
232
233 switch (nor->addr_width) {
234 case 3:
235 val &= ~MTK_NOR_4B_ADDR_EN;
236 break;
237 case 4:
238 val |= MTK_NOR_4B_ADDR_EN;
239 break;
240 default:
241 dev_warn(mtk_nor->dev, "Unexpected address width %u.\n",
242 nor->addr_width);
243 break;
244 }
245
246 writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG);
247 }
248
mtk_nor_set_addr(struct mtk_nor * mtk_nor,u32 addr)249 static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr)
250 {
251 int i;
252
253 mtk_nor_set_addr_width(mtk_nor);
254
255 for (i = 0; i < 3; i++) {
256 writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4);
257 addr >>= 8;
258 }
259 /* Last register is non-contiguous */
260 writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG);
261 }
262
mtk_nor_read(struct spi_nor * nor,loff_t from,size_t length,u_char * buffer)263 static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length,
264 u_char *buffer)
265 {
266 int i, ret;
267 int addr = (int)from;
268 u8 *buf = (u8 *)buffer;
269 struct mtk_nor *mtk_nor = nor->priv;
270
271 /* set mode for fast read mode ,dual mode or quad mode */
272 mtk_nor_set_read_mode(mtk_nor);
273 mtk_nor_set_addr(mtk_nor, addr);
274
275 for (i = 0; i < length; i++) {
276 ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD);
277 if (ret < 0)
278 return ret;
279 buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG);
280 }
281 return length;
282 }
283
mtk_nor_write_single_byte(struct mtk_nor * mtk_nor,int addr,int length,u8 * data)284 static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor,
285 int addr, int length, u8 *data)
286 {
287 int i, ret;
288
289 mtk_nor_set_addr(mtk_nor, addr);
290
291 for (i = 0; i < length; i++) {
292 writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG);
293 ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD);
294 if (ret < 0)
295 return ret;
296 }
297 return 0;
298 }
299
mtk_nor_write_buffer(struct mtk_nor * mtk_nor,int addr,const u8 * buf)300 static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr,
301 const u8 *buf)
302 {
303 int i, bufidx, data;
304
305 mtk_nor_set_addr(mtk_nor, addr);
306
307 bufidx = 0;
308 for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
309 data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
310 buf[bufidx + 1]<<8 | buf[bufidx];
311 bufidx += 4;
312 writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG);
313 }
314 return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD);
315 }
316
mtk_nor_write(struct spi_nor * nor,loff_t to,size_t len,const u_char * buf)317 static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
318 const u_char *buf)
319 {
320 int ret;
321 struct mtk_nor *mtk_nor = nor->priv;
322 size_t i;
323
324 ret = mtk_nor_write_buffer_enable(mtk_nor);
325 if (ret < 0) {
326 dev_warn(mtk_nor->dev, "write buffer enable failed!\n");
327 return ret;
328 }
329
330 for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
331 ret = mtk_nor_write_buffer(mtk_nor, to, buf);
332 if (ret < 0) {
333 dev_err(mtk_nor->dev, "write buffer failed!\n");
334 return ret;
335 }
336 to += SFLASH_WRBUF_SIZE;
337 buf += SFLASH_WRBUF_SIZE;
338 }
339 ret = mtk_nor_write_buffer_disable(mtk_nor);
340 if (ret < 0) {
341 dev_warn(mtk_nor->dev, "write buffer disable failed!\n");
342 return ret;
343 }
344
345 if (i < len) {
346 ret = mtk_nor_write_single_byte(mtk_nor, to,
347 (int)(len - i), (u8 *)buf);
348 if (ret < 0) {
349 dev_err(mtk_nor->dev, "write single byte failed!\n");
350 return ret;
351 }
352 }
353
354 return len;
355 }
356
mtk_nor_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)357 static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
358 {
359 int ret;
360 struct mtk_nor *mtk_nor = nor->priv;
361
362 switch (opcode) {
363 case SPINOR_OP_RDSR:
364 ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD);
365 if (ret < 0)
366 return ret;
367 if (len == 1)
368 *buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG);
369 else
370 dev_err(mtk_nor->dev, "len should be 1 for read status!\n");
371 break;
372 default:
373 ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len);
374 break;
375 }
376 return ret;
377 }
378
mtk_nor_write_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)379 static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
380 int len)
381 {
382 int ret;
383 struct mtk_nor *mtk_nor = nor->priv;
384
385 switch (opcode) {
386 case SPINOR_OP_WRSR:
387 /* We only handle 1 byte */
388 ret = mtk_nor_wr_sr(mtk_nor, *buf);
389 break;
390 default:
391 ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0);
392 if (ret)
393 dev_warn(mtk_nor->dev, "write reg failure!\n");
394 break;
395 }
396 return ret;
397 }
398
mtk_nor_disable_clk(struct mtk_nor * mtk_nor)399 static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor)
400 {
401 clk_disable_unprepare(mtk_nor->spi_clk);
402 clk_disable_unprepare(mtk_nor->nor_clk);
403 }
404
mtk_nor_enable_clk(struct mtk_nor * mtk_nor)405 static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
406 {
407 int ret;
408
409 ret = clk_prepare_enable(mtk_nor->spi_clk);
410 if (ret)
411 return ret;
412
413 ret = clk_prepare_enable(mtk_nor->nor_clk);
414 if (ret) {
415 clk_disable_unprepare(mtk_nor->spi_clk);
416 return ret;
417 }
418
419 return 0;
420 }
421
mtk_nor_init(struct mtk_nor * mtk_nor,struct device_node * flash_node)422 static int mtk_nor_init(struct mtk_nor *mtk_nor,
423 struct device_node *flash_node)
424 {
425 const struct spi_nor_hwcaps hwcaps = {
426 .mask = SNOR_HWCAPS_READ |
427 SNOR_HWCAPS_READ_FAST |
428 SNOR_HWCAPS_READ_1_1_2 |
429 SNOR_HWCAPS_PP,
430 };
431 int ret;
432 struct spi_nor *nor;
433
434 /* initialize controller to accept commands */
435 writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG);
436
437 nor = &mtk_nor->nor;
438 nor->dev = mtk_nor->dev;
439 nor->priv = mtk_nor;
440 spi_nor_set_flash_node(nor, flash_node);
441
442 /* fill the hooks to spi nor */
443 nor->read = mtk_nor_read;
444 nor->read_reg = mtk_nor_read_reg;
445 nor->write = mtk_nor_write;
446 nor->write_reg = mtk_nor_write_reg;
447 nor->mtd.name = "mtk_nor";
448 /* initialized with NULL */
449 ret = spi_nor_scan(nor, NULL, &hwcaps);
450 if (ret)
451 return ret;
452
453 return mtd_device_register(&nor->mtd, NULL, 0);
454 }
455
mtk_nor_drv_probe(struct platform_device * pdev)456 static int mtk_nor_drv_probe(struct platform_device *pdev)
457 {
458 struct device_node *flash_np;
459 struct resource *res;
460 int ret;
461 struct mtk_nor *mtk_nor;
462
463 if (!pdev->dev.of_node) {
464 dev_err(&pdev->dev, "No DT found\n");
465 return -EINVAL;
466 }
467
468 mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL);
469 if (!mtk_nor)
470 return -ENOMEM;
471 platform_set_drvdata(pdev, mtk_nor);
472
473 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474 mtk_nor->base = devm_ioremap_resource(&pdev->dev, res);
475 if (IS_ERR(mtk_nor->base))
476 return PTR_ERR(mtk_nor->base);
477
478 mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
479 if (IS_ERR(mtk_nor->spi_clk))
480 return PTR_ERR(mtk_nor->spi_clk);
481
482 mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
483 if (IS_ERR(mtk_nor->nor_clk))
484 return PTR_ERR(mtk_nor->nor_clk);
485
486 mtk_nor->dev = &pdev->dev;
487
488 ret = mtk_nor_enable_clk(mtk_nor);
489 if (ret)
490 return ret;
491
492 /* only support one attached flash */
493 flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
494 if (!flash_np) {
495 dev_err(&pdev->dev, "no SPI flash device to configure\n");
496 ret = -ENODEV;
497 goto nor_free;
498 }
499 ret = mtk_nor_init(mtk_nor, flash_np);
500
501 nor_free:
502 if (ret)
503 mtk_nor_disable_clk(mtk_nor);
504
505 return ret;
506 }
507
mtk_nor_drv_remove(struct platform_device * pdev)508 static int mtk_nor_drv_remove(struct platform_device *pdev)
509 {
510 struct mtk_nor *mtk_nor = platform_get_drvdata(pdev);
511
512 mtk_nor_disable_clk(mtk_nor);
513
514 return 0;
515 }
516
517 #ifdef CONFIG_PM_SLEEP
mtk_nor_suspend(struct device * dev)518 static int mtk_nor_suspend(struct device *dev)
519 {
520 struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
521
522 mtk_nor_disable_clk(mtk_nor);
523
524 return 0;
525 }
526
mtk_nor_resume(struct device * dev)527 static int mtk_nor_resume(struct device *dev)
528 {
529 struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
530
531 return mtk_nor_enable_clk(mtk_nor);
532 }
533
534 static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
535 .suspend = mtk_nor_suspend,
536 .resume = mtk_nor_resume,
537 };
538
539 #define MTK_NOR_DEV_PM_OPS (&mtk_nor_dev_pm_ops)
540 #else
541 #define MTK_NOR_DEV_PM_OPS NULL
542 #endif
543
544 static const struct of_device_id mtk_nor_of_ids[] = {
545 { .compatible = "mediatek,mt8173-nor"},
546 { /* sentinel */ }
547 };
548 MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);
549
550 static struct platform_driver mtk_nor_driver = {
551 .probe = mtk_nor_drv_probe,
552 .remove = mtk_nor_drv_remove,
553 .driver = {
554 .name = "mtk-nor",
555 .pm = MTK_NOR_DEV_PM_OPS,
556 .of_match_table = mtk_nor_of_ids,
557 },
558 };
559
560 module_platform_driver(mtk_nor_driver);
561 MODULE_LICENSE("GPL v2");
562 MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");
563