1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017 Cadence
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
5
6 #include <linux/delay.h>
7 #include <linux/kernel.h>
8 #include <linux/of.h>
9 #include <linux/pci-epc.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/sizes.h>
13
14 #include "pcie-cadence.h"
15
16 #define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
17 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1
18 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3
19
20 /**
21 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
22 * @pcie: Cadence PCIe controller
23 * @max_regions: maximum number of regions supported by hardware
24 * @ob_region_map: bitmask of mapped outbound regions
25 * @ob_addr: base addresses in the AXI bus where the outbound regions start
26 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
27 * dedicated outbound regions is mapped.
28 * @irq_cpu_addr: base address in the CPU space where a write access triggers
29 * the sending of a memory write (MSI) / normal message (legacy
30 * IRQ) TLP through the PCIe bus.
31 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
32 * dedicated outbound region.
33 * @irq_pci_fn: the latest PCI function that has updated the mapping of
34 * the MSI/legacy IRQ dedicated outbound region.
35 * @irq_pending: bitmask of asserted legacy IRQs.
36 */
37 struct cdns_pcie_ep {
38 struct cdns_pcie pcie;
39 u32 max_regions;
40 unsigned long ob_region_map;
41 phys_addr_t *ob_addr;
42 phys_addr_t irq_phys_addr;
43 void __iomem *irq_cpu_addr;
44 u64 irq_pci_addr;
45 u8 irq_pci_fn;
46 u8 irq_pending;
47 };
48
cdns_pcie_ep_write_header(struct pci_epc * epc,u8 fn,struct pci_epf_header * hdr)49 static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
50 struct pci_epf_header *hdr)
51 {
52 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
53 struct cdns_pcie *pcie = &ep->pcie;
54
55 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
56 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
57 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
58 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
59 hdr->subclass_code | hdr->baseclass_code << 8);
60 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
61 hdr->cache_line_size);
62 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
63 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
64
65 /*
66 * Vendor ID can only be modified from function 0, all other functions
67 * use the same vendor ID as function 0.
68 */
69 if (fn == 0) {
70 /* Update the vendor IDs. */
71 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
72 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
73
74 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
75 }
76
77 return 0;
78 }
79
cdns_pcie_ep_set_bar(struct pci_epc * epc,u8 fn,struct pci_epf_bar * epf_bar)80 static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
81 struct pci_epf_bar *epf_bar)
82 {
83 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
84 struct cdns_pcie *pcie = &ep->pcie;
85 dma_addr_t bar_phys = epf_bar->phys_addr;
86 enum pci_barno bar = epf_bar->barno;
87 int flags = epf_bar->flags;
88 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
89 u64 sz;
90
91 /* BAR size is 2^(aperture + 7) */
92 sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
93 /*
94 * roundup_pow_of_two() returns an unsigned long, which is not suited
95 * for 64bit values.
96 */
97 sz = 1ULL << fls64(sz - 1);
98 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
99
100 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
101 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
102 } else {
103 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
104 bool is_64bits = sz > SZ_2G;
105
106 if (is_64bits && (bar & 1))
107 return -EINVAL;
108
109 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
110 epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
111
112 if (is_64bits && is_prefetch)
113 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
114 else if (is_prefetch)
115 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
116 else if (is_64bits)
117 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
118 else
119 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
120 }
121
122 addr0 = lower_32_bits(bar_phys);
123 addr1 = upper_32_bits(bar_phys);
124 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
125 addr0);
126 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
127 addr1);
128
129 if (bar < BAR_4) {
130 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
131 b = bar;
132 } else {
133 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
134 b = bar - BAR_4;
135 }
136
137 cfg = cdns_pcie_readl(pcie, reg);
138 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
139 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
140 cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
141 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
142 cdns_pcie_writel(pcie, reg, cfg);
143
144 return 0;
145 }
146
cdns_pcie_ep_clear_bar(struct pci_epc * epc,u8 fn,struct pci_epf_bar * epf_bar)147 static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
148 struct pci_epf_bar *epf_bar)
149 {
150 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
151 struct cdns_pcie *pcie = &ep->pcie;
152 enum pci_barno bar = epf_bar->barno;
153 u32 reg, cfg, b, ctrl;
154
155 if (bar < BAR_4) {
156 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
157 b = bar;
158 } else {
159 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
160 b = bar - BAR_4;
161 }
162
163 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
164 cfg = cdns_pcie_readl(pcie, reg);
165 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
166 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
167 cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
168 cdns_pcie_writel(pcie, reg, cfg);
169
170 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
171 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
172 }
173
cdns_pcie_ep_map_addr(struct pci_epc * epc,u8 fn,phys_addr_t addr,u64 pci_addr,size_t size)174 static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
175 u64 pci_addr, size_t size)
176 {
177 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
178 struct cdns_pcie *pcie = &ep->pcie;
179 u32 r;
180
181 r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);
182 if (r >= ep->max_regions - 1) {
183 dev_err(&epc->dev, "no free outbound region\n");
184 return -EINVAL;
185 }
186
187 cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);
188
189 set_bit(r, &ep->ob_region_map);
190 ep->ob_addr[r] = addr;
191
192 return 0;
193 }
194
cdns_pcie_ep_unmap_addr(struct pci_epc * epc,u8 fn,phys_addr_t addr)195 static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
196 phys_addr_t addr)
197 {
198 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
199 struct cdns_pcie *pcie = &ep->pcie;
200 u32 r;
201
202 for (r = 0; r < ep->max_regions - 1; r++)
203 if (ep->ob_addr[r] == addr)
204 break;
205
206 if (r == ep->max_regions - 1)
207 return;
208
209 cdns_pcie_reset_outbound_region(pcie, r);
210
211 ep->ob_addr[r] = 0;
212 clear_bit(r, &ep->ob_region_map);
213 }
214
cdns_pcie_ep_set_msi(struct pci_epc * epc,u8 fn,u8 mmc)215 static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
216 {
217 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
218 struct cdns_pcie *pcie = &ep->pcie;
219 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
220 u16 flags;
221
222 /*
223 * Set the Multiple Message Capable bitfield into the Message Control
224 * register.
225 */
226 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
227 flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
228 flags |= PCI_MSI_FLAGS_64BIT;
229 flags &= ~PCI_MSI_FLAGS_MASKBIT;
230 cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
231
232 return 0;
233 }
234
cdns_pcie_ep_get_msi(struct pci_epc * epc,u8 fn)235 static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
236 {
237 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
238 struct cdns_pcie *pcie = &ep->pcie;
239 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
240 u16 flags, mme;
241
242 /* Validate that the MSI feature is actually enabled. */
243 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
244 if (!(flags & PCI_MSI_FLAGS_ENABLE))
245 return -EINVAL;
246
247 /*
248 * Get the Multiple Message Enable bitfield from the Message Control
249 * register.
250 */
251 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
252
253 return mme;
254 }
255
cdns_pcie_ep_assert_intx(struct cdns_pcie_ep * ep,u8 fn,u8 intx,bool is_asserted)256 static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
257 u8 intx, bool is_asserted)
258 {
259 struct cdns_pcie *pcie = &ep->pcie;
260 u32 offset;
261 u16 status;
262 u8 msg_code;
263
264 intx &= 3;
265
266 /* Set the outbound region if needed. */
267 if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
268 ep->irq_pci_fn != fn)) {
269 /* First region was reserved for IRQ writes. */
270 cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, 0,
271 ep->irq_phys_addr);
272 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
273 ep->irq_pci_fn = fn;
274 }
275
276 if (is_asserted) {
277 ep->irq_pending |= BIT(intx);
278 msg_code = MSG_CODE_ASSERT_INTA + intx;
279 } else {
280 ep->irq_pending &= ~BIT(intx);
281 msg_code = MSG_CODE_DEASSERT_INTA + intx;
282 }
283
284 status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
285 if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
286 status ^= PCI_STATUS_INTERRUPT;
287 cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
288 }
289
290 offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
291 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
292 CDNS_PCIE_MSG_NO_DATA;
293 writel(0, ep->irq_cpu_addr + offset);
294 }
295
cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep * ep,u8 fn,u8 intx)296 static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
297 {
298 u16 cmd;
299
300 cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
301 if (cmd & PCI_COMMAND_INTX_DISABLE)
302 return -EINVAL;
303
304 cdns_pcie_ep_assert_intx(ep, fn, intx, true);
305 /*
306 * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
307 * from drivers/pci/dwc/pci-dra7xx.c
308 */
309 mdelay(1);
310 cdns_pcie_ep_assert_intx(ep, fn, intx, false);
311 return 0;
312 }
313
cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep * ep,u8 fn,u8 interrupt_num)314 static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
315 u8 interrupt_num)
316 {
317 struct cdns_pcie *pcie = &ep->pcie;
318 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
319 u16 flags, mme, data, data_mask;
320 u8 msi_count;
321 u64 pci_addr, pci_addr_mask = 0xff;
322
323 /* Check whether the MSI feature has been enabled by the PCI host. */
324 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
325 if (!(flags & PCI_MSI_FLAGS_ENABLE))
326 return -EINVAL;
327
328 /* Get the number of enabled MSIs */
329 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
330 msi_count = 1 << mme;
331 if (!interrupt_num || interrupt_num > msi_count)
332 return -EINVAL;
333
334 /* Compute the data value to be written. */
335 data_mask = msi_count - 1;
336 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
337 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
338
339 /* Get the PCI address where to write the data into. */
340 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
341 pci_addr <<= 32;
342 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
343 pci_addr &= GENMASK_ULL(63, 2);
344
345 /* Set the outbound region if needed. */
346 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
347 ep->irq_pci_fn != fn)) {
348 /* First region was reserved for IRQ writes. */
349 cdns_pcie_set_outbound_region(pcie, fn, 0,
350 false,
351 ep->irq_phys_addr,
352 pci_addr & ~pci_addr_mask,
353 pci_addr_mask + 1);
354 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
355 ep->irq_pci_fn = fn;
356 }
357 writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
358
359 return 0;
360 }
361
cdns_pcie_ep_raise_irq(struct pci_epc * epc,u8 fn,enum pci_epc_irq_type type,u16 interrupt_num)362 static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
363 enum pci_epc_irq_type type,
364 u16 interrupt_num)
365 {
366 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
367
368 switch (type) {
369 case PCI_EPC_IRQ_LEGACY:
370 return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
371
372 case PCI_EPC_IRQ_MSI:
373 return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
374
375 default:
376 break;
377 }
378
379 return -EINVAL;
380 }
381
cdns_pcie_ep_start(struct pci_epc * epc)382 static int cdns_pcie_ep_start(struct pci_epc *epc)
383 {
384 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
385 struct cdns_pcie *pcie = &ep->pcie;
386 struct pci_epf *epf;
387 u32 cfg;
388
389 /*
390 * BIT(0) is hardwired to 1, hence function 0 is always enabled
391 * and can't be disabled anyway.
392 */
393 cfg = BIT(0);
394 list_for_each_entry(epf, &epc->pci_epf, list)
395 cfg |= BIT(epf->func_no);
396 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
397
398 return 0;
399 }
400
401 static const struct pci_epc_features cdns_pcie_epc_features = {
402 .linkup_notifier = false,
403 .msi_capable = true,
404 .msix_capable = false,
405 };
406
407 static const struct pci_epc_features*
cdns_pcie_ep_get_features(struct pci_epc * epc,u8 func_no)408 cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
409 {
410 return &cdns_pcie_epc_features;
411 }
412
413 static const struct pci_epc_ops cdns_pcie_epc_ops = {
414 .write_header = cdns_pcie_ep_write_header,
415 .set_bar = cdns_pcie_ep_set_bar,
416 .clear_bar = cdns_pcie_ep_clear_bar,
417 .map_addr = cdns_pcie_ep_map_addr,
418 .unmap_addr = cdns_pcie_ep_unmap_addr,
419 .set_msi = cdns_pcie_ep_set_msi,
420 .get_msi = cdns_pcie_ep_get_msi,
421 .raise_irq = cdns_pcie_ep_raise_irq,
422 .start = cdns_pcie_ep_start,
423 .get_features = cdns_pcie_ep_get_features,
424 };
425
426 static const struct of_device_id cdns_pcie_ep_of_match[] = {
427 { .compatible = "cdns,cdns-pcie-ep" },
428
429 { },
430 };
431
cdns_pcie_ep_probe(struct platform_device * pdev)432 static int cdns_pcie_ep_probe(struct platform_device *pdev)
433 {
434 struct device *dev = &pdev->dev;
435 struct device_node *np = dev->of_node;
436 struct cdns_pcie_ep *ep;
437 struct cdns_pcie *pcie;
438 struct pci_epc *epc;
439 struct resource *res;
440 int ret;
441 int phy_count;
442
443 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
444 if (!ep)
445 return -ENOMEM;
446
447 pcie = &ep->pcie;
448 pcie->is_rc = false;
449
450 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
451 pcie->reg_base = devm_ioremap_resource(dev, res);
452 if (IS_ERR(pcie->reg_base)) {
453 dev_err(dev, "missing \"reg\"\n");
454 return PTR_ERR(pcie->reg_base);
455 }
456
457 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
458 if (!res) {
459 dev_err(dev, "missing \"mem\"\n");
460 return -EINVAL;
461 }
462 pcie->mem_res = res;
463
464 ret = of_property_read_u32(np, "cdns,max-outbound-regions",
465 &ep->max_regions);
466 if (ret < 0) {
467 dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
468 return ret;
469 }
470 ep->ob_addr = devm_kcalloc(dev,
471 ep->max_regions, sizeof(*ep->ob_addr),
472 GFP_KERNEL);
473 if (!ep->ob_addr)
474 return -ENOMEM;
475
476 ret = cdns_pcie_init_phy(dev, pcie);
477 if (ret) {
478 dev_err(dev, "failed to init phy\n");
479 return ret;
480 }
481 platform_set_drvdata(pdev, pcie);
482 pm_runtime_enable(dev);
483 ret = pm_runtime_get_sync(dev);
484 if (ret < 0) {
485 dev_err(dev, "pm_runtime_get_sync() failed\n");
486 goto err_get_sync;
487 }
488
489 /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
490 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
491
492 epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
493 if (IS_ERR(epc)) {
494 dev_err(dev, "failed to create epc device\n");
495 ret = PTR_ERR(epc);
496 goto err_init;
497 }
498
499 epc_set_drvdata(epc, ep);
500
501 if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
502 epc->max_functions = 1;
503
504 ret = pci_epc_mem_init(epc, pcie->mem_res->start,
505 resource_size(pcie->mem_res));
506 if (ret < 0) {
507 dev_err(dev, "failed to initialize the memory space\n");
508 goto err_init;
509 }
510
511 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
512 SZ_128K);
513 if (!ep->irq_cpu_addr) {
514 dev_err(dev, "failed to reserve memory space for MSI\n");
515 ret = -ENOMEM;
516 goto free_epc_mem;
517 }
518 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
519 /* Reserve region 0 for IRQs */
520 set_bit(0, &ep->ob_region_map);
521
522 return 0;
523
524 free_epc_mem:
525 pci_epc_mem_exit(epc);
526
527 err_init:
528 pm_runtime_put_sync(dev);
529
530 err_get_sync:
531 pm_runtime_disable(dev);
532 cdns_pcie_disable_phy(pcie);
533 phy_count = pcie->phy_count;
534 while (phy_count--)
535 device_link_del(pcie->link[phy_count]);
536
537 return ret;
538 }
539
cdns_pcie_ep_shutdown(struct platform_device * pdev)540 static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
541 {
542 struct device *dev = &pdev->dev;
543 struct cdns_pcie *pcie = dev_get_drvdata(dev);
544 int ret;
545
546 ret = pm_runtime_put_sync(dev);
547 if (ret < 0)
548 dev_dbg(dev, "pm_runtime_put_sync failed\n");
549
550 pm_runtime_disable(dev);
551
552 cdns_pcie_disable_phy(pcie);
553 }
554
555 static struct platform_driver cdns_pcie_ep_driver = {
556 .driver = {
557 .name = "cdns-pcie-ep",
558 .of_match_table = cdns_pcie_ep_of_match,
559 .pm = &cdns_pcie_pm_ops,
560 },
561 .probe = cdns_pcie_ep_probe,
562 .shutdown = cdns_pcie_ep_shutdown,
563 };
564 builtin_platform_driver(cdns_pcie_ep_driver);
565