1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
5 *
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/irqdomain.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
17 #include <linux/of_address.h>
18 #include <linux/of_pci.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_irq.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/irqchip/chained_irq.h>
24
25 #include "../pci.h"
26
27 /* Bridge core config registers */
28 #define BRCFG_PCIE_RX0 0x00000000
29 #define BRCFG_INTERRUPT 0x00000010
30 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
31
32 /* Egress - Bridge translation registers */
33 #define E_BREG_CAPABILITIES 0x00000200
34 #define E_BREG_CONTROL 0x00000208
35 #define E_BREG_BASE_LO 0x00000210
36 #define E_BREG_BASE_HI 0x00000214
37 #define E_ECAM_CAPABILITIES 0x00000220
38 #define E_ECAM_CONTROL 0x00000228
39 #define E_ECAM_BASE_LO 0x00000230
40 #define E_ECAM_BASE_HI 0x00000234
41
42 /* Ingress - address translations */
43 #define I_MSII_CAPABILITIES 0x00000300
44 #define I_MSII_CONTROL 0x00000308
45 #define I_MSII_BASE_LO 0x00000310
46 #define I_MSII_BASE_HI 0x00000314
47
48 #define I_ISUB_CONTROL 0x000003E8
49 #define SET_ISUB_CONTROL BIT(0)
50 /* Rxed msg fifo - Interrupt status registers */
51 #define MSGF_MISC_STATUS 0x00000400
52 #define MSGF_MISC_MASK 0x00000404
53 #define MSGF_LEG_STATUS 0x00000420
54 #define MSGF_LEG_MASK 0x00000424
55 #define MSGF_MSI_STATUS_LO 0x00000440
56 #define MSGF_MSI_STATUS_HI 0x00000444
57 #define MSGF_MSI_MASK_LO 0x00000448
58 #define MSGF_MSI_MASK_HI 0x0000044C
59
60 /* Msg filter mask bits */
61 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
62 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
63 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
64 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
65 CFG_ENABLE_INT_MSG_FWD | \
66 CFG_ENABLE_ERR_MSG_FWD)
67
68 /* Misc interrupt status mask bits */
69 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
70 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
71 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
72 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
73 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
74 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
75 #define MSGF_MISC_SR_FATAL_AER BIT(16)
76 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
77 #define MSGF_MISC_SR_CORR_AER BIT(18)
78 #define MSGF_MISC_SR_UR_DETECT BIT(20)
79 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
80 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
81 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
82 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
83 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
84
85 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
86 MSGF_MISC_SR_RXMSG_OVER | \
87 MSGF_MISC_SR_SLAVE_ERR | \
88 MSGF_MISC_SR_MASTER_ERR | \
89 MSGF_MISC_SR_I_ADDR_ERR | \
90 MSGF_MISC_SR_E_ADDR_ERR | \
91 MSGF_MISC_SR_FATAL_AER | \
92 MSGF_MISC_SR_NON_FATAL_AER | \
93 MSGF_MISC_SR_CORR_AER | \
94 MSGF_MISC_SR_UR_DETECT | \
95 MSGF_MISC_SR_NON_FATAL_DEV | \
96 MSGF_MISC_SR_FATAL_DEV | \
97 MSGF_MISC_SR_LINK_DOWN | \
98 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
99 MSGF_MSIC_SR_LINK_BWIDTH)
100
101 /* Legacy interrupt status mask bits */
102 #define MSGF_LEG_SR_INTA BIT(0)
103 #define MSGF_LEG_SR_INTB BIT(1)
104 #define MSGF_LEG_SR_INTC BIT(2)
105 #define MSGF_LEG_SR_INTD BIT(3)
106 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
107 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
108
109 /* MSI interrupt status mask bits */
110 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
111 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
112
113 #define MSII_PRESENT BIT(0)
114 #define MSII_ENABLE BIT(0)
115 #define MSII_STATUS_ENABLE BIT(15)
116
117 /* Bridge config interrupt mask */
118 #define BRCFG_INTERRUPT_MASK BIT(0)
119 #define BREG_PRESENT BIT(0)
120 #define BREG_ENABLE BIT(0)
121 #define BREG_ENABLE_FORCE BIT(1)
122
123 /* E_ECAM status mask bits */
124 #define E_ECAM_PRESENT BIT(0)
125 #define E_ECAM_CR_ENABLE BIT(0)
126 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
127 #define E_ECAM_SIZE_SHIFT 16
128 #define ECAM_BUS_LOC_SHIFT 20
129 #define ECAM_DEV_LOC_SHIFT 12
130 #define NWL_ECAM_VALUE_DEFAULT 12
131
132 #define CFG_DMA_REG_BAR GENMASK(2, 0)
133
134 #define INT_PCI_MSI_NR (2 * 32)
135
136 /* Readin the PS_LINKUP */
137 #define PS_LINKUP_OFFSET 0x00000238
138 #define PCIE_PHY_LINKUP_BIT BIT(0)
139 #define PHY_RDY_LINKUP_BIT BIT(1)
140
141 /* Parameters for the waiting for link up routine */
142 #define LINK_WAIT_MAX_RETRIES 10
143 #define LINK_WAIT_USLEEP_MIN 90000
144 #define LINK_WAIT_USLEEP_MAX 100000
145
146 struct nwl_msi { /* MSI information */
147 struct irq_domain *msi_domain;
148 unsigned long *bitmap;
149 struct irq_domain *dev_domain;
150 struct mutex lock; /* protect bitmap variable */
151 int irq_msi0;
152 int irq_msi1;
153 };
154
155 struct nwl_pcie {
156 struct device *dev;
157 void __iomem *breg_base;
158 void __iomem *pcireg_base;
159 void __iomem *ecam_base;
160 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
162 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
163 u32 breg_size;
164 u32 pcie_reg_size;
165 u32 ecam_size;
166 int irq_intx;
167 int irq_misc;
168 u32 ecam_value;
169 u8 last_busno;
170 u8 root_busno;
171 struct nwl_msi msi;
172 struct irq_domain *legacy_irq_domain;
173 struct clk *clk;
174 raw_spinlock_t leg_mask_lock;
175 };
176
nwl_bridge_readl(struct nwl_pcie * pcie,u32 off)177 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
178 {
179 return readl(pcie->breg_base + off);
180 }
181
nwl_bridge_writel(struct nwl_pcie * pcie,u32 val,u32 off)182 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
183 {
184 writel(val, pcie->breg_base + off);
185 }
186
nwl_pcie_link_up(struct nwl_pcie * pcie)187 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
188 {
189 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
190 return true;
191 return false;
192 }
193
nwl_phy_link_up(struct nwl_pcie * pcie)194 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
195 {
196 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
197 return true;
198 return false;
199 }
200
nwl_wait_for_link(struct nwl_pcie * pcie)201 static int nwl_wait_for_link(struct nwl_pcie *pcie)
202 {
203 struct device *dev = pcie->dev;
204 int retries;
205
206 /* check if the link is up or not */
207 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
208 if (nwl_phy_link_up(pcie))
209 return 0;
210 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
211 }
212
213 dev_err(dev, "PHY link never came up\n");
214 return -ETIMEDOUT;
215 }
216
nwl_pcie_valid_device(struct pci_bus * bus,unsigned int devfn)217 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
218 {
219 struct nwl_pcie *pcie = bus->sysdata;
220
221 /* Check link before accessing downstream ports */
222 if (bus->number != pcie->root_busno) {
223 if (!nwl_pcie_link_up(pcie))
224 return false;
225 }
226
227 /* Only one device down on each root port */
228 if (bus->number == pcie->root_busno && devfn > 0)
229 return false;
230
231 return true;
232 }
233
234 /**
235 * nwl_pcie_map_bus - Get configuration base
236 *
237 * @bus: Bus structure of current bus
238 * @devfn: Device/function
239 * @where: Offset from base
240 *
241 * Return: Base address of the configuration space needed to be
242 * accessed.
243 */
nwl_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int where)244 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
245 int where)
246 {
247 struct nwl_pcie *pcie = bus->sysdata;
248 int relbus;
249
250 if (!nwl_pcie_valid_device(bus, devfn))
251 return NULL;
252
253 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
254 (devfn << ECAM_DEV_LOC_SHIFT);
255
256 return pcie->ecam_base + relbus + where;
257 }
258
259 /* PCIe operations */
260 static struct pci_ops nwl_pcie_ops = {
261 .map_bus = nwl_pcie_map_bus,
262 .read = pci_generic_config_read,
263 .write = pci_generic_config_write,
264 };
265
nwl_pcie_misc_handler(int irq,void * data)266 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
267 {
268 struct nwl_pcie *pcie = data;
269 struct device *dev = pcie->dev;
270 u32 misc_stat;
271
272 /* Checking for misc interrupts */
273 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
274 MSGF_MISC_SR_MASKALL;
275 if (!misc_stat)
276 return IRQ_NONE;
277
278 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
279 dev_err(dev, "Received Message FIFO Overflow\n");
280
281 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
282 dev_err(dev, "Slave error\n");
283
284 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
285 dev_err(dev, "Master error\n");
286
287 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
288 dev_err(dev, "In Misc Ingress address translation error\n");
289
290 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
291 dev_err(dev, "In Misc Egress address translation error\n");
292
293 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
294 dev_err(dev, "Fatal Error in AER Capability\n");
295
296 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
297 dev_err(dev, "Non-Fatal Error in AER Capability\n");
298
299 if (misc_stat & MSGF_MISC_SR_CORR_AER)
300 dev_err(dev, "Correctable Error in AER Capability\n");
301
302 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
303 dev_err(dev, "Unsupported request Detected\n");
304
305 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
306 dev_err(dev, "Non-Fatal Error Detected\n");
307
308 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
309 dev_err(dev, "Fatal Error Detected\n");
310
311 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
312 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
313
314 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
315 dev_info(dev, "Link Bandwidth Management Status bit set\n");
316
317 /* Clear misc interrupt status */
318 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
319
320 return IRQ_HANDLED;
321 }
322
nwl_pcie_leg_handler(struct irq_desc * desc)323 static void nwl_pcie_leg_handler(struct irq_desc *desc)
324 {
325 struct irq_chip *chip = irq_desc_get_chip(desc);
326 struct nwl_pcie *pcie;
327 unsigned long status;
328 u32 bit;
329 u32 virq;
330
331 chained_irq_enter(chip, desc);
332 pcie = irq_desc_get_handler_data(desc);
333
334 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
335 MSGF_LEG_SR_MASKALL) != 0) {
336 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
337 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
338 if (virq)
339 generic_handle_irq(virq);
340 }
341 }
342
343 chained_irq_exit(chip, desc);
344 }
345
nwl_pcie_handle_msi_irq(struct nwl_pcie * pcie,u32 status_reg)346 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
347 {
348 struct nwl_msi *msi;
349 unsigned long status;
350 u32 bit;
351 u32 virq;
352
353 msi = &pcie->msi;
354
355 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
356 for_each_set_bit(bit, &status, 32) {
357 nwl_bridge_writel(pcie, 1 << bit, status_reg);
358 virq = irq_find_mapping(msi->dev_domain, bit);
359 if (virq)
360 generic_handle_irq(virq);
361 }
362 }
363 }
364
nwl_pcie_msi_handler_high(struct irq_desc * desc)365 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
366 {
367 struct irq_chip *chip = irq_desc_get_chip(desc);
368 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
369
370 chained_irq_enter(chip, desc);
371 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
372 chained_irq_exit(chip, desc);
373 }
374
nwl_pcie_msi_handler_low(struct irq_desc * desc)375 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
376 {
377 struct irq_chip *chip = irq_desc_get_chip(desc);
378 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
379
380 chained_irq_enter(chip, desc);
381 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
382 chained_irq_exit(chip, desc);
383 }
384
nwl_mask_leg_irq(struct irq_data * data)385 static void nwl_mask_leg_irq(struct irq_data *data)
386 {
387 struct irq_desc *desc = irq_to_desc(data->irq);
388 struct nwl_pcie *pcie;
389 unsigned long flags;
390 u32 mask;
391 u32 val;
392
393 pcie = irq_desc_get_chip_data(desc);
394 mask = 1 << (data->hwirq - 1);
395 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
396 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
397 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
398 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
399 }
400
nwl_unmask_leg_irq(struct irq_data * data)401 static void nwl_unmask_leg_irq(struct irq_data *data)
402 {
403 struct irq_desc *desc = irq_to_desc(data->irq);
404 struct nwl_pcie *pcie;
405 unsigned long flags;
406 u32 mask;
407 u32 val;
408
409 pcie = irq_desc_get_chip_data(desc);
410 mask = 1 << (data->hwirq - 1);
411 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
412 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
413 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
414 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
415 }
416
417 static struct irq_chip nwl_leg_irq_chip = {
418 .name = "nwl_pcie:legacy",
419 .irq_enable = nwl_unmask_leg_irq,
420 .irq_disable = nwl_mask_leg_irq,
421 .irq_mask = nwl_mask_leg_irq,
422 .irq_unmask = nwl_unmask_leg_irq,
423 };
424
nwl_legacy_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)425 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
426 irq_hw_number_t hwirq)
427 {
428 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
429 irq_set_chip_data(irq, domain->host_data);
430 irq_set_status_flags(irq, IRQ_LEVEL);
431
432 return 0;
433 }
434
435 static const struct irq_domain_ops legacy_domain_ops = {
436 .map = nwl_legacy_map,
437 .xlate = pci_irqd_intx_xlate,
438 };
439
440 #ifdef CONFIG_PCI_MSI
441 static struct irq_chip nwl_msi_irq_chip = {
442 .name = "nwl_pcie:msi",
443 .irq_enable = pci_msi_unmask_irq,
444 .irq_disable = pci_msi_mask_irq,
445 .irq_mask = pci_msi_mask_irq,
446 .irq_unmask = pci_msi_unmask_irq,
447 };
448
449 static struct msi_domain_info nwl_msi_domain_info = {
450 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
451 MSI_FLAG_MULTI_PCI_MSI),
452 .chip = &nwl_msi_irq_chip,
453 };
454 #endif
455
nwl_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)456 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
457 {
458 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
459 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
460
461 msg->address_lo = lower_32_bits(msi_addr);
462 msg->address_hi = upper_32_bits(msi_addr);
463 msg->data = data->hwirq;
464 }
465
nwl_msi_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)466 static int nwl_msi_set_affinity(struct irq_data *irq_data,
467 const struct cpumask *mask, bool force)
468 {
469 return -EINVAL;
470 }
471
472 static struct irq_chip nwl_irq_chip = {
473 .name = "Xilinx MSI",
474 .irq_compose_msi_msg = nwl_compose_msi_msg,
475 .irq_set_affinity = nwl_msi_set_affinity,
476 };
477
nwl_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)478 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
479 unsigned int nr_irqs, void *args)
480 {
481 struct nwl_pcie *pcie = domain->host_data;
482 struct nwl_msi *msi = &pcie->msi;
483 int bit;
484 int i;
485
486 mutex_lock(&msi->lock);
487 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
488 get_count_order(nr_irqs));
489 if (bit < 0) {
490 mutex_unlock(&msi->lock);
491 return -ENOSPC;
492 }
493
494 for (i = 0; i < nr_irqs; i++) {
495 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
496 domain->host_data, handle_simple_irq,
497 NULL, NULL);
498 }
499 mutex_unlock(&msi->lock);
500 return 0;
501 }
502
nwl_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)503 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
504 unsigned int nr_irqs)
505 {
506 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
507 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
508 struct nwl_msi *msi = &pcie->msi;
509
510 mutex_lock(&msi->lock);
511 bitmap_release_region(msi->bitmap, data->hwirq,
512 get_count_order(nr_irqs));
513 mutex_unlock(&msi->lock);
514 }
515
516 static const struct irq_domain_ops dev_msi_domain_ops = {
517 .alloc = nwl_irq_domain_alloc,
518 .free = nwl_irq_domain_free,
519 };
520
nwl_pcie_init_msi_irq_domain(struct nwl_pcie * pcie)521 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
522 {
523 #ifdef CONFIG_PCI_MSI
524 struct device *dev = pcie->dev;
525 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
526 struct nwl_msi *msi = &pcie->msi;
527
528 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
529 &dev_msi_domain_ops, pcie);
530 if (!msi->dev_domain) {
531 dev_err(dev, "failed to create dev IRQ domain\n");
532 return -ENOMEM;
533 }
534 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
535 &nwl_msi_domain_info,
536 msi->dev_domain);
537 if (!msi->msi_domain) {
538 dev_err(dev, "failed to create msi IRQ domain\n");
539 irq_domain_remove(msi->dev_domain);
540 return -ENOMEM;
541 }
542 #endif
543 return 0;
544 }
545
nwl_pcie_init_irq_domain(struct nwl_pcie * pcie)546 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
547 {
548 struct device *dev = pcie->dev;
549 struct device_node *node = dev->of_node;
550 struct device_node *legacy_intc_node;
551
552 legacy_intc_node = of_get_next_child(node, NULL);
553 if (!legacy_intc_node) {
554 dev_err(dev, "No legacy intc node found\n");
555 return -EINVAL;
556 }
557
558 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
559 PCI_NUM_INTX,
560 &legacy_domain_ops,
561 pcie);
562 of_node_put(legacy_intc_node);
563 if (!pcie->legacy_irq_domain) {
564 dev_err(dev, "failed to create IRQ domain\n");
565 return -ENOMEM;
566 }
567
568 raw_spin_lock_init(&pcie->leg_mask_lock);
569 nwl_pcie_init_msi_irq_domain(pcie);
570 return 0;
571 }
572
nwl_pcie_enable_msi(struct nwl_pcie * pcie)573 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
574 {
575 struct device *dev = pcie->dev;
576 struct platform_device *pdev = to_platform_device(dev);
577 struct nwl_msi *msi = &pcie->msi;
578 unsigned long base;
579 int ret;
580 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
581
582 mutex_init(&msi->lock);
583
584 msi->bitmap = kzalloc(size, GFP_KERNEL);
585 if (!msi->bitmap)
586 return -ENOMEM;
587
588 /* Get msi_1 IRQ number */
589 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
590 if (msi->irq_msi1 < 0) {
591 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi1);
592 ret = -EINVAL;
593 goto err;
594 }
595
596 irq_set_chained_handler_and_data(msi->irq_msi1,
597 nwl_pcie_msi_handler_high, pcie);
598
599 /* Get msi_0 IRQ number */
600 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
601 if (msi->irq_msi0 < 0) {
602 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi0);
603 ret = -EINVAL;
604 goto err;
605 }
606
607 irq_set_chained_handler_and_data(msi->irq_msi0,
608 nwl_pcie_msi_handler_low, pcie);
609
610 /* Check for msii_present bit */
611 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
612 if (!ret) {
613 dev_err(dev, "MSI not present\n");
614 ret = -EIO;
615 goto err;
616 }
617
618 /* Enable MSII */
619 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
620 MSII_ENABLE, I_MSII_CONTROL);
621
622 /* Enable MSII status */
623 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
624 MSII_STATUS_ENABLE, I_MSII_CONTROL);
625
626 /* setup AFI/FPCI range */
627 base = pcie->phys_pcie_reg_base;
628 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
629 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
630
631 /*
632 * For high range MSI interrupts: disable, clear any pending,
633 * and enable
634 */
635 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
636
637 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
638 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
639
640 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
641
642 /*
643 * For low range MSI interrupts: disable, clear any pending,
644 * and enable
645 */
646 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
647
648 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
649 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
650
651 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
652
653 return 0;
654 err:
655 kfree(msi->bitmap);
656 msi->bitmap = NULL;
657 return ret;
658 }
659
nwl_pcie_bridge_init(struct nwl_pcie * pcie)660 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
661 {
662 struct device *dev = pcie->dev;
663 struct platform_device *pdev = to_platform_device(dev);
664 u32 breg_val, ecam_val, first_busno = 0;
665 int err;
666
667 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
668 if (!breg_val) {
669 dev_err(dev, "BREG is not present\n");
670 return breg_val;
671 }
672
673 /* Write bridge_off to breg base */
674 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
675 E_BREG_BASE_LO);
676 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
677 E_BREG_BASE_HI);
678
679 /* Enable BREG */
680 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
681 E_BREG_CONTROL);
682
683 /* Disable DMA channel registers */
684 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
685 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
686
687 /* Enable Ingress subtractive decode translation */
688 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
689
690 /* Enable msg filtering details */
691 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
692 BRCFG_PCIE_RX_MSG_FILTER);
693
694 err = nwl_wait_for_link(pcie);
695 if (err)
696 return err;
697
698 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
699 if (!ecam_val) {
700 dev_err(dev, "ECAM is not present\n");
701 return ecam_val;
702 }
703
704 /* Enable ECAM */
705 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
706 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
707
708 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
709 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
710 E_ECAM_CONTROL);
711
712 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
713 E_ECAM_BASE_LO);
714 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
715 E_ECAM_BASE_HI);
716
717 /* Get bus range */
718 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
719 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
720 /* Write primary, secondary and subordinate bus numbers */
721 ecam_val = first_busno;
722 ecam_val |= (first_busno + 1) << 8;
723 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
724 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
725
726 if (nwl_pcie_link_up(pcie))
727 dev_info(dev, "Link is UP\n");
728 else
729 dev_info(dev, "Link is DOWN\n");
730
731 /* Get misc IRQ number */
732 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
733 if (pcie->irq_misc < 0) {
734 dev_err(dev, "failed to get misc IRQ %d\n",
735 pcie->irq_misc);
736 return -EINVAL;
737 }
738
739 err = devm_request_irq(dev, pcie->irq_misc,
740 nwl_pcie_misc_handler, IRQF_SHARED,
741 "nwl_pcie:misc", pcie);
742 if (err) {
743 dev_err(dev, "fail to register misc IRQ#%d\n",
744 pcie->irq_misc);
745 return err;
746 }
747
748 /* Disable all misc interrupts */
749 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
750
751 /* Clear pending misc interrupts */
752 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
753 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
754
755 /* Enable all misc interrupts */
756 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
757
758
759 /* Disable all legacy interrupts */
760 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
761
762 /* Clear pending legacy interrupts */
763 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
764 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
765
766 /* Enable all legacy interrupts */
767 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
768
769 /* Enable the bridge config interrupt */
770 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
771 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
772
773 return 0;
774 }
775
nwl_pcie_parse_dt(struct nwl_pcie * pcie,struct platform_device * pdev)776 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
777 struct platform_device *pdev)
778 {
779 struct device *dev = pcie->dev;
780 struct resource *res;
781
782 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
783 pcie->breg_base = devm_ioremap_resource(dev, res);
784 if (IS_ERR(pcie->breg_base))
785 return PTR_ERR(pcie->breg_base);
786 pcie->phys_breg_base = res->start;
787
788 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
789 pcie->pcireg_base = devm_ioremap_resource(dev, res);
790 if (IS_ERR(pcie->pcireg_base))
791 return PTR_ERR(pcie->pcireg_base);
792 pcie->phys_pcie_reg_base = res->start;
793
794 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
795 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
796 if (IS_ERR(pcie->ecam_base))
797 return PTR_ERR(pcie->ecam_base);
798 pcie->phys_ecam_base = res->start;
799
800 /* Get intx IRQ number */
801 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
802 if (pcie->irq_intx < 0) {
803 dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx);
804 return pcie->irq_intx;
805 }
806
807 irq_set_chained_handler_and_data(pcie->irq_intx,
808 nwl_pcie_leg_handler, pcie);
809
810 return 0;
811 }
812
813 static const struct of_device_id nwl_pcie_of_match[] = {
814 { .compatible = "xlnx,nwl-pcie-2.11", },
815 {}
816 };
817
nwl_pcie_probe(struct platform_device * pdev)818 static int nwl_pcie_probe(struct platform_device *pdev)
819 {
820 struct device *dev = &pdev->dev;
821 struct nwl_pcie *pcie;
822 struct pci_bus *bus;
823 struct pci_bus *child;
824 struct pci_host_bridge *bridge;
825 int err;
826 resource_size_t iobase = 0;
827 LIST_HEAD(res);
828
829 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
830 if (!bridge)
831 return -ENODEV;
832
833 pcie = pci_host_bridge_priv(bridge);
834
835 pcie->dev = dev;
836 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
837
838 err = nwl_pcie_parse_dt(pcie, pdev);
839 if (err) {
840 dev_err(dev, "Parsing DT failed\n");
841 return err;
842 }
843
844 pcie->clk = devm_clk_get(dev, NULL);
845 if (IS_ERR(pcie->clk))
846 return PTR_ERR(pcie->clk);
847
848 err = clk_prepare_enable(pcie->clk);
849 if (err) {
850 dev_err(dev, "can't enable PCIe ref clock\n");
851 return err;
852 }
853
854 err = nwl_pcie_bridge_init(pcie);
855 if (err) {
856 dev_err(dev, "HW Initialization failed\n");
857 return err;
858 }
859
860 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
861 &iobase);
862 if (err) {
863 dev_err(dev, "Getting bridge resources failed\n");
864 return err;
865 }
866
867 err = devm_request_pci_bus_resources(dev, &res);
868 if (err)
869 goto error;
870
871 err = nwl_pcie_init_irq_domain(pcie);
872 if (err) {
873 dev_err(dev, "Failed creating IRQ Domain\n");
874 goto error;
875 }
876
877 list_splice_init(&res, &bridge->windows);
878 bridge->dev.parent = dev;
879 bridge->sysdata = pcie;
880 bridge->busnr = pcie->root_busno;
881 bridge->ops = &nwl_pcie_ops;
882 bridge->map_irq = of_irq_parse_and_map_pci;
883 bridge->swizzle_irq = pci_common_swizzle;
884
885 if (IS_ENABLED(CONFIG_PCI_MSI)) {
886 err = nwl_pcie_enable_msi(pcie);
887 if (err < 0) {
888 dev_err(dev, "failed to enable MSI support: %d\n", err);
889 goto error;
890 }
891 }
892
893 err = pci_scan_root_bus_bridge(bridge);
894 if (err)
895 goto error;
896
897 bus = bridge->bus;
898
899 pci_assign_unassigned_bus_resources(bus);
900 list_for_each_entry(child, &bus->children, node)
901 pcie_bus_configure_settings(child);
902 pci_bus_add_devices(bus);
903 return 0;
904
905 error:
906 pci_free_resource_list(&res);
907 return err;
908 }
909
910 static struct platform_driver nwl_pcie_driver = {
911 .driver = {
912 .name = "nwl-pcie",
913 .suppress_bind_attrs = true,
914 .of_match_table = nwl_pcie_of_match,
915 },
916 .probe = nwl_pcie_probe,
917 };
918 builtin_platform_driver(nwl_pcie_driver);
919