1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
8 */
9
10 #include <linux/err.h>
11 #include <linux/mm.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
21 #include <linux/io.h>
22 #include <linux/acpi_iort.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
26
27 #include "pci.h"
28
29 static int pci_msi_enable = 1;
30 int pci_msi_ignore_mask;
31
32 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33
34 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
pci_msi_setup_msi_irqs(struct pci_dev * dev,int nvec,int type)35 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
36 {
37 struct irq_domain *domain;
38
39 domain = dev_get_msi_domain(&dev->dev);
40 if (domain && irq_domain_is_hierarchy(domain))
41 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
42
43 return arch_setup_msi_irqs(dev, nvec, type);
44 }
45
pci_msi_teardown_msi_irqs(struct pci_dev * dev)46 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
47 {
48 struct irq_domain *domain;
49
50 domain = dev_get_msi_domain(&dev->dev);
51 if (domain && irq_domain_is_hierarchy(domain))
52 msi_domain_free_irqs(domain, &dev->dev);
53 else
54 arch_teardown_msi_irqs(dev);
55 }
56 #else
57 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
58 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
59 #endif
60
61 /* Arch hooks */
62
arch_setup_msi_irq(struct pci_dev * dev,struct msi_desc * desc)63 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
64 {
65 struct msi_controller *chip = dev->bus->msi;
66 int err;
67
68 if (!chip || !chip->setup_irq)
69 return -EINVAL;
70
71 err = chip->setup_irq(chip, dev, desc);
72 if (err < 0)
73 return err;
74
75 irq_set_chip_data(desc->irq, chip);
76
77 return 0;
78 }
79
arch_teardown_msi_irq(unsigned int irq)80 void __weak arch_teardown_msi_irq(unsigned int irq)
81 {
82 struct msi_controller *chip = irq_get_chip_data(irq);
83
84 if (!chip || !chip->teardown_irq)
85 return;
86
87 chip->teardown_irq(chip, irq);
88 }
89
arch_setup_msi_irqs(struct pci_dev * dev,int nvec,int type)90 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
91 {
92 struct msi_controller *chip = dev->bus->msi;
93 struct msi_desc *entry;
94 int ret;
95
96 if (chip && chip->setup_irqs)
97 return chip->setup_irqs(chip, dev, nvec, type);
98 /*
99 * If an architecture wants to support multiple MSI, it needs to
100 * override arch_setup_msi_irqs()
101 */
102 if (type == PCI_CAP_ID_MSI && nvec > 1)
103 return 1;
104
105 for_each_pci_msi_entry(entry, dev) {
106 ret = arch_setup_msi_irq(dev, entry);
107 if (ret < 0)
108 return ret;
109 if (ret > 0)
110 return -ENOSPC;
111 }
112
113 return 0;
114 }
115
116 /*
117 * We have a default implementation available as a separate non-weak
118 * function, as it is used by the Xen x86 PCI code
119 */
default_teardown_msi_irqs(struct pci_dev * dev)120 void default_teardown_msi_irqs(struct pci_dev *dev)
121 {
122 int i;
123 struct msi_desc *entry;
124
125 for_each_pci_msi_entry(entry, dev)
126 if (entry->irq)
127 for (i = 0; i < entry->nvec_used; i++)
128 arch_teardown_msi_irq(entry->irq + i);
129 }
130
arch_teardown_msi_irqs(struct pci_dev * dev)131 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
132 {
133 return default_teardown_msi_irqs(dev);
134 }
135
default_restore_msi_irq(struct pci_dev * dev,int irq)136 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
137 {
138 struct msi_desc *entry;
139
140 entry = NULL;
141 if (dev->msix_enabled) {
142 for_each_pci_msi_entry(entry, dev) {
143 if (irq == entry->irq)
144 break;
145 }
146 } else if (dev->msi_enabled) {
147 entry = irq_get_msi_desc(irq);
148 }
149
150 if (entry)
151 __pci_write_msi_msg(entry, &entry->msg);
152 }
153
arch_restore_msi_irqs(struct pci_dev * dev)154 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
155 {
156 return default_restore_msi_irqs(dev);
157 }
158
msi_mask(unsigned x)159 static inline __attribute_const__ u32 msi_mask(unsigned x)
160 {
161 /* Don't shift by >= width of type */
162 if (x >= 5)
163 return 0xffffffff;
164 return (1 << (1 << x)) - 1;
165 }
166
167 /*
168 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
169 * mask all MSI interrupts by clearing the MSI enable bit does not work
170 * reliably as devices without an INTx disable bit will then generate a
171 * level IRQ which will never be cleared.
172 */
__pci_msi_desc_mask_irq(struct msi_desc * desc,u32 mask,u32 flag)173 u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
174 {
175 u32 mask_bits = desc->masked;
176
177 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
178 return 0;
179
180 mask_bits &= ~mask;
181 mask_bits |= flag;
182 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
183 mask_bits);
184
185 return mask_bits;
186 }
187
msi_mask_irq(struct msi_desc * desc,u32 mask,u32 flag)188 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
189 {
190 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
191 }
192
pci_msix_desc_addr(struct msi_desc * desc)193 static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
194 {
195 if (desc->msi_attrib.is_virtual)
196 return NULL;
197
198 return desc->mask_base +
199 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
200 }
201
202 /*
203 * This internal function does not flush PCI writes to the device.
204 * All users must ensure that they read from the device before either
205 * assuming that the device state is up to date, or returning out of this
206 * file. This saves a few milliseconds when initialising devices with lots
207 * of MSI-X interrupts.
208 */
__pci_msix_desc_mask_irq(struct msi_desc * desc,u32 flag)209 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
210 {
211 u32 mask_bits = desc->masked;
212 void __iomem *desc_addr;
213
214 if (pci_msi_ignore_mask)
215 return 0;
216
217 desc_addr = pci_msix_desc_addr(desc);
218 if (!desc_addr)
219 return 0;
220
221 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
222 if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
223 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
224
225 writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
226
227 return mask_bits;
228 }
229
msix_mask_irq(struct msi_desc * desc,u32 flag)230 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
231 {
232 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
233 }
234
msi_set_mask_bit(struct irq_data * data,u32 flag)235 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
236 {
237 struct msi_desc *desc = irq_data_get_msi_desc(data);
238
239 if (desc->msi_attrib.is_msix) {
240 msix_mask_irq(desc, flag);
241 readl(desc->mask_base); /* Flush write to device */
242 } else {
243 unsigned offset = data->irq - desc->irq;
244 msi_mask_irq(desc, 1 << offset, flag << offset);
245 }
246 }
247
248 /**
249 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
250 * @data: pointer to irqdata associated to that interrupt
251 */
pci_msi_mask_irq(struct irq_data * data)252 void pci_msi_mask_irq(struct irq_data *data)
253 {
254 msi_set_mask_bit(data, 1);
255 }
256 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
257
258 /**
259 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
260 * @data: pointer to irqdata associated to that interrupt
261 */
pci_msi_unmask_irq(struct irq_data * data)262 void pci_msi_unmask_irq(struct irq_data *data)
263 {
264 msi_set_mask_bit(data, 0);
265 }
266 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
267
default_restore_msi_irqs(struct pci_dev * dev)268 void default_restore_msi_irqs(struct pci_dev *dev)
269 {
270 struct msi_desc *entry;
271
272 for_each_pci_msi_entry(entry, dev)
273 default_restore_msi_irq(dev, entry->irq);
274 }
275
__pci_read_msi_msg(struct msi_desc * entry,struct msi_msg * msg)276 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
277 {
278 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
279
280 BUG_ON(dev->current_state != PCI_D0);
281
282 if (entry->msi_attrib.is_msix) {
283 void __iomem *base = pci_msix_desc_addr(entry);
284
285 if (!base) {
286 WARN_ON(1);
287 return;
288 }
289
290 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
291 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
292 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
293 } else {
294 int pos = dev->msi_cap;
295 u16 data;
296
297 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
298 &msg->address_lo);
299 if (entry->msi_attrib.is_64) {
300 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
301 &msg->address_hi);
302 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
303 } else {
304 msg->address_hi = 0;
305 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
306 }
307 msg->data = data;
308 }
309 }
310
__pci_write_msi_msg(struct msi_desc * entry,struct msi_msg * msg)311 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
312 {
313 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
314
315 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
316 /* Don't touch the hardware now */
317 } else if (entry->msi_attrib.is_msix) {
318 void __iomem *base = pci_msix_desc_addr(entry);
319 bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
320
321 if (!base)
322 goto skip;
323
324 /*
325 * The specification mandates that the entry is masked
326 * when the message is modified:
327 *
328 * "If software changes the Address or Data value of an
329 * entry while the entry is unmasked, the result is
330 * undefined."
331 */
332 if (unmasked)
333 __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
334
335 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
336 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
337 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
338
339 if (unmasked)
340 __pci_msix_desc_mask_irq(entry, 0);
341
342 /* Ensure that the writes are visible in the device */
343 readl(base + PCI_MSIX_ENTRY_DATA);
344 } else {
345 int pos = dev->msi_cap;
346 u16 msgctl;
347
348 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
349 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
350 msgctl |= entry->msi_attrib.multiple << 4;
351 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
352
353 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
354 msg->address_lo);
355 if (entry->msi_attrib.is_64) {
356 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
357 msg->address_hi);
358 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
359 msg->data);
360 } else {
361 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
362 msg->data);
363 }
364 /* Ensure that the writes are visible in the device */
365 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
366 }
367
368 skip:
369 entry->msg = *msg;
370
371 if (entry->write_msi_msg)
372 entry->write_msi_msg(entry, entry->write_msi_msg_data);
373
374 }
375
pci_write_msi_msg(unsigned int irq,struct msi_msg * msg)376 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
377 {
378 struct msi_desc *entry = irq_get_msi_desc(irq);
379
380 __pci_write_msi_msg(entry, msg);
381 }
382 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
383
free_msi_irqs(struct pci_dev * dev)384 static void free_msi_irqs(struct pci_dev *dev)
385 {
386 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
387 struct msi_desc *entry, *tmp;
388 struct attribute **msi_attrs;
389 struct device_attribute *dev_attr;
390 int i, count = 0;
391
392 for_each_pci_msi_entry(entry, dev)
393 if (entry->irq)
394 for (i = 0; i < entry->nvec_used; i++)
395 BUG_ON(irq_has_action(entry->irq + i));
396
397 if (dev->msi_irq_groups) {
398 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
399 msi_attrs = dev->msi_irq_groups[0]->attrs;
400 while (msi_attrs[count]) {
401 dev_attr = container_of(msi_attrs[count],
402 struct device_attribute, attr);
403 kfree(dev_attr->attr.name);
404 kfree(dev_attr);
405 ++count;
406 }
407 kfree(msi_attrs);
408 kfree(dev->msi_irq_groups[0]);
409 kfree(dev->msi_irq_groups);
410 dev->msi_irq_groups = NULL;
411 }
412
413 pci_msi_teardown_msi_irqs(dev);
414
415 list_for_each_entry_safe(entry, tmp, msi_list, list) {
416 if (entry->msi_attrib.is_msix) {
417 if (list_is_last(&entry->list, msi_list))
418 iounmap(entry->mask_base);
419 }
420
421 list_del(&entry->list);
422 free_msi_entry(entry);
423 }
424 }
425
pci_intx_for_msi(struct pci_dev * dev,int enable)426 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
427 {
428 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
429 pci_intx(dev, enable);
430 }
431
__pci_restore_msi_state(struct pci_dev * dev)432 static void __pci_restore_msi_state(struct pci_dev *dev)
433 {
434 u16 control;
435 struct msi_desc *entry;
436
437 if (!dev->msi_enabled)
438 return;
439
440 entry = irq_get_msi_desc(dev->irq);
441
442 pci_intx_for_msi(dev, 0);
443 pci_msi_set_enable(dev, 0);
444 arch_restore_msi_irqs(dev);
445
446 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
447 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
448 entry->masked);
449 control &= ~PCI_MSI_FLAGS_QSIZE;
450 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
451 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
452 }
453
__pci_restore_msix_state(struct pci_dev * dev)454 static void __pci_restore_msix_state(struct pci_dev *dev)
455 {
456 struct msi_desc *entry;
457
458 if (!dev->msix_enabled)
459 return;
460 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
461
462 /* route the table */
463 pci_intx_for_msi(dev, 0);
464 pci_msix_clear_and_set_ctrl(dev, 0,
465 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
466
467 arch_restore_msi_irqs(dev);
468 for_each_pci_msi_entry(entry, dev)
469 msix_mask_irq(entry, entry->masked);
470
471 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
472 }
473
pci_restore_msi_state(struct pci_dev * dev)474 void pci_restore_msi_state(struct pci_dev *dev)
475 {
476 __pci_restore_msi_state(dev);
477 __pci_restore_msix_state(dev);
478 }
479 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
480
msi_mode_show(struct device * dev,struct device_attribute * attr,char * buf)481 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
482 char *buf)
483 {
484 struct msi_desc *entry;
485 unsigned long irq;
486 int retval;
487
488 retval = kstrtoul(attr->attr.name, 10, &irq);
489 if (retval)
490 return retval;
491
492 entry = irq_get_msi_desc(irq);
493 if (entry)
494 return sprintf(buf, "%s\n",
495 entry->msi_attrib.is_msix ? "msix" : "msi");
496
497 return -ENODEV;
498 }
499
populate_msi_sysfs(struct pci_dev * pdev)500 static int populate_msi_sysfs(struct pci_dev *pdev)
501 {
502 struct attribute **msi_attrs;
503 struct attribute *msi_attr;
504 struct device_attribute *msi_dev_attr;
505 struct attribute_group *msi_irq_group;
506 const struct attribute_group **msi_irq_groups;
507 struct msi_desc *entry;
508 int ret = -ENOMEM;
509 int num_msi = 0;
510 int count = 0;
511 int i;
512
513 /* Determine how many msi entries we have */
514 for_each_pci_msi_entry(entry, pdev)
515 num_msi += entry->nvec_used;
516 if (!num_msi)
517 return 0;
518
519 /* Dynamically create the MSI attributes for the PCI device */
520 msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
521 if (!msi_attrs)
522 return -ENOMEM;
523 for_each_pci_msi_entry(entry, pdev) {
524 for (i = 0; i < entry->nvec_used; i++) {
525 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
526 if (!msi_dev_attr)
527 goto error_attrs;
528 msi_attrs[count] = &msi_dev_attr->attr;
529
530 sysfs_attr_init(&msi_dev_attr->attr);
531 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
532 entry->irq + i);
533 if (!msi_dev_attr->attr.name)
534 goto error_attrs;
535 msi_dev_attr->attr.mode = S_IRUGO;
536 msi_dev_attr->show = msi_mode_show;
537 ++count;
538 }
539 }
540
541 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
542 if (!msi_irq_group)
543 goto error_attrs;
544 msi_irq_group->name = "msi_irqs";
545 msi_irq_group->attrs = msi_attrs;
546
547 msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
548 if (!msi_irq_groups)
549 goto error_irq_group;
550 msi_irq_groups[0] = msi_irq_group;
551
552 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
553 if (ret)
554 goto error_irq_groups;
555 pdev->msi_irq_groups = msi_irq_groups;
556
557 return 0;
558
559 error_irq_groups:
560 kfree(msi_irq_groups);
561 error_irq_group:
562 kfree(msi_irq_group);
563 error_attrs:
564 count = 0;
565 msi_attr = msi_attrs[count];
566 while (msi_attr) {
567 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
568 kfree(msi_attr->name);
569 kfree(msi_dev_attr);
570 ++count;
571 msi_attr = msi_attrs[count];
572 }
573 kfree(msi_attrs);
574 return ret;
575 }
576
577 static struct msi_desc *
msi_setup_entry(struct pci_dev * dev,int nvec,struct irq_affinity * affd)578 msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
579 {
580 struct irq_affinity_desc *masks = NULL;
581 struct msi_desc *entry;
582 u16 control;
583
584 if (affd)
585 masks = irq_create_affinity_masks(nvec, affd);
586
587 /* MSI Entry Initialization */
588 entry = alloc_msi_entry(&dev->dev, nvec, masks);
589 if (!entry)
590 goto out;
591
592 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
593 /* Lies, damned lies, and MSIs */
594 if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
595 control |= PCI_MSI_FLAGS_MASKBIT;
596
597 entry->msi_attrib.is_msix = 0;
598 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
599 entry->msi_attrib.is_virtual = 0;
600 entry->msi_attrib.entry_nr = 0;
601 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
602 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
603 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
604 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
605
606 if (control & PCI_MSI_FLAGS_64BIT)
607 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
608 else
609 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
610
611 /* Save the initial mask status */
612 if (entry->msi_attrib.maskbit)
613 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
614
615 out:
616 kfree(masks);
617 return entry;
618 }
619
msi_verify_entries(struct pci_dev * dev)620 static int msi_verify_entries(struct pci_dev *dev)
621 {
622 struct msi_desc *entry;
623
624 for_each_pci_msi_entry(entry, dev) {
625 if (!dev->no_64bit_msi || !entry->msg.address_hi)
626 continue;
627 pci_err(dev, "Device has broken 64-bit MSI but arch"
628 " tried to assign one above 4G\n");
629 return -EIO;
630 }
631 return 0;
632 }
633
634 /**
635 * msi_capability_init - configure device's MSI capability structure
636 * @dev: pointer to the pci_dev data structure of MSI device function
637 * @nvec: number of interrupts to allocate
638 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
639 *
640 * Setup the MSI capability structure of the device with the requested
641 * number of interrupts. A return value of zero indicates the successful
642 * setup of an entry with the new MSI IRQ. A negative return value indicates
643 * an error, and a positive return value indicates the number of interrupts
644 * which could have been allocated.
645 */
msi_capability_init(struct pci_dev * dev,int nvec,struct irq_affinity * affd)646 static int msi_capability_init(struct pci_dev *dev, int nvec,
647 struct irq_affinity *affd)
648 {
649 struct msi_desc *entry;
650 int ret;
651 unsigned mask;
652
653 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
654
655 entry = msi_setup_entry(dev, nvec, affd);
656 if (!entry)
657 return -ENOMEM;
658
659 /* All MSIs are unmasked by default; mask them all */
660 mask = msi_mask(entry->msi_attrib.multi_cap);
661 msi_mask_irq(entry, mask, mask);
662
663 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
664
665 /* Configure MSI capability structure */
666 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
667 if (ret) {
668 msi_mask_irq(entry, mask, 0);
669 free_msi_irqs(dev);
670 return ret;
671 }
672
673 ret = msi_verify_entries(dev);
674 if (ret) {
675 msi_mask_irq(entry, mask, 0);
676 free_msi_irqs(dev);
677 return ret;
678 }
679
680 ret = populate_msi_sysfs(dev);
681 if (ret) {
682 msi_mask_irq(entry, mask, 0);
683 free_msi_irqs(dev);
684 return ret;
685 }
686
687 /* Set MSI enabled bits */
688 pci_intx_for_msi(dev, 0);
689 pci_msi_set_enable(dev, 1);
690 dev->msi_enabled = 1;
691
692 pcibios_free_irq(dev);
693 dev->irq = entry->irq;
694 return 0;
695 }
696
msix_map_region(struct pci_dev * dev,unsigned nr_entries)697 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
698 {
699 resource_size_t phys_addr;
700 u32 table_offset;
701 unsigned long flags;
702 u8 bir;
703
704 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
705 &table_offset);
706 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
707 flags = pci_resource_flags(dev, bir);
708 if (!flags || (flags & IORESOURCE_UNSET))
709 return NULL;
710
711 table_offset &= PCI_MSIX_TABLE_OFFSET;
712 phys_addr = pci_resource_start(dev, bir) + table_offset;
713
714 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
715 }
716
msix_setup_entries(struct pci_dev * dev,void __iomem * base,struct msix_entry * entries,int nvec,struct irq_affinity * affd)717 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
718 struct msix_entry *entries, int nvec,
719 struct irq_affinity *affd)
720 {
721 struct irq_affinity_desc *curmsk, *masks = NULL;
722 struct msi_desc *entry;
723 void __iomem *addr;
724 int ret, i;
725 int vec_count = pci_msix_vec_count(dev);
726
727 if (affd)
728 masks = irq_create_affinity_masks(nvec, affd);
729
730 for (i = 0, curmsk = masks; i < nvec; i++) {
731 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
732 if (!entry) {
733 if (!i)
734 iounmap(base);
735 else
736 free_msi_irqs(dev);
737 /* No enough memory. Don't try again */
738 ret = -ENOMEM;
739 goto out;
740 }
741
742 entry->msi_attrib.is_msix = 1;
743 entry->msi_attrib.is_64 = 1;
744
745 if (entries)
746 entry->msi_attrib.entry_nr = entries[i].entry;
747 else
748 entry->msi_attrib.entry_nr = i;
749
750 entry->msi_attrib.is_virtual =
751 entry->msi_attrib.entry_nr >= vec_count;
752
753 entry->msi_attrib.default_irq = dev->irq;
754 entry->mask_base = base;
755
756 addr = pci_msix_desc_addr(entry);
757 if (addr)
758 entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
759
760 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
761 if (masks)
762 curmsk++;
763 }
764 ret = 0;
765 out:
766 kfree(masks);
767 return ret;
768 }
769
msix_update_entries(struct pci_dev * dev,struct msix_entry * entries)770 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
771 {
772 struct msi_desc *entry;
773
774 for_each_pci_msi_entry(entry, dev) {
775 if (entries) {
776 entries->vector = entry->irq;
777 entries++;
778 }
779 }
780 }
781
msix_mask_all(void __iomem * base,int tsize)782 static void msix_mask_all(void __iomem *base, int tsize)
783 {
784 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
785 int i;
786
787 if (pci_msi_ignore_mask)
788 return;
789
790 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
791 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
792 }
793
794 /**
795 * msix_capability_init - configure device's MSI-X capability
796 * @dev: pointer to the pci_dev data structure of MSI-X device function
797 * @entries: pointer to an array of struct msix_entry entries
798 * @nvec: number of @entries
799 * @affd: Optional pointer to enable automatic affinity assignment
800 *
801 * Setup the MSI-X capability structure of device function with a
802 * single MSI-X IRQ. A return of zero indicates the successful setup of
803 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
804 **/
msix_capability_init(struct pci_dev * dev,struct msix_entry * entries,int nvec,struct irq_affinity * affd)805 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
806 int nvec, struct irq_affinity *affd)
807 {
808 void __iomem *base;
809 int ret, tsize;
810 u16 control;
811
812 /*
813 * Some devices require MSI-X to be enabled before the MSI-X
814 * registers can be accessed. Mask all the vectors to prevent
815 * interrupts coming in before they're fully set up.
816 */
817 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
818 PCI_MSIX_FLAGS_ENABLE);
819
820 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
821 /* Request & Map MSI-X table region */
822 tsize = msix_table_size(control);
823 base = msix_map_region(dev, tsize);
824 if (!base) {
825 ret = -ENOMEM;
826 goto out_disable;
827 }
828
829 ret = msix_setup_entries(dev, base, entries, nvec, affd);
830 if (ret)
831 goto out_disable;
832
833 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
834 if (ret)
835 goto out_avail;
836
837 /* Check if all MSI entries honor device restrictions */
838 ret = msi_verify_entries(dev);
839 if (ret)
840 goto out_free;
841
842 msix_update_entries(dev, entries);
843
844 ret = populate_msi_sysfs(dev);
845 if (ret)
846 goto out_free;
847
848 /* Set MSI-X enabled bits and unmask the function */
849 pci_intx_for_msi(dev, 0);
850 dev->msix_enabled = 1;
851
852 /*
853 * Ensure that all table entries are masked to prevent
854 * stale entries from firing in a crash kernel.
855 *
856 * Done late to deal with a broken Marvell NVME device
857 * which takes the MSI-X mask bits into account even
858 * when MSI-X is disabled, which prevents MSI delivery.
859 */
860 msix_mask_all(base, tsize);
861 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
862
863 pcibios_free_irq(dev);
864 return 0;
865
866 out_avail:
867 if (ret < 0) {
868 /*
869 * If we had some success, report the number of IRQs
870 * we succeeded in setting up.
871 */
872 struct msi_desc *entry;
873 int avail = 0;
874
875 for_each_pci_msi_entry(entry, dev) {
876 if (entry->irq != 0)
877 avail++;
878 }
879 if (avail != 0)
880 ret = avail;
881 }
882
883 out_free:
884 free_msi_irqs(dev);
885
886 out_disable:
887 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
888
889 return ret;
890 }
891
892 /**
893 * pci_msi_supported - check whether MSI may be enabled on a device
894 * @dev: pointer to the pci_dev data structure of MSI device function
895 * @nvec: how many MSIs have been requested?
896 *
897 * Look at global flags, the device itself, and its parent buses
898 * to determine if MSI/-X are supported for the device. If MSI/-X is
899 * supported return 1, else return 0.
900 **/
pci_msi_supported(struct pci_dev * dev,int nvec)901 static int pci_msi_supported(struct pci_dev *dev, int nvec)
902 {
903 struct pci_bus *bus;
904
905 /* MSI must be globally enabled and supported by the device */
906 if (!pci_msi_enable)
907 return 0;
908
909 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
910 return 0;
911
912 /*
913 * You can't ask to have 0 or less MSIs configured.
914 * a) it's stupid ..
915 * b) the list manipulation code assumes nvec >= 1.
916 */
917 if (nvec < 1)
918 return 0;
919
920 /*
921 * Any bridge which does NOT route MSI transactions from its
922 * secondary bus to its primary bus must set NO_MSI flag on
923 * the secondary pci_bus.
924 * We expect only arch-specific PCI host bus controller driver
925 * or quirks for specific PCI bridges to be setting NO_MSI.
926 */
927 for (bus = dev->bus; bus; bus = bus->parent)
928 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
929 return 0;
930
931 return 1;
932 }
933
934 /**
935 * pci_msi_vec_count - Return the number of MSI vectors a device can send
936 * @dev: device to report about
937 *
938 * This function returns the number of MSI vectors a device requested via
939 * Multiple Message Capable register. It returns a negative errno if the
940 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
941 * and returns a power of two, up to a maximum of 2^5 (32), according to the
942 * MSI specification.
943 **/
pci_msi_vec_count(struct pci_dev * dev)944 int pci_msi_vec_count(struct pci_dev *dev)
945 {
946 int ret;
947 u16 msgctl;
948
949 if (!dev->msi_cap)
950 return -EINVAL;
951
952 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
953 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
954
955 return ret;
956 }
957 EXPORT_SYMBOL(pci_msi_vec_count);
958
pci_msi_shutdown(struct pci_dev * dev)959 static void pci_msi_shutdown(struct pci_dev *dev)
960 {
961 struct msi_desc *desc;
962 u32 mask;
963
964 if (!pci_msi_enable || !dev || !dev->msi_enabled)
965 return;
966
967 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
968 desc = first_pci_msi_entry(dev);
969
970 pci_msi_set_enable(dev, 0);
971 pci_intx_for_msi(dev, 1);
972 dev->msi_enabled = 0;
973
974 /* Return the device with MSI unmasked as initial states */
975 mask = msi_mask(desc->msi_attrib.multi_cap);
976 msi_mask_irq(desc, mask, 0);
977
978 /* Restore dev->irq to its default pin-assertion IRQ */
979 dev->irq = desc->msi_attrib.default_irq;
980 pcibios_alloc_irq(dev);
981 }
982
pci_disable_msi(struct pci_dev * dev)983 void pci_disable_msi(struct pci_dev *dev)
984 {
985 if (!pci_msi_enable || !dev || !dev->msi_enabled)
986 return;
987
988 pci_msi_shutdown(dev);
989 free_msi_irqs(dev);
990 }
991 EXPORT_SYMBOL(pci_disable_msi);
992
993 /**
994 * pci_msix_vec_count - return the number of device's MSI-X table entries
995 * @dev: pointer to the pci_dev data structure of MSI-X device function
996 * This function returns the number of device's MSI-X table entries and
997 * therefore the number of MSI-X vectors device is capable of sending.
998 * It returns a negative errno if the device is not capable of sending MSI-X
999 * interrupts.
1000 **/
pci_msix_vec_count(struct pci_dev * dev)1001 int pci_msix_vec_count(struct pci_dev *dev)
1002 {
1003 u16 control;
1004
1005 if (!dev->msix_cap)
1006 return -EINVAL;
1007
1008 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
1009 return msix_table_size(control);
1010 }
1011 EXPORT_SYMBOL(pci_msix_vec_count);
1012
__pci_enable_msix(struct pci_dev * dev,struct msix_entry * entries,int nvec,struct irq_affinity * affd,int flags)1013 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
1014 int nvec, struct irq_affinity *affd, int flags)
1015 {
1016 int nr_entries;
1017 int i, j;
1018
1019 if (!pci_msi_supported(dev, nvec))
1020 return -EINVAL;
1021
1022 nr_entries = pci_msix_vec_count(dev);
1023 if (nr_entries < 0)
1024 return nr_entries;
1025 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
1026 return nr_entries;
1027
1028 if (entries) {
1029 /* Check for any invalid entries */
1030 for (i = 0; i < nvec; i++) {
1031 if (entries[i].entry >= nr_entries)
1032 return -EINVAL; /* invalid entry */
1033 for (j = i + 1; j < nvec; j++) {
1034 if (entries[i].entry == entries[j].entry)
1035 return -EINVAL; /* duplicate entry */
1036 }
1037 }
1038 }
1039
1040 /* Check whether driver already requested for MSI IRQ */
1041 if (dev->msi_enabled) {
1042 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
1043 return -EINVAL;
1044 }
1045 return msix_capability_init(dev, entries, nvec, affd);
1046 }
1047
pci_msix_shutdown(struct pci_dev * dev)1048 static void pci_msix_shutdown(struct pci_dev *dev)
1049 {
1050 struct msi_desc *entry;
1051
1052 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1053 return;
1054
1055 if (pci_dev_is_disconnected(dev)) {
1056 dev->msix_enabled = 0;
1057 return;
1058 }
1059
1060 /* Return the device with MSI-X masked as initial states */
1061 for_each_pci_msi_entry(entry, dev)
1062 __pci_msix_desc_mask_irq(entry, 1);
1063
1064 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1065 pci_intx_for_msi(dev, 1);
1066 dev->msix_enabled = 0;
1067 pcibios_alloc_irq(dev);
1068 }
1069
pci_disable_msix(struct pci_dev * dev)1070 void pci_disable_msix(struct pci_dev *dev)
1071 {
1072 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1073 return;
1074
1075 pci_msix_shutdown(dev);
1076 free_msi_irqs(dev);
1077 }
1078 EXPORT_SYMBOL(pci_disable_msix);
1079
pci_no_msi(void)1080 void pci_no_msi(void)
1081 {
1082 pci_msi_enable = 0;
1083 }
1084
1085 /**
1086 * pci_msi_enabled - is MSI enabled?
1087 *
1088 * Returns true if MSI has not been disabled by the command-line option
1089 * pci=nomsi.
1090 **/
pci_msi_enabled(void)1091 int pci_msi_enabled(void)
1092 {
1093 return pci_msi_enable;
1094 }
1095 EXPORT_SYMBOL(pci_msi_enabled);
1096
__pci_enable_msi_range(struct pci_dev * dev,int minvec,int maxvec,struct irq_affinity * affd)1097 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1098 struct irq_affinity *affd)
1099 {
1100 int nvec;
1101 int rc;
1102
1103 if (!pci_msi_supported(dev, minvec))
1104 return -EINVAL;
1105
1106 /* Check whether driver already requested MSI-X IRQs */
1107 if (dev->msix_enabled) {
1108 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
1109 return -EINVAL;
1110 }
1111
1112 if (maxvec < minvec)
1113 return -ERANGE;
1114
1115 if (WARN_ON_ONCE(dev->msi_enabled))
1116 return -EINVAL;
1117
1118 nvec = pci_msi_vec_count(dev);
1119 if (nvec < 0)
1120 return nvec;
1121 if (nvec < minvec)
1122 return -ENOSPC;
1123
1124 if (nvec > maxvec)
1125 nvec = maxvec;
1126
1127 for (;;) {
1128 if (affd) {
1129 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1130 if (nvec < minvec)
1131 return -ENOSPC;
1132 }
1133
1134 rc = msi_capability_init(dev, nvec, affd);
1135 if (rc == 0)
1136 return nvec;
1137
1138 if (rc < 0)
1139 return rc;
1140 if (rc < minvec)
1141 return -ENOSPC;
1142
1143 nvec = rc;
1144 }
1145 }
1146
1147 /* deprecated, don't use */
pci_enable_msi(struct pci_dev * dev)1148 int pci_enable_msi(struct pci_dev *dev)
1149 {
1150 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
1151 if (rc < 0)
1152 return rc;
1153 return 0;
1154 }
1155 EXPORT_SYMBOL(pci_enable_msi);
1156
__pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec,struct irq_affinity * affd,int flags)1157 static int __pci_enable_msix_range(struct pci_dev *dev,
1158 struct msix_entry *entries, int minvec,
1159 int maxvec, struct irq_affinity *affd,
1160 int flags)
1161 {
1162 int rc, nvec = maxvec;
1163
1164 if (maxvec < minvec)
1165 return -ERANGE;
1166
1167 if (WARN_ON_ONCE(dev->msix_enabled))
1168 return -EINVAL;
1169
1170 for (;;) {
1171 if (affd) {
1172 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1173 if (nvec < minvec)
1174 return -ENOSPC;
1175 }
1176
1177 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
1178 if (rc == 0)
1179 return nvec;
1180
1181 if (rc < 0)
1182 return rc;
1183 if (rc < minvec)
1184 return -ENOSPC;
1185
1186 nvec = rc;
1187 }
1188 }
1189
1190 /**
1191 * pci_enable_msix_range - configure device's MSI-X capability structure
1192 * @dev: pointer to the pci_dev data structure of MSI-X device function
1193 * @entries: pointer to an array of MSI-X entries
1194 * @minvec: minimum number of MSI-X IRQs requested
1195 * @maxvec: maximum number of MSI-X IRQs requested
1196 *
1197 * Setup the MSI-X capability structure of device function with a maximum
1198 * possible number of interrupts in the range between @minvec and @maxvec
1199 * upon its software driver call to request for MSI-X mode enabled on its
1200 * hardware device function. It returns a negative errno if an error occurs.
1201 * If it succeeds, it returns the actual number of interrupts allocated and
1202 * indicates the successful configuration of MSI-X capability structure
1203 * with new allocated MSI-X interrupts.
1204 **/
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1205 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1206 int minvec, int maxvec)
1207 {
1208 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
1209 }
1210 EXPORT_SYMBOL(pci_enable_msix_range);
1211
1212 /**
1213 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1214 * @dev: PCI device to operate on
1215 * @min_vecs: minimum number of vectors required (must be >= 1)
1216 * @max_vecs: maximum (desired) number of vectors
1217 * @flags: flags or quirks for the allocation
1218 * @affd: optional description of the affinity requirements
1219 *
1220 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1221 * vectors if available, and fall back to a single legacy vector
1222 * if neither is available. Return the number of vectors allocated,
1223 * (which might be smaller than @max_vecs) if successful, or a negative
1224 * error code on error. If less than @min_vecs interrupt vectors are
1225 * available for @dev the function will fail with -ENOSPC.
1226 *
1227 * To get the Linux IRQ number used for a vector that can be passed to
1228 * request_irq() use the pci_irq_vector() helper.
1229 */
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * affd)1230 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1231 unsigned int max_vecs, unsigned int flags,
1232 struct irq_affinity *affd)
1233 {
1234 struct irq_affinity msi_default_affd = {0};
1235 int msix_vecs = -ENOSPC;
1236 int msi_vecs = -ENOSPC;
1237
1238 if (flags & PCI_IRQ_AFFINITY) {
1239 if (!affd)
1240 affd = &msi_default_affd;
1241 } else {
1242 if (WARN_ON(affd))
1243 affd = NULL;
1244 }
1245
1246 if (flags & PCI_IRQ_MSIX) {
1247 msix_vecs = __pci_enable_msix_range(dev, NULL, min_vecs,
1248 max_vecs, affd, flags);
1249 if (msix_vecs > 0)
1250 return msix_vecs;
1251 }
1252
1253 if (flags & PCI_IRQ_MSI) {
1254 msi_vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs,
1255 affd);
1256 if (msi_vecs > 0)
1257 return msi_vecs;
1258 }
1259
1260 /* use legacy IRQ if allowed */
1261 if (flags & PCI_IRQ_LEGACY) {
1262 if (min_vecs == 1 && dev->irq) {
1263 /*
1264 * Invoke the affinity spreading logic to ensure that
1265 * the device driver can adjust queue configuration
1266 * for the single interrupt case.
1267 */
1268 if (affd)
1269 irq_create_affinity_masks(1, affd);
1270 pci_intx(dev, 1);
1271 return 1;
1272 }
1273 }
1274
1275 if (msix_vecs == -ENOSPC)
1276 return -ENOSPC;
1277 return msi_vecs;
1278 }
1279 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1280
1281 /**
1282 * pci_free_irq_vectors - free previously allocated IRQs for a device
1283 * @dev: PCI device to operate on
1284 *
1285 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1286 */
pci_free_irq_vectors(struct pci_dev * dev)1287 void pci_free_irq_vectors(struct pci_dev *dev)
1288 {
1289 pci_disable_msix(dev);
1290 pci_disable_msi(dev);
1291 }
1292 EXPORT_SYMBOL(pci_free_irq_vectors);
1293
1294 /**
1295 * pci_irq_vector - return Linux IRQ number of a device vector
1296 * @dev: PCI device to operate on
1297 * @nr: Interrupt vector index (0-based)
1298 *
1299 * @nr has the following meanings depending on the interrupt mode:
1300 * MSI-X: The index in the MSI-X vector table
1301 * MSI: The index of the enabled MSI vectors
1302 * INTx: Must be 0
1303 *
1304 * Return: The Linux interrupt number or -EINVAl if @nr is out of range.
1305 */
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1306 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1307 {
1308 if (dev->msix_enabled) {
1309 struct msi_desc *entry;
1310
1311 for_each_pci_msi_entry(entry, dev) {
1312 if (entry->msi_attrib.entry_nr == nr)
1313 return entry->irq;
1314 }
1315 WARN_ON_ONCE(1);
1316 return -EINVAL;
1317 }
1318
1319 if (dev->msi_enabled) {
1320 struct msi_desc *entry = first_pci_msi_entry(dev);
1321
1322 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1323 return -EINVAL;
1324 } else {
1325 if (WARN_ON_ONCE(nr > 0))
1326 return -EINVAL;
1327 }
1328
1329 return dev->irq + nr;
1330 }
1331 EXPORT_SYMBOL(pci_irq_vector);
1332
1333 /**
1334 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1335 * @dev: PCI device to operate on
1336 * @nr: device-relative interrupt vector index (0-based).
1337 *
1338 * @nr has the following meanings depending on the interrupt mode:
1339 * MSI-X: The index in the MSI-X vector table
1340 * MSI: The index of the enabled MSI vectors
1341 * INTx: Must be 0
1342 *
1343 * Return: A cpumask pointer or NULL if @nr is out of range
1344 */
pci_irq_get_affinity(struct pci_dev * dev,int nr)1345 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1346 {
1347 if (dev->msix_enabled) {
1348 struct msi_desc *entry;
1349
1350 for_each_pci_msi_entry(entry, dev) {
1351 if (entry->msi_attrib.entry_nr == nr)
1352 return &entry->affinity->mask;
1353 }
1354 WARN_ON_ONCE(1);
1355 return NULL;
1356 } else if (dev->msi_enabled) {
1357 struct msi_desc *entry = first_pci_msi_entry(dev);
1358
1359 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1360 nr >= entry->nvec_used))
1361 return NULL;
1362
1363 return &entry->affinity[nr].mask;
1364 } else {
1365 return cpu_possible_mask;
1366 }
1367 }
1368 EXPORT_SYMBOL(pci_irq_get_affinity);
1369
1370 /**
1371 * pci_irq_get_node - return the NUMA node of a particular MSI vector
1372 * @pdev: PCI device to operate on
1373 * @vec: device-relative interrupt vector index (0-based).
1374 */
pci_irq_get_node(struct pci_dev * pdev,int vec)1375 int pci_irq_get_node(struct pci_dev *pdev, int vec)
1376 {
1377 const struct cpumask *mask;
1378
1379 mask = pci_irq_get_affinity(pdev, vec);
1380 if (mask)
1381 return local_memory_node(cpu_to_node(cpumask_first(mask)));
1382 return dev_to_node(&pdev->dev);
1383 }
1384 EXPORT_SYMBOL(pci_irq_get_node);
1385
msi_desc_to_pci_dev(struct msi_desc * desc)1386 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1387 {
1388 return to_pci_dev(desc->dev);
1389 }
1390 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1391
msi_desc_to_pci_sysdata(struct msi_desc * desc)1392 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1393 {
1394 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1395
1396 return dev->bus->sysdata;
1397 }
1398 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1399
1400 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1401 /**
1402 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1403 * @irq_data: Pointer to interrupt data of the MSI interrupt
1404 * @msg: Pointer to the message
1405 */
pci_msi_domain_write_msg(struct irq_data * irq_data,struct msi_msg * msg)1406 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1407 {
1408 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1409
1410 /*
1411 * For MSI-X desc->irq is always equal to irq_data->irq. For
1412 * MSI only the first interrupt of MULTI MSI passes the test.
1413 */
1414 if (desc->irq == irq_data->irq)
1415 __pci_write_msi_msg(desc, msg);
1416 }
1417
1418 /**
1419 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1420 * @dev: Pointer to the PCI device
1421 * @desc: Pointer to the MSI descriptor
1422 *
1423 * The ID number is only used within the irqdomain.
1424 */
pci_msi_domain_calc_hwirq(struct pci_dev * dev,struct msi_desc * desc)1425 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1426 struct msi_desc *desc)
1427 {
1428 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1429 pci_dev_id(dev) << 11 |
1430 ((irq_hw_number_t)(pci_domain_nr(dev->bus) & 0xFFFFFFFF)) << 27;
1431 }
1432
pci_msi_desc_is_multi_msi(struct msi_desc * desc)1433 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1434 {
1435 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1436 }
1437
1438 /**
1439 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1440 * for @dev
1441 * @domain: The interrupt domain to check
1442 * @info: The domain info for verification
1443 * @dev: The device to check
1444 *
1445 * Returns:
1446 * 0 if the functionality is supported
1447 * 1 if Multi MSI is requested, but the domain does not support it
1448 * -ENOTSUPP otherwise
1449 */
pci_msi_domain_check_cap(struct irq_domain * domain,struct msi_domain_info * info,struct device * dev)1450 int pci_msi_domain_check_cap(struct irq_domain *domain,
1451 struct msi_domain_info *info, struct device *dev)
1452 {
1453 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1454
1455 /* Special handling to support __pci_enable_msi_range() */
1456 if (pci_msi_desc_is_multi_msi(desc) &&
1457 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1458 return 1;
1459 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1460 return -ENOTSUPP;
1461
1462 return 0;
1463 }
1464
pci_msi_domain_handle_error(struct irq_domain * domain,struct msi_desc * desc,int error)1465 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1466 struct msi_desc *desc, int error)
1467 {
1468 /* Special handling to support __pci_enable_msi_range() */
1469 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1470 return 1;
1471
1472 return error;
1473 }
1474
1475 #ifdef GENERIC_MSI_DOMAIN_OPS
pci_msi_domain_set_desc(msi_alloc_info_t * arg,struct msi_desc * desc)1476 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1477 struct msi_desc *desc)
1478 {
1479 arg->desc = desc;
1480 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1481 desc);
1482 }
1483 #else
1484 #define pci_msi_domain_set_desc NULL
1485 #endif
1486
1487 static struct msi_domain_ops pci_msi_domain_ops_default = {
1488 .set_desc = pci_msi_domain_set_desc,
1489 .msi_check = pci_msi_domain_check_cap,
1490 .handle_error = pci_msi_domain_handle_error,
1491 };
1492
pci_msi_domain_update_dom_ops(struct msi_domain_info * info)1493 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1494 {
1495 struct msi_domain_ops *ops = info->ops;
1496
1497 if (ops == NULL) {
1498 info->ops = &pci_msi_domain_ops_default;
1499 } else {
1500 if (ops->set_desc == NULL)
1501 ops->set_desc = pci_msi_domain_set_desc;
1502 if (ops->msi_check == NULL)
1503 ops->msi_check = pci_msi_domain_check_cap;
1504 if (ops->handle_error == NULL)
1505 ops->handle_error = pci_msi_domain_handle_error;
1506 }
1507 }
1508
pci_msi_domain_update_chip_ops(struct msi_domain_info * info)1509 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1510 {
1511 struct irq_chip *chip = info->chip;
1512
1513 BUG_ON(!chip);
1514 if (!chip->irq_write_msi_msg)
1515 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1516 if (!chip->irq_mask)
1517 chip->irq_mask = pci_msi_mask_irq;
1518 if (!chip->irq_unmask)
1519 chip->irq_unmask = pci_msi_unmask_irq;
1520 }
1521
1522 /**
1523 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1524 * @fwnode: Optional fwnode of the interrupt controller
1525 * @info: MSI domain info
1526 * @parent: Parent irq domain
1527 *
1528 * Updates the domain and chip ops and creates a MSI interrupt domain.
1529 *
1530 * Returns:
1531 * A domain pointer or NULL in case of failure.
1532 */
pci_msi_create_irq_domain(struct fwnode_handle * fwnode,struct msi_domain_info * info,struct irq_domain * parent)1533 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1534 struct msi_domain_info *info,
1535 struct irq_domain *parent)
1536 {
1537 struct irq_domain *domain;
1538
1539 if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
1540 info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
1541
1542 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1543 pci_msi_domain_update_dom_ops(info);
1544 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1545 pci_msi_domain_update_chip_ops(info);
1546
1547 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1548 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
1549 info->flags |= MSI_FLAG_MUST_REACTIVATE;
1550
1551 /* PCI-MSI is oneshot-safe */
1552 info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
1553
1554 domain = msi_create_irq_domain(fwnode, info, parent);
1555 if (!domain)
1556 return NULL;
1557
1558 irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
1559 return domain;
1560 }
1561 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1562
1563 /*
1564 * Users of the generic MSI infrastructure expect a device to have a single ID,
1565 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1566 * DMA phantom functions tend to still emit MSIs from the real function number,
1567 * so we ignore those and only consider topological aliases where either the
1568 * alias device or RID appears on a different bus number. We also make the
1569 * reasonable assumption that bridges are walked in an upstream direction (so
1570 * the last one seen wins), and the much braver assumption that the most likely
1571 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1572 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1573 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1574 * for taking ownership all we can really do is close our eyes and hope...
1575 */
get_msi_id_cb(struct pci_dev * pdev,u16 alias,void * data)1576 static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1577 {
1578 u32 *pa = data;
1579 u8 bus = PCI_BUS_NUM(*pa);
1580
1581 if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
1582 *pa = alias;
1583
1584 return 0;
1585 }
1586
1587 /**
1588 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1589 * @domain: The interrupt domain
1590 * @pdev: The PCI device.
1591 *
1592 * The RID for a device is formed from the alias, with a firmware
1593 * supplied mapping applied
1594 *
1595 * Returns: The RID.
1596 */
pci_msi_domain_get_msi_rid(struct irq_domain * domain,struct pci_dev * pdev)1597 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1598 {
1599 struct device_node *of_node;
1600 u32 rid = pci_dev_id(pdev);
1601
1602 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1603
1604 of_node = irq_domain_get_of_node(domain);
1605 rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) :
1606 iort_msi_map_id(&pdev->dev, rid);
1607
1608 return rid;
1609 }
1610
1611 /**
1612 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1613 * @pdev: The PCI device
1614 *
1615 * Use the firmware data to find a device-specific MSI domain
1616 * (i.e. not one that is set as a default).
1617 *
1618 * Returns: The corresponding MSI domain or NULL if none has been found.
1619 */
pci_msi_get_device_domain(struct pci_dev * pdev)1620 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1621 {
1622 struct irq_domain *dom;
1623 u32 rid = pci_dev_id(pdev);
1624
1625 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1626 dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI);
1627 if (!dom)
1628 dom = iort_get_device_domain(&pdev->dev, rid,
1629 DOMAIN_BUS_PCI_MSI);
1630 return dom;
1631 }
1632 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
1633