1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Marvell
4 *
5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
6 *
7 * This file helps PCI controller drivers implement a fake root port
8 * PCI bridge when the HW doesn't provide such a root port PCI
9 * bridge.
10 *
11 * It emulates a PCI bridge by providing a fake PCI configuration
12 * space (and optionally a PCIe capability configuration space) in
13 * memory. By default the read/write operations simply read and update
14 * this fake configuration space in memory. However, PCI controller
15 * drivers can provide through the 'struct pci_sw_bridge_ops'
16 * structure a set of operations to override or complement this
17 * default behavior.
18 */
19
20 #include <linux/pci.h>
21 #include "pci-bridge-emul.h"
22
23 #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
24 #define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2)
25 #define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
26 #define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
27
28 struct pci_bridge_reg_behavior {
29 /* Read-only bits */
30 u32 ro;
31
32 /* Read-write bits */
33 u32 rw;
34
35 /* Write-1-to-clear bits */
36 u32 w1c;
37
38 /* Reserved bits (hardwired to 0) */
39 u32 rsvd;
40 };
41
42 static const
43 struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
44 [PCI_VENDOR_ID / 4] = { .ro = ~0 },
45 [PCI_COMMAND / 4] = {
46 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
47 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
48 PCI_COMMAND_SERR),
49 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
50 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
51 PCI_COMMAND_FAST_BACK) |
52 (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
53 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
54 .rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16),
55 .w1c = (PCI_STATUS_PARITY |
56 PCI_STATUS_SIG_TARGET_ABORT |
57 PCI_STATUS_REC_TARGET_ABORT |
58 PCI_STATUS_REC_MASTER_ABORT |
59 PCI_STATUS_SIG_SYSTEM_ERROR |
60 PCI_STATUS_DETECTED_PARITY) << 16,
61 },
62 [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
63
64 /*
65 * Cache Line Size register: implement as read-only, we do not
66 * pretend implementing "Memory Write and Invalidate"
67 * transactions"
68 *
69 * Latency Timer Register: implemented as read-only, as "A
70 * bridge that is not capable of a burst transfer of more than
71 * two data phases on its primary interface is permitted to
72 * hardwire the Latency Timer to a value of 16 or less"
73 *
74 * Header Type: always read-only
75 *
76 * BIST register: implemented as read-only, as "A bridge that
77 * does not support BIST must implement this register as a
78 * read-only register that returns 0 when read"
79 */
80 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
81
82 /*
83 * Base Address registers not used must be implemented as
84 * read-only registers that return 0 when read.
85 */
86 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
87 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
88
89 [PCI_PRIMARY_BUS / 4] = {
90 /* Primary, secondary and subordinate bus are RW */
91 .rw = GENMASK(24, 0),
92 /* Secondary latency is read-only */
93 .ro = GENMASK(31, 24),
94 },
95
96 [PCI_IO_BASE / 4] = {
97 /* The high four bits of I/O base/limit are RW */
98 .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
99
100 /* The low four bits of I/O base/limit are RO */
101 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
102 PCI_STATUS_DEVSEL_MASK) << 16) |
103 GENMASK(11, 8) | GENMASK(3, 0)),
104
105 .w1c = (PCI_STATUS_PARITY |
106 PCI_STATUS_SIG_TARGET_ABORT |
107 PCI_STATUS_REC_TARGET_ABORT |
108 PCI_STATUS_REC_MASTER_ABORT |
109 PCI_STATUS_SIG_SYSTEM_ERROR |
110 PCI_STATUS_DETECTED_PARITY) << 16,
111
112 .rsvd = ((BIT(6) | GENMASK(4, 0)) << 16),
113 },
114
115 [PCI_MEMORY_BASE / 4] = {
116 /* The high 12-bits of mem base/limit are RW */
117 .rw = GENMASK(31, 20) | GENMASK(15, 4),
118
119 /* The low four bits of mem base/limit are RO */
120 .ro = GENMASK(19, 16) | GENMASK(3, 0),
121 },
122
123 [PCI_PREF_MEMORY_BASE / 4] = {
124 /* The high 12-bits of pref mem base/limit are RW */
125 .rw = GENMASK(31, 20) | GENMASK(15, 4),
126
127 /* The low four bits of pref mem base/limit are RO */
128 .ro = GENMASK(19, 16) | GENMASK(3, 0),
129 },
130
131 [PCI_PREF_BASE_UPPER32 / 4] = {
132 .rw = ~0,
133 },
134
135 [PCI_PREF_LIMIT_UPPER32 / 4] = {
136 .rw = ~0,
137 },
138
139 [PCI_IO_BASE_UPPER16 / 4] = {
140 .rw = ~0,
141 },
142
143 [PCI_CAPABILITY_LIST / 4] = {
144 .ro = GENMASK(7, 0),
145 .rsvd = GENMASK(31, 8),
146 },
147
148 [PCI_ROM_ADDRESS1 / 4] = {
149 .rw = GENMASK(31, 11) | BIT(0),
150 .rsvd = GENMASK(10, 1),
151 },
152
153 /*
154 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
155 * are RO, and bridge control (31:16) are a mix of RW, RO,
156 * reserved and W1C bits
157 */
158 [PCI_INTERRUPT_LINE / 4] = {
159 /* Interrupt line is RW */
160 .rw = (GENMASK(7, 0) |
161 ((PCI_BRIDGE_CTL_PARITY |
162 PCI_BRIDGE_CTL_SERR |
163 PCI_BRIDGE_CTL_ISA |
164 PCI_BRIDGE_CTL_VGA |
165 PCI_BRIDGE_CTL_MASTER_ABORT |
166 PCI_BRIDGE_CTL_BUS_RESET |
167 BIT(8) | BIT(9) | BIT(11)) << 16)),
168
169 /* Interrupt pin is RO */
170 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
171
172 .w1c = BIT(10) << 16,
173
174 .rsvd = (GENMASK(15, 12) | BIT(4)) << 16,
175 },
176 };
177
178 static const
179 struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
180 [PCI_CAP_LIST_ID / 4] = {
181 /*
182 * Capability ID, Next Capability Pointer and
183 * Capabilities register are all read-only.
184 */
185 .ro = ~0,
186 },
187
188 [PCI_EXP_DEVCAP / 4] = {
189 .ro = ~0,
190 },
191
192 [PCI_EXP_DEVCTL / 4] = {
193 /* Device control register is RW */
194 .rw = GENMASK(15, 0),
195
196 /*
197 * Device status register has 4 bits W1C, then 2 bits
198 * RO, the rest is reserved
199 */
200 .w1c = GENMASK(19, 16),
201 .ro = GENMASK(21, 20),
202 .rsvd = GENMASK(31, 22),
203 },
204
205 [PCI_EXP_LNKCAP / 4] = {
206 /* All bits are RO, except bit 23 which is reserved */
207 .ro = lower_32_bits(~BIT(23)),
208 .rsvd = BIT(23),
209 },
210
211 [PCI_EXP_LNKCTL / 4] = {
212 /*
213 * Link control has bits [1:0] and [11:3] RW, the
214 * other bits are reserved.
215 * Link status has bits [13:0] RO, and bits [14:15]
216 * W1C.
217 */
218 .rw = GENMASK(11, 3) | GENMASK(1, 0),
219 .ro = GENMASK(13, 0) << 16,
220 .w1c = GENMASK(15, 14) << 16,
221 .rsvd = GENMASK(15, 12) | BIT(2),
222 },
223
224 [PCI_EXP_SLTCAP / 4] = {
225 .ro = ~0,
226 },
227
228 [PCI_EXP_SLTCTL / 4] = {
229 /*
230 * Slot control has bits [12:0] RW, the rest is
231 * reserved.
232 *
233 * Slot status has a mix of W1C and RO bits, as well
234 * as reserved bits.
235 */
236 .rw = GENMASK(12, 0),
237 .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
238 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
239 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
240 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
241 PCI_EXP_SLTSTA_EIS) << 16,
242 .rsvd = GENMASK(15, 13) | (GENMASK(15, 9) << 16),
243 },
244
245 [PCI_EXP_RTCTL / 4] = {
246 /*
247 * Root control has bits [4:0] RW, the rest is
248 * reserved.
249 *
250 * Root status has bit 0 RO, the rest is reserved.
251 */
252 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
253 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
254 PCI_EXP_RTCTL_CRSSVE),
255 .ro = PCI_EXP_RTCAP_CRSVIS << 16,
256 .rsvd = GENMASK(15, 5) | (GENMASK(15, 1) << 16),
257 },
258
259 [PCI_EXP_RTSTA / 4] = {
260 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
261 .w1c = PCI_EXP_RTSTA_PME,
262 .rsvd = GENMASK(31, 18),
263 },
264 };
265
266 /*
267 * Initialize a pci_bridge_emul structure to represent a fake PCI
268 * bridge configuration space. The caller needs to have initialized
269 * the PCI configuration space with whatever values make sense
270 * (typically at least vendor, device, revision), the ->ops pointer,
271 * and optionally ->data and ->has_pcie.
272 */
pci_bridge_emul_init(struct pci_bridge_emul * bridge,unsigned int flags)273 int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
274 unsigned int flags)
275 {
276 BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
277
278 bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
279 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
280 bridge->conf.cache_line_size = 0x10;
281 bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
282 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
283 sizeof(pci_regs_behavior),
284 GFP_KERNEL);
285 if (!bridge->pci_regs_behavior)
286 return -ENOMEM;
287
288 if (bridge->has_pcie) {
289 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
290 bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
291 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
292 bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
293 bridge->pcie_cap_regs_behavior =
294 kmemdup(pcie_cap_regs_behavior,
295 sizeof(pcie_cap_regs_behavior),
296 GFP_KERNEL);
297 if (!bridge->pcie_cap_regs_behavior) {
298 kfree(bridge->pci_regs_behavior);
299 return -ENOMEM;
300 }
301 /* These bits are applicable only for PCI and reserved on PCIe */
302 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
303 ~GENMASK(15, 8);
304 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
305 ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
306 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
307 PCI_COMMAND_FAST_BACK) |
308 (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
309 PCI_STATUS_DEVSEL_MASK) << 16);
310 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
311 ~GENMASK(31, 24);
312 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
313 ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
314 PCI_STATUS_DEVSEL_MASK) << 16);
315 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
316 ~((PCI_BRIDGE_CTL_MASTER_ABORT |
317 BIT(8) | BIT(9) | BIT(11)) << 16);
318 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
319 ~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
320 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
321 ~(BIT(10) << 16);
322 }
323
324 if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
325 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
326 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
327 }
328
329 return 0;
330 }
331
332 /*
333 * Cleanup a pci_bridge_emul structure that was previously initialized
334 * using pci_bridge_emul_init().
335 */
pci_bridge_emul_cleanup(struct pci_bridge_emul * bridge)336 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
337 {
338 if (bridge->has_pcie)
339 kfree(bridge->pcie_cap_regs_behavior);
340 kfree(bridge->pci_regs_behavior);
341 }
342
343 /*
344 * Should be called by the PCI controller driver when reading the PCI
345 * configuration space of the fake bridge. It will call back the
346 * ->ops->read_base or ->ops->read_pcie operations.
347 */
pci_bridge_emul_conf_read(struct pci_bridge_emul * bridge,int where,int size,u32 * value)348 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
349 int size, u32 *value)
350 {
351 int ret;
352 int reg = where & ~3;
353 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
354 int reg, u32 *value);
355 __le32 *cfgspace;
356 const struct pci_bridge_reg_behavior *behavior;
357
358 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
359 *value = 0;
360 return PCIBIOS_SUCCESSFUL;
361 }
362
363 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
364 *value = 0;
365 return PCIBIOS_SUCCESSFUL;
366 }
367
368 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
369 reg -= PCI_CAP_PCIE_START;
370 read_op = bridge->ops->read_pcie;
371 cfgspace = (__le32 *) &bridge->pcie_conf;
372 behavior = bridge->pcie_cap_regs_behavior;
373 } else {
374 read_op = bridge->ops->read_base;
375 cfgspace = (__le32 *) &bridge->conf;
376 behavior = bridge->pci_regs_behavior;
377 }
378
379 if (read_op)
380 ret = read_op(bridge, reg, value);
381 else
382 ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
383
384 if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
385 *value = le32_to_cpu(cfgspace[reg / 4]);
386
387 /*
388 * Make sure we never return any reserved bit with a value
389 * different from 0.
390 */
391 *value &= ~behavior[reg / 4].rsvd;
392
393 if (size == 1)
394 *value = (*value >> (8 * (where & 3))) & 0xff;
395 else if (size == 2)
396 *value = (*value >> (8 * (where & 3))) & 0xffff;
397 else if (size != 4)
398 return PCIBIOS_BAD_REGISTER_NUMBER;
399
400 return PCIBIOS_SUCCESSFUL;
401 }
402
403 /*
404 * Should be called by the PCI controller driver when writing the PCI
405 * configuration space of the fake bridge. It will call back the
406 * ->ops->write_base or ->ops->write_pcie operations.
407 */
pci_bridge_emul_conf_write(struct pci_bridge_emul * bridge,int where,int size,u32 value)408 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
409 int size, u32 value)
410 {
411 int reg = where & ~3;
412 int mask, ret, old, new, shift;
413 void (*write_op)(struct pci_bridge_emul *bridge, int reg,
414 u32 old, u32 new, u32 mask);
415 __le32 *cfgspace;
416 const struct pci_bridge_reg_behavior *behavior;
417
418 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
419 return PCIBIOS_SUCCESSFUL;
420
421 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
422 return PCIBIOS_SUCCESSFUL;
423
424 shift = (where & 0x3) * 8;
425
426 if (size == 4)
427 mask = 0xffffffff;
428 else if (size == 2)
429 mask = 0xffff << shift;
430 else if (size == 1)
431 mask = 0xff << shift;
432 else
433 return PCIBIOS_BAD_REGISTER_NUMBER;
434
435 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
436 if (ret != PCIBIOS_SUCCESSFUL)
437 return ret;
438
439 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
440 reg -= PCI_CAP_PCIE_START;
441 write_op = bridge->ops->write_pcie;
442 cfgspace = (__le32 *) &bridge->pcie_conf;
443 behavior = bridge->pcie_cap_regs_behavior;
444 } else {
445 write_op = bridge->ops->write_base;
446 cfgspace = (__le32 *) &bridge->conf;
447 behavior = bridge->pci_regs_behavior;
448 }
449
450 /* Keep all bits, except the RW bits */
451 new = old & (~mask | ~behavior[reg / 4].rw);
452
453 /* Update the value of the RW bits */
454 new |= (value << shift) & (behavior[reg / 4].rw & mask);
455
456 /* Clear the W1C bits */
457 new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
458
459 /* Save the new value with the cleared W1C bits into the cfgspace */
460 cfgspace[reg / 4] = cpu_to_le32(new);
461
462 /*
463 * Clear the W1C bits not specified by the write mask, so that the
464 * write_op() does not clear them.
465 */
466 new &= ~(behavior[reg / 4].w1c & ~mask);
467
468 /*
469 * Set the W1C bits specified by the write mask, so that write_op()
470 * knows about that they are to be cleared.
471 */
472 new |= (value << shift) & (behavior[reg / 4].w1c & mask);
473
474 if (write_op)
475 write_op(bridge, reg, old, new, mask);
476
477 return PCIBIOS_SUCCESSFUL;
478 }
479