1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DRIVERS_PCI_H
3 #define DRIVERS_PCI_H
4
5 #include <linux/pci.h>
6 #include <linux/android_kabi.h>
7
8 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
9 #define MAX_NR_DEVFNS 256
10
11 #define PCI_FIND_CAP_TTL 48
12
13 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14
15 extern const unsigned char pcie_link_speed[];
16 extern bool pci_early_dump;
17
18 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
19
20 /* Functions internal to the PCI core code */
21
22 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
24 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
pci_create_firmware_label_files(struct pci_dev * pdev)25 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
26 { return; }
pci_remove_firmware_label_files(struct pci_dev * pdev)27 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
28 { return; }
29 #else
30 void pci_create_firmware_label_files(struct pci_dev *pdev);
31 void pci_remove_firmware_label_files(struct pci_dev *pdev);
32 #endif
33 void pci_cleanup_rom(struct pci_dev *dev);
34
35 enum pci_mmap_api {
36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
38 };
39 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
40 enum pci_mmap_api mmap_api);
41
42 int pci_probe_reset_function(struct pci_dev *dev);
43 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
44 int pci_bus_error_reset(struct pci_dev *dev);
45
46 #define PCI_PM_D2_DELAY 200
47 #define PCI_PM_D3_WAIT 10
48 #define PCI_PM_D3COLD_WAIT 100
49 #define PCI_PM_BUS_WAIT 50
50
51 /*
52 * Following exit from Conventional Reset, devices must be ready within 1 sec
53 * (PCIe r6.0 sec 6.6.1). A D3cold to D0 transition implies a Conventional
54 * Reset (PCIe r6.0 sec 5.8).
55 */
56 #define PCI_RESET_WAIT 1000 /* msec */
57
58 /**
59 * struct pci_platform_pm_ops - Firmware PM callbacks
60 *
61 * @bridge_d3: Does the bridge allow entering into D3
62 *
63 * @is_manageable: returns 'true' if given device is power manageable by the
64 * platform firmware
65 *
66 * @set_state: invokes the platform firmware to set the device's power state
67 *
68 * @get_state: queries the platform firmware for a device's current power state
69 *
70 * @refresh_state: asks the platform to refresh the device's power state data
71 *
72 * @choose_state: returns PCI power state of given device preferred by the
73 * platform; to be used during system-wide transitions from a
74 * sleeping state to the working state and vice versa
75 *
76 * @set_wakeup: enables/disables wakeup capability for the device
77 *
78 * @need_resume: returns 'true' if the given device (which is currently
79 * suspended) needs to be resumed to be configured for system
80 * wakeup.
81 *
82 * If given platform is generally capable of power managing PCI devices, all of
83 * these callbacks are mandatory.
84 */
85 struct pci_platform_pm_ops {
86 bool (*bridge_d3)(struct pci_dev *dev);
87 bool (*is_manageable)(struct pci_dev *dev);
88 int (*set_state)(struct pci_dev *dev, pci_power_t state);
89 pci_power_t (*get_state)(struct pci_dev *dev);
90 void (*refresh_state)(struct pci_dev *dev);
91 pci_power_t (*choose_state)(struct pci_dev *dev);
92 int (*set_wakeup)(struct pci_dev *dev, bool enable);
93 bool (*need_resume)(struct pci_dev *dev);
94 };
95
96 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
97 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
98 void pci_refresh_power_state(struct pci_dev *dev);
99 void pci_power_up(struct pci_dev *dev);
100 void pci_disable_enabled_device(struct pci_dev *dev);
101 int pci_finish_runtime_suspend(struct pci_dev *dev);
102 void pcie_clear_root_pme_status(struct pci_dev *dev);
103 bool pci_check_pme_status(struct pci_dev *dev);
104 void pci_pme_wakeup_bus(struct pci_bus *bus);
105 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
106 void pci_pme_restore(struct pci_dev *dev);
107 bool pci_dev_need_resume(struct pci_dev *dev);
108 void pci_dev_adjust_pme(struct pci_dev *dev);
109 void pci_dev_complete_resume(struct pci_dev *pci_dev);
110 void pci_config_pm_runtime_get(struct pci_dev *dev);
111 void pci_config_pm_runtime_put(struct pci_dev *dev);
112 void pci_pm_init(struct pci_dev *dev);
113 void pci_ea_init(struct pci_dev *dev);
114 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
115 void pci_free_cap_save_buffers(struct pci_dev *dev);
116 bool pci_bridge_d3_possible(struct pci_dev *dev);
117 void pci_bridge_d3_update(struct pci_dev *dev);
118 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
119 int timeout);
120
pci_wakeup_event(struct pci_dev * dev)121 static inline void pci_wakeup_event(struct pci_dev *dev)
122 {
123 /* Wait 100 ms before the system can be put into a sleep state. */
124 pm_wakeup_event(&dev->dev, 100);
125 }
126
pci_has_subordinate(struct pci_dev * pci_dev)127 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
128 {
129 return !!(pci_dev->subordinate);
130 }
131
pci_power_manageable(struct pci_dev * pci_dev)132 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
133 {
134 /*
135 * Currently we allow normal PCI devices and PCI bridges transition
136 * into D3 if their bridge_d3 is set.
137 */
138 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
139 }
140
pcie_downstream_port(const struct pci_dev * dev)141 static inline bool pcie_downstream_port(const struct pci_dev *dev)
142 {
143 int type = pci_pcie_type(dev);
144
145 return type == PCI_EXP_TYPE_ROOT_PORT ||
146 type == PCI_EXP_TYPE_DOWNSTREAM ||
147 type == PCI_EXP_TYPE_PCIE_BRIDGE;
148 }
149
150 int pci_vpd_init(struct pci_dev *dev);
151 void pci_vpd_release(struct pci_dev *dev);
152 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
153 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
154
155 /* PCI Virtual Channel */
156 int pci_save_vc_state(struct pci_dev *dev);
157 void pci_restore_vc_state(struct pci_dev *dev);
158 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
159
160 /* PCI /proc functions */
161 #ifdef CONFIG_PROC_FS
162 int pci_proc_attach_device(struct pci_dev *dev);
163 int pci_proc_detach_device(struct pci_dev *dev);
164 int pci_proc_detach_bus(struct pci_bus *bus);
165 #else
pci_proc_attach_device(struct pci_dev * dev)166 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_device(struct pci_dev * dev)167 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_bus(struct pci_bus * bus)168 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
169 #endif
170
171 /* Functions for PCI Hotplug drivers to use */
172 int pci_hp_add_bridge(struct pci_dev *dev);
173
174 #ifdef HAVE_PCI_LEGACY
175 void pci_create_legacy_files(struct pci_bus *bus);
176 void pci_remove_legacy_files(struct pci_bus *bus);
177 #else
pci_create_legacy_files(struct pci_bus * bus)178 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
pci_remove_legacy_files(struct pci_bus * bus)179 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
180 #endif
181
182 /* Lock for read/write access to pci device and bus lists */
183 extern struct rw_semaphore pci_bus_sem;
184 extern struct mutex pci_slot_mutex;
185
186 extern raw_spinlock_t pci_lock;
187
188 extern unsigned int pci_pm_d3_delay;
189
190 #ifdef CONFIG_PCI_MSI
191 void pci_no_msi(void);
192 #else
pci_no_msi(void)193 static inline void pci_no_msi(void) { }
194 #endif
195
pci_msi_set_enable(struct pci_dev * dev,int enable)196 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
197 {
198 u16 control;
199
200 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
201 control &= ~PCI_MSI_FLAGS_ENABLE;
202 if (enable)
203 control |= PCI_MSI_FLAGS_ENABLE;
204 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
205 }
206
pci_msix_clear_and_set_ctrl(struct pci_dev * dev,u16 clear,u16 set)207 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
208 {
209 u16 ctrl;
210
211 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
212 ctrl &= ~clear;
213 ctrl |= set;
214 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
215 }
216
217 void pci_realloc_get_opt(char *);
218
pci_no_d1d2(struct pci_dev * dev)219 static inline int pci_no_d1d2(struct pci_dev *dev)
220 {
221 unsigned int parent_dstates = 0;
222
223 if (dev->bus->self)
224 parent_dstates = dev->bus->self->no_d1d2;
225 return (dev->no_d1d2 || parent_dstates);
226
227 }
228 extern const struct attribute_group *pci_dev_groups[];
229 extern const struct attribute_group *pcibus_groups[];
230 extern const struct device_type pci_dev_type;
231 extern const struct attribute_group *pci_bus_groups[];
232
233 extern unsigned long pci_hotplug_io_size;
234 extern unsigned long pci_hotplug_mem_size;
235 extern unsigned long pci_hotplug_bus_size;
236
237 /**
238 * pci_match_one_device - Tell if a PCI device structure has a matching
239 * PCI device id structure
240 * @id: single PCI device id structure to match
241 * @dev: the PCI device structure to match against
242 *
243 * Returns the matching pci_device_id structure or %NULL if there is no match.
244 */
245 static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id * id,const struct pci_dev * dev)246 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
247 {
248 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
249 (id->device == PCI_ANY_ID || id->device == dev->device) &&
250 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
251 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
252 !((id->class ^ dev->class) & id->class_mask))
253 return id;
254 return NULL;
255 }
256
257 /* PCI slot sysfs helper code */
258 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
259
260 extern struct kset *pci_slots_kset;
261
262 struct pci_slot_attribute {
263 struct attribute attr;
264 ssize_t (*show)(struct pci_slot *, char *);
265 ssize_t (*store)(struct pci_slot *, const char *, size_t);
266 };
267 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
268
269 enum pci_bar_type {
270 pci_bar_unknown, /* Standard PCI BAR probe */
271 pci_bar_io, /* An I/O port BAR */
272 pci_bar_mem32, /* A 32-bit memory BAR */
273 pci_bar_mem64, /* A 64-bit memory BAR */
274 };
275
276 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
277 void pci_put_host_bridge_device(struct device *dev);
278
279 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
280 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
281 int crs_timeout);
282 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
283 int crs_timeout);
284 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
285
286 int pci_setup_device(struct pci_dev *dev);
287 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
288 struct resource *res, unsigned int reg);
289 void pci_configure_ari(struct pci_dev *dev);
290 void __pci_bus_size_bridges(struct pci_bus *bus,
291 struct list_head *realloc_head);
292 void __pci_bus_assign_resources(const struct pci_bus *bus,
293 struct list_head *realloc_head,
294 struct list_head *fail_head);
295 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
296
297 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
298 void pci_disable_bridge_window(struct pci_dev *dev);
299 struct pci_bus *pci_bus_get(struct pci_bus *bus);
300 void pci_bus_put(struct pci_bus *bus);
301
302 /* PCIe link information */
303 #define PCIE_SPEED2STR(speed) \
304 ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
305 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
306 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
307 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
308 "Unknown speed")
309
310 /* PCIe speed to Mb/s reduced by encoding overhead */
311 #define PCIE_SPEED2MBS_ENC(speed) \
312 ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
313 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
314 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
315 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
316 0)
317
318 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
319 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
320 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
321 enum pcie_link_width *width);
322 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
323 void pcie_report_downtraining(struct pci_dev *dev);
324 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
325
326 /* Single Root I/O Virtualization */
327 struct pci_sriov {
328 int pos; /* Capability position */
329 int nres; /* Number of resources */
330 u32 cap; /* SR-IOV Capabilities */
331 u16 ctrl; /* SR-IOV Control */
332 u16 total_VFs; /* Total VFs associated with the PF */
333 u16 initial_VFs; /* Initial VFs associated with the PF */
334 u16 num_VFs; /* Number of VFs available */
335 u16 offset; /* First VF Routing ID offset */
336 u16 stride; /* Following VF stride */
337 u16 vf_device; /* VF device ID */
338 u32 pgsz; /* Page size for BAR alignment */
339 u8 link; /* Function Dependency Link */
340 u8 max_VF_buses; /* Max buses consumed by VFs */
341 u16 driver_max_VFs; /* Max num VFs driver supports */
342 struct pci_dev *dev; /* Lowest numbered PF */
343 struct pci_dev *self; /* This PF */
344 u32 class; /* VF device */
345 u8 hdr_type; /* VF header type */
346 u16 subsystem_vendor; /* VF subsystem vendor */
347 u16 subsystem_device; /* VF subsystem device */
348 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
349 bool drivers_autoprobe; /* Auto probing of VFs by driver */
350
351 ANDROID_KABI_RESERVE(1);
352 ANDROID_KABI_RESERVE(2);
353 ANDROID_KABI_RESERVE(3);
354 ANDROID_KABI_RESERVE(4);
355 };
356
357 /**
358 * pci_dev_set_io_state - Set the new error state if possible.
359 *
360 * @dev - pci device to set new error_state
361 * @new - the state we want dev to be in
362 *
363 * If the device is experiencing perm_failure, it has to remain in that state.
364 * Any other transition is allowed.
365 *
366 * Returns true if state has been changed to the requested state.
367 */
pci_dev_set_io_state(struct pci_dev * dev,pci_channel_state_t new)368 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
369 pci_channel_state_t new)
370 {
371 pci_channel_state_t old;
372
373 switch (new) {
374 case pci_channel_io_perm_failure:
375 xchg(&dev->error_state, pci_channel_io_perm_failure);
376 return true;
377 case pci_channel_io_frozen:
378 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
379 pci_channel_io_frozen);
380 return old != pci_channel_io_perm_failure;
381 case pci_channel_io_normal:
382 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
383 pci_channel_io_normal);
384 return old != pci_channel_io_perm_failure;
385 default:
386 return false;
387 }
388 }
389
pci_dev_set_disconnected(struct pci_dev * dev,void * unused)390 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
391 {
392 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
393
394 return 0;
395 }
396
pci_dev_is_disconnected(const struct pci_dev * dev)397 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
398 {
399 return dev->error_state == pci_channel_io_perm_failure;
400 }
401
402 /* pci_dev priv_flags */
403 #define PCI_DEV_ADDED 0
404
pci_dev_assign_added(struct pci_dev * dev,bool added)405 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
406 {
407 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
408 }
409
pci_dev_is_added(const struct pci_dev * dev)410 static inline bool pci_dev_is_added(const struct pci_dev *dev)
411 {
412 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
413 }
414
415 #ifdef CONFIG_PCIEAER
416 #include <linux/aer.h>
417
418 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
419
420 struct aer_err_info {
421 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
422 int error_dev_num;
423
424 unsigned int id:16;
425
426 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
427 unsigned int __pad1:5;
428 unsigned int multi_error_valid:1;
429
430 unsigned int first_error:5;
431 unsigned int __pad2:2;
432 unsigned int tlp_header_valid:1;
433
434 unsigned int status; /* COR/UNCOR Error Status */
435 unsigned int mask; /* COR/UNCOR Error Mask */
436 struct aer_header_log_regs tlp; /* TLP Header */
437 };
438
439 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
440 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
441 #endif /* CONFIG_PCIEAER */
442
443 #ifdef CONFIG_PCIE_DPC
444 void pci_save_dpc_state(struct pci_dev *dev);
445 void pci_restore_dpc_state(struct pci_dev *dev);
446 #else
pci_save_dpc_state(struct pci_dev * dev)447 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
pci_restore_dpc_state(struct pci_dev * dev)448 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
449 #endif
450
451 #ifdef CONFIG_PCI_ATS
452 /* Address Translation Service */
453 void pci_ats_init(struct pci_dev *dev);
454 void pci_restore_ats_state(struct pci_dev *dev);
455 #else
pci_ats_init(struct pci_dev * d)456 static inline void pci_ats_init(struct pci_dev *d) { }
pci_restore_ats_state(struct pci_dev * dev)457 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
458 #endif /* CONFIG_PCI_ATS */
459
460 #ifdef CONFIG_PCI_IOV
461 int pci_iov_init(struct pci_dev *dev);
462 void pci_iov_release(struct pci_dev *dev);
463 void pci_iov_remove(struct pci_dev *dev);
464 void pci_iov_update_resource(struct pci_dev *dev, int resno);
465 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
466 void pci_restore_iov_state(struct pci_dev *dev);
467 int pci_iov_bus_range(struct pci_bus *bus);
468 extern const struct attribute_group sriov_dev_attr_group;
469 #else
pci_iov_init(struct pci_dev * dev)470 static inline int pci_iov_init(struct pci_dev *dev)
471 {
472 return -ENODEV;
473 }
pci_iov_release(struct pci_dev * dev)474 static inline void pci_iov_release(struct pci_dev *dev)
475
476 {
477 }
pci_iov_remove(struct pci_dev * dev)478 static inline void pci_iov_remove(struct pci_dev *dev)
479 {
480 }
pci_restore_iov_state(struct pci_dev * dev)481 static inline void pci_restore_iov_state(struct pci_dev *dev)
482 {
483 }
pci_iov_bus_range(struct pci_bus * bus)484 static inline int pci_iov_bus_range(struct pci_bus *bus)
485 {
486 return 0;
487 }
488
489 #endif /* CONFIG_PCI_IOV */
490
491 unsigned long pci_cardbus_resource_alignment(struct resource *);
492
pci_resource_alignment(struct pci_dev * dev,struct resource * res)493 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
494 struct resource *res)
495 {
496 #ifdef CONFIG_PCI_IOV
497 int resno = res - dev->resource;
498
499 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
500 return pci_sriov_resource_alignment(dev, resno);
501 #endif
502 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
503 return pci_cardbus_resource_alignment(res);
504 return resource_alignment(res);
505 }
506
507 void pci_enable_acs(struct pci_dev *dev);
508 #ifdef CONFIG_PCI_QUIRKS
509 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
510 int pci_dev_specific_enable_acs(struct pci_dev *dev);
511 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
512 #else
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)513 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
514 u16 acs_flags)
515 {
516 return -ENOTTY;
517 }
pci_dev_specific_enable_acs(struct pci_dev * dev)518 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
519 {
520 return -ENOTTY;
521 }
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)522 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
523 {
524 return -ENOTTY;
525 }
526 #endif
527
528 /* PCI error reporting and recovery */
529 void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,
530 u32 service);
531
532 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
533 #ifdef CONFIG_PCIEASPM
534 void pcie_aspm_init_link_state(struct pci_dev *pdev);
535 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
536 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
537 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
538 #else
pcie_aspm_init_link_state(struct pci_dev * pdev)539 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
pcie_aspm_exit_link_state(struct pci_dev * pdev)540 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
pcie_aspm_pm_state_change(struct pci_dev * pdev)541 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
pcie_aspm_powersave_config_link(struct pci_dev * pdev)542 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
543 #endif
544
545 #ifdef CONFIG_PCIEASPM_DEBUG
546 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
547 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
548 #else
pcie_aspm_create_sysfs_dev_files(struct pci_dev * pdev)549 static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
pcie_aspm_remove_sysfs_dev_files(struct pci_dev * pdev)550 static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
551 #endif
552
553 #ifdef CONFIG_PCIE_ECRC
554 void pcie_set_ecrc_checking(struct pci_dev *dev);
555 void pcie_ecrc_get_policy(char *str);
556 #else
pcie_set_ecrc_checking(struct pci_dev * dev)557 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)558 static inline void pcie_ecrc_get_policy(char *str) { }
559 #endif
560
561 #ifdef CONFIG_PCIE_PTM
562 void pci_ptm_init(struct pci_dev *dev);
563 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
564 #else
pci_ptm_init(struct pci_dev * dev)565 static inline void pci_ptm_init(struct pci_dev *dev) { }
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)566 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
567 { return -EINVAL; }
568 #endif
569
570 struct pci_dev_reset_methods {
571 u16 vendor;
572 u16 device;
573 int (*reset)(struct pci_dev *dev, int probe);
574 };
575
576 #ifdef CONFIG_PCI_QUIRKS
577 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
578 #else
pci_dev_specific_reset(struct pci_dev * dev,int probe)579 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
580 {
581 return -ENOTTY;
582 }
583 #endif
584
585 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
586 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
587 struct resource *res);
588 #else
acpi_get_rc_resources(struct device * dev,const char * hid,u16 segment,struct resource * res)589 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
590 u16 segment, struct resource *res)
591 {
592 return -ENODEV;
593 }
594 #endif
595
596 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
597 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
598 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
pci_rebar_size_to_bytes(int size)599 static inline u64 pci_rebar_size_to_bytes(int size)
600 {
601 return 1ULL << (size + 20);
602 }
603
604 struct device_node;
605
606 #ifdef CONFIG_OF
607 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
608 int of_get_pci_domain_nr(struct device_node *node);
609 int of_pci_get_max_link_speed(struct device_node *node);
610 void pci_set_of_node(struct pci_dev *dev);
611 void pci_release_of_node(struct pci_dev *dev);
612 void pci_set_bus_of_node(struct pci_bus *bus);
613 void pci_release_bus_of_node(struct pci_bus *bus);
614
615 #else
616 static inline int
of_pci_parse_bus_range(struct device_node * node,struct resource * res)617 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
618 {
619 return -EINVAL;
620 }
621
622 static inline int
of_get_pci_domain_nr(struct device_node * node)623 of_get_pci_domain_nr(struct device_node *node)
624 {
625 return -1;
626 }
627
628 static inline int
of_pci_get_max_link_speed(struct device_node * node)629 of_pci_get_max_link_speed(struct device_node *node)
630 {
631 return -EINVAL;
632 }
633
pci_set_of_node(struct pci_dev * dev)634 static inline void pci_set_of_node(struct pci_dev *dev) { }
pci_release_of_node(struct pci_dev * dev)635 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)636 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)637 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
638 #endif /* CONFIG_OF */
639
640 #if defined(CONFIG_OF_ADDRESS)
641 int devm_of_pci_get_host_bridge_resources(struct device *dev,
642 unsigned char busno, unsigned char bus_max,
643 struct list_head *resources, resource_size_t *io_base);
644 #else
devm_of_pci_get_host_bridge_resources(struct device * dev,unsigned char busno,unsigned char bus_max,struct list_head * resources,resource_size_t * io_base)645 static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
646 unsigned char busno, unsigned char bus_max,
647 struct list_head *resources, resource_size_t *io_base)
648 {
649 return -EINVAL;
650 }
651 #endif
652
653 #ifdef CONFIG_PCIEAER
654 void pci_no_aer(void);
655 void pci_aer_init(struct pci_dev *dev);
656 void pci_aer_exit(struct pci_dev *dev);
657 extern const struct attribute_group aer_stats_attr_group;
658 void pci_aer_clear_fatal_status(struct pci_dev *dev);
659 void pci_aer_clear_device_status(struct pci_dev *dev);
660 #else
pci_no_aer(void)661 static inline void pci_no_aer(void) { }
pci_aer_init(struct pci_dev * d)662 static inline void pci_aer_init(struct pci_dev *d) { }
pci_aer_exit(struct pci_dev * d)663 static inline void pci_aer_exit(struct pci_dev *d) { }
pci_aer_clear_fatal_status(struct pci_dev * dev)664 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
pci_aer_clear_device_status(struct pci_dev * dev)665 static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
666 #endif
667
668 #ifdef CONFIG_ACPI
669 int pci_acpi_program_hp_params(struct pci_dev *dev);
670 #else
pci_acpi_program_hp_params(struct pci_dev * dev)671 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
672 {
673 return -ENODEV;
674 }
675 #endif
676
677 #endif /* DRIVERS_PCI_H */
678