1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl GPIO driver for Intel Baytrail
4 *
5 * Copyright (c) 2012-2013, Intel Corporation
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/property.h>
20 #include <linux/seq_file.h>
21
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26
27 #include "pinctrl-intel.h"
28
29 /* memory mapped register offsets */
30 #define BYT_CONF0_REG 0x000
31 #define BYT_CONF1_REG 0x004
32 #define BYT_VAL_REG 0x008
33 #define BYT_DFT_REG 0x00c
34 #define BYT_INT_STAT_REG 0x800
35 #define BYT_DEBOUNCE_REG 0x9d0
36
37 /* BYT_CONF0_REG register bits */
38 #define BYT_IODEN BIT(31)
39 #define BYT_DIRECT_IRQ_EN BIT(27)
40 #define BYT_TRIG_MASK GENMASK(26, 24)
41 #define BYT_TRIG_NEG BIT(26)
42 #define BYT_TRIG_POS BIT(25)
43 #define BYT_TRIG_LVL BIT(24)
44 #define BYT_DEBOUNCE_EN BIT(20)
45 #define BYT_GLITCH_FILTER_EN BIT(19)
46 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
47 #define BYT_GLITCH_F_FAST_CLK BIT(16)
48 #define BYT_PULL_STR_SHIFT 9
49 #define BYT_PULL_STR_MASK GENMASK(10, 9)
50 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
51 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_ASSIGN_SHIFT 7
55 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
56 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
57 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PIN_MUX GENMASK(2, 0)
59
60 /* BYT_VAL_REG register bits */
61 #define BYT_DIR_MASK GENMASK(2, 1)
62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
64 #define BYT_LEVEL BIT(0)
65
66 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
67 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
68
69 /* BYT_DEBOUNCE_REG bits */
70 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)
71 #define BYT_DEBOUNCE_PULSE_375US 1
72 #define BYT_DEBOUNCE_PULSE_750US 2
73 #define BYT_DEBOUNCE_PULSE_1500US 3
74 #define BYT_DEBOUNCE_PULSE_3MS 4
75 #define BYT_DEBOUNCE_PULSE_6MS 5
76 #define BYT_DEBOUNCE_PULSE_12MS 6
77 #define BYT_DEBOUNCE_PULSE_24MS 7
78
79 #define BYT_NGPIO_SCORE 102
80 #define BYT_NGPIO_NCORE 28
81 #define BYT_NGPIO_SUS 44
82
83 #define BYT_SCORE_ACPI_UID "1"
84 #define BYT_NCORE_ACPI_UID "2"
85 #define BYT_SUS_ACPI_UID "3"
86
87 /*
88 * This is the function value most pins have for GPIO muxing. If the value
89 * differs from the default one, it must be explicitly mentioned. Otherwise, the
90 * pin control implementation will set the muxing value to default GPIO if it
91 * does not find a match for the requested function.
92 */
93 #define BYT_DEFAULT_GPIO_MUX 0
94 #define BYT_ALTER_GPIO_MUX 1
95
96 struct byt_gpio_pin_context {
97 u32 conf0;
98 u32 val;
99 };
100
101 #define COMMUNITY(p, n, map) \
102 { \
103 .pin_base = (p), \
104 .npins = (n), \
105 .pad_map = (map),\
106 }
107
108 struct byt_gpio {
109 struct gpio_chip chip;
110 struct platform_device *pdev;
111 struct pinctrl_dev *pctl_dev;
112 struct pinctrl_desc pctl_desc;
113 const struct intel_pinctrl_soc_data *soc_data;
114 struct intel_community *communities_copy;
115 struct byt_gpio_pin_context *saved_context;
116 };
117
118 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
119 static const struct pinctrl_pin_desc byt_score_pins[] = {
120 PINCTRL_PIN(0, "SATA_GP0"),
121 PINCTRL_PIN(1, "SATA_GP1"),
122 PINCTRL_PIN(2, "SATA_LED#"),
123 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
124 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
125 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
126 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
127 PINCTRL_PIN(7, "SD3_WP"),
128 PINCTRL_PIN(8, "HDA_RST"),
129 PINCTRL_PIN(9, "HDA_SYNC"),
130 PINCTRL_PIN(10, "HDA_CLK"),
131 PINCTRL_PIN(11, "HDA_SDO"),
132 PINCTRL_PIN(12, "HDA_SDI0"),
133 PINCTRL_PIN(13, "HDA_SDI1"),
134 PINCTRL_PIN(14, "GPIO_S0_SC14"),
135 PINCTRL_PIN(15, "GPIO_S0_SC15"),
136 PINCTRL_PIN(16, "MMC1_CLK"),
137 PINCTRL_PIN(17, "MMC1_D0"),
138 PINCTRL_PIN(18, "MMC1_D1"),
139 PINCTRL_PIN(19, "MMC1_D2"),
140 PINCTRL_PIN(20, "MMC1_D3"),
141 PINCTRL_PIN(21, "MMC1_D4"),
142 PINCTRL_PIN(22, "MMC1_D5"),
143 PINCTRL_PIN(23, "MMC1_D6"),
144 PINCTRL_PIN(24, "MMC1_D7"),
145 PINCTRL_PIN(25, "MMC1_CMD"),
146 PINCTRL_PIN(26, "MMC1_RST"),
147 PINCTRL_PIN(27, "SD2_CLK"),
148 PINCTRL_PIN(28, "SD2_D0"),
149 PINCTRL_PIN(29, "SD2_D1"),
150 PINCTRL_PIN(30, "SD2_D2"),
151 PINCTRL_PIN(31, "SD2_D3_CD"),
152 PINCTRL_PIN(32, "SD2_CMD"),
153 PINCTRL_PIN(33, "SD3_CLK"),
154 PINCTRL_PIN(34, "SD3_D0"),
155 PINCTRL_PIN(35, "SD3_D1"),
156 PINCTRL_PIN(36, "SD3_D2"),
157 PINCTRL_PIN(37, "SD3_D3"),
158 PINCTRL_PIN(38, "SD3_CD"),
159 PINCTRL_PIN(39, "SD3_CMD"),
160 PINCTRL_PIN(40, "SD3_1P8EN"),
161 PINCTRL_PIN(41, "SD3_PWREN#"),
162 PINCTRL_PIN(42, "ILB_LPC_AD0"),
163 PINCTRL_PIN(43, "ILB_LPC_AD1"),
164 PINCTRL_PIN(44, "ILB_LPC_AD2"),
165 PINCTRL_PIN(45, "ILB_LPC_AD3"),
166 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
167 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
168 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
169 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
170 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
171 PINCTRL_PIN(51, "PCU_SMB_DATA"),
172 PINCTRL_PIN(52, "PCU_SMB_CLK"),
173 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
174 PINCTRL_PIN(54, "ILB_8254_SPKR"),
175 PINCTRL_PIN(55, "GPIO_S0_SC55"),
176 PINCTRL_PIN(56, "GPIO_S0_SC56"),
177 PINCTRL_PIN(57, "GPIO_S0_SC57"),
178 PINCTRL_PIN(58, "GPIO_S0_SC58"),
179 PINCTRL_PIN(59, "GPIO_S0_SC59"),
180 PINCTRL_PIN(60, "GPIO_S0_SC60"),
181 PINCTRL_PIN(61, "GPIO_S0_SC61"),
182 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
183 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
184 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
185 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
186 PINCTRL_PIN(66, "SIO_SPI_CS"),
187 PINCTRL_PIN(67, "SIO_SPI_MISO"),
188 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
189 PINCTRL_PIN(69, "SIO_SPI_CLK"),
190 PINCTRL_PIN(70, "SIO_UART1_RXD"),
191 PINCTRL_PIN(71, "SIO_UART1_TXD"),
192 PINCTRL_PIN(72, "SIO_UART1_RTS"),
193 PINCTRL_PIN(73, "SIO_UART1_CTS"),
194 PINCTRL_PIN(74, "SIO_UART2_RXD"),
195 PINCTRL_PIN(75, "SIO_UART2_TXD"),
196 PINCTRL_PIN(76, "SIO_UART2_RTS"),
197 PINCTRL_PIN(77, "SIO_UART2_CTS"),
198 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
199 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
200 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
201 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
202 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
203 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
204 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
205 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
206 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
207 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
208 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
209 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
210 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
211 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
212 PINCTRL_PIN(92, "GPIO_S0_SC92"),
213 PINCTRL_PIN(93, "GPIO_S0_SC93"),
214 PINCTRL_PIN(94, "SIO_PWM0"),
215 PINCTRL_PIN(95, "SIO_PWM1"),
216 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
217 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
218 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
219 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
220 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
221 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
222 };
223
224 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
225 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
226 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
227 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
228 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
229 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
230 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
231 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
232 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
233 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
234 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
235 97, 100,
236 };
237
238 /* SCORE groups */
239 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
240 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
241
242 static const unsigned int byt_score_pwm0_pins[] = { 94 };
243 static const unsigned int byt_score_pwm1_pins[] = { 95 };
244
245 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
246
247 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
248 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
249 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
250 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
251 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
252 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
253 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
254
255 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
256 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
257 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
258
259 static const unsigned int byt_score_sdcard_pins[] = {
260 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
261 };
262 static const unsigned int byt_score_sdcard_mux_values[] = {
263 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
264 };
265
266 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
267
268 static const unsigned int byt_score_emmc_pins[] = {
269 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
270 };
271
272 static const unsigned int byt_score_ilb_lpc_pins[] = {
273 42, 43, 44, 45, 46, 47, 48, 49, 50,
274 };
275
276 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
277
278 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
279 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
280 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
281 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
282 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
283 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
284
285 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
286
287 static const struct intel_pingroup byt_score_groups[] = {
288 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
289 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
290 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
291 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
292 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
293 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
294 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
295 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
296 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
297 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
298 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
299 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
300 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
301 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
302 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
303 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
304 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
305 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
306 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
307 PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
308 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
309 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
310 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
311 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
312 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
313 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
314 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
315 };
316
317 static const char * const byt_score_uart_groups[] = {
318 "uart1_grp", "uart2_grp",
319 };
320 static const char * const byt_score_pwm_groups[] = {
321 "pwm0_grp", "pwm1_grp",
322 };
323 static const char * const byt_score_ssp_groups[] = {
324 "ssp0_grp", "ssp1_grp", "ssp2_grp",
325 };
326 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
327 static const char * const byt_score_i2c_groups[] = {
328 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
329 "i2c6_grp",
330 };
331 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
332 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
333 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
334 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
335 static const char * const byt_score_sata_groups[] = { "sata_grp" };
336 static const char * const byt_score_plt_clk_groups[] = {
337 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
338 "plt_clk4_grp", "plt_clk5_grp",
339 };
340 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
341 static const char * const byt_score_gpio_groups[] = {
342 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
343 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
344 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
345 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
346 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
347 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
348 };
349
350 static const struct intel_function byt_score_functions[] = {
351 FUNCTION("uart", byt_score_uart_groups),
352 FUNCTION("pwm", byt_score_pwm_groups),
353 FUNCTION("ssp", byt_score_ssp_groups),
354 FUNCTION("spi", byt_score_spi_groups),
355 FUNCTION("i2c", byt_score_i2c_groups),
356 FUNCTION("sdcard", byt_score_sdcard_groups),
357 FUNCTION("sdio", byt_score_sdio_groups),
358 FUNCTION("emmc", byt_score_emmc_groups),
359 FUNCTION("lpc", byt_score_lpc_groups),
360 FUNCTION("sata", byt_score_sata_groups),
361 FUNCTION("plt_clk", byt_score_plt_clk_groups),
362 FUNCTION("smbus", byt_score_smbus_groups),
363 FUNCTION("gpio", byt_score_gpio_groups),
364 };
365
366 static const struct intel_community byt_score_communities[] = {
367 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
368 };
369
370 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
371 .uid = BYT_SCORE_ACPI_UID,
372 .pins = byt_score_pins,
373 .npins = ARRAY_SIZE(byt_score_pins),
374 .groups = byt_score_groups,
375 .ngroups = ARRAY_SIZE(byt_score_groups),
376 .functions = byt_score_functions,
377 .nfunctions = ARRAY_SIZE(byt_score_functions),
378 .communities = byt_score_communities,
379 .ncommunities = ARRAY_SIZE(byt_score_communities),
380 };
381
382 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
383 static const struct pinctrl_pin_desc byt_sus_pins[] = {
384 PINCTRL_PIN(0, "GPIO_S50"),
385 PINCTRL_PIN(1, "GPIO_S51"),
386 PINCTRL_PIN(2, "GPIO_S52"),
387 PINCTRL_PIN(3, "GPIO_S53"),
388 PINCTRL_PIN(4, "GPIO_S54"),
389 PINCTRL_PIN(5, "GPIO_S55"),
390 PINCTRL_PIN(6, "GPIO_S56"),
391 PINCTRL_PIN(7, "GPIO_S57"),
392 PINCTRL_PIN(8, "GPIO_S58"),
393 PINCTRL_PIN(9, "GPIO_S59"),
394 PINCTRL_PIN(10, "GPIO_S510"),
395 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
396 PINCTRL_PIN(12, "PMC_SUSCLK0"),
397 PINCTRL_PIN(13, "GPIO_S513"),
398 PINCTRL_PIN(14, "USB_ULPI_RST"),
399 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
400 PINCTRL_PIN(16, "PMC_PWRBTN"),
401 PINCTRL_PIN(17, "GPIO_S517"),
402 PINCTRL_PIN(18, "PMC_SUS_STAT"),
403 PINCTRL_PIN(19, "USB_OC0"),
404 PINCTRL_PIN(20, "USB_OC1"),
405 PINCTRL_PIN(21, "PCU_SPI_CS1"),
406 PINCTRL_PIN(22, "GPIO_S522"),
407 PINCTRL_PIN(23, "GPIO_S523"),
408 PINCTRL_PIN(24, "GPIO_S524"),
409 PINCTRL_PIN(25, "GPIO_S525"),
410 PINCTRL_PIN(26, "GPIO_S526"),
411 PINCTRL_PIN(27, "GPIO_S527"),
412 PINCTRL_PIN(28, "GPIO_S528"),
413 PINCTRL_PIN(29, "GPIO_S529"),
414 PINCTRL_PIN(30, "GPIO_S530"),
415 PINCTRL_PIN(31, "USB_ULPI_CLK"),
416 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
417 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
418 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
419 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
420 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
421 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
422 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
423 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
424 PINCTRL_PIN(40, "USB_ULPI_DIR"),
425 PINCTRL_PIN(41, "USB_ULPI_NXT"),
426 PINCTRL_PIN(42, "USB_ULPI_STP"),
427 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
428 };
429
430 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
431 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
432 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
433 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
434 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
435 52, 53, 59, 40,
436 };
437
438 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
439 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
440 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
441
442 static const unsigned int byt_sus_usb_ulpi_pins[] = {
443 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
444 };
445 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
446 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
447 };
448 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
449 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
450 };
451
452 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
453 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
454 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
455
456 static const struct intel_pingroup byt_sus_groups[] = {
457 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
458 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
459 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
460 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
461 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
462 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
463 };
464
465 static const char * const byt_sus_usb_groups[] = {
466 "usb_oc_grp", "usb_ulpi_grp",
467 };
468 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
469 static const char * const byt_sus_gpio_groups[] = {
470 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
471 };
472
473 static const struct intel_function byt_sus_functions[] = {
474 FUNCTION("usb", byt_sus_usb_groups),
475 FUNCTION("spi", byt_sus_spi_groups),
476 FUNCTION("gpio", byt_sus_gpio_groups),
477 };
478
479 static const struct intel_community byt_sus_communities[] = {
480 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
481 };
482
483 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
484 .uid = BYT_SUS_ACPI_UID,
485 .pins = byt_sus_pins,
486 .npins = ARRAY_SIZE(byt_sus_pins),
487 .groups = byt_sus_groups,
488 .ngroups = ARRAY_SIZE(byt_sus_groups),
489 .functions = byt_sus_functions,
490 .nfunctions = ARRAY_SIZE(byt_sus_functions),
491 .communities = byt_sus_communities,
492 .ncommunities = ARRAY_SIZE(byt_sus_communities),
493 };
494
495 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
496 PINCTRL_PIN(0, "GPIO_NCORE0"),
497 PINCTRL_PIN(1, "GPIO_NCORE1"),
498 PINCTRL_PIN(2, "GPIO_NCORE2"),
499 PINCTRL_PIN(3, "GPIO_NCORE3"),
500 PINCTRL_PIN(4, "GPIO_NCORE4"),
501 PINCTRL_PIN(5, "GPIO_NCORE5"),
502 PINCTRL_PIN(6, "GPIO_NCORE6"),
503 PINCTRL_PIN(7, "GPIO_NCORE7"),
504 PINCTRL_PIN(8, "GPIO_NCORE8"),
505 PINCTRL_PIN(9, "GPIO_NCORE9"),
506 PINCTRL_PIN(10, "GPIO_NCORE10"),
507 PINCTRL_PIN(11, "GPIO_NCORE11"),
508 PINCTRL_PIN(12, "GPIO_NCORE12"),
509 PINCTRL_PIN(13, "GPIO_NCORE13"),
510 PINCTRL_PIN(14, "GPIO_NCORE14"),
511 PINCTRL_PIN(15, "GPIO_NCORE15"),
512 PINCTRL_PIN(16, "GPIO_NCORE16"),
513 PINCTRL_PIN(17, "GPIO_NCORE17"),
514 PINCTRL_PIN(18, "GPIO_NCORE18"),
515 PINCTRL_PIN(19, "GPIO_NCORE19"),
516 PINCTRL_PIN(20, "GPIO_NCORE20"),
517 PINCTRL_PIN(21, "GPIO_NCORE21"),
518 PINCTRL_PIN(22, "GPIO_NCORE22"),
519 PINCTRL_PIN(23, "GPIO_NCORE23"),
520 PINCTRL_PIN(24, "GPIO_NCORE24"),
521 PINCTRL_PIN(25, "GPIO_NCORE25"),
522 PINCTRL_PIN(26, "GPIO_NCORE26"),
523 PINCTRL_PIN(27, "GPIO_NCORE27"),
524 };
525
526 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
527 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
528 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
529 3, 6, 10, 13, 2, 5, 9, 7,
530 };
531
532 static const struct intel_community byt_ncore_communities[] = {
533 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
534 };
535
536 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
537 .uid = BYT_NCORE_ACPI_UID,
538 .pins = byt_ncore_pins,
539 .npins = ARRAY_SIZE(byt_ncore_pins),
540 .communities = byt_ncore_communities,
541 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
542 };
543
544 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
545 &byt_score_soc_data,
546 &byt_sus_soc_data,
547 &byt_ncore_soc_data,
548 NULL
549 };
550
551 static DEFINE_RAW_SPINLOCK(byt_lock);
552
byt_get_community(struct byt_gpio * vg,unsigned int pin)553 static struct intel_community *byt_get_community(struct byt_gpio *vg,
554 unsigned int pin)
555 {
556 struct intel_community *comm;
557 int i;
558
559 for (i = 0; i < vg->soc_data->ncommunities; i++) {
560 comm = vg->communities_copy + i;
561 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
562 return comm;
563 }
564
565 return NULL;
566 }
567
byt_gpio_reg(struct byt_gpio * vg,unsigned int offset,int reg)568 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
569 int reg)
570 {
571 struct intel_community *comm = byt_get_community(vg, offset);
572 u32 reg_offset;
573
574 if (!comm)
575 return NULL;
576
577 offset -= comm->pin_base;
578 switch (reg) {
579 case BYT_INT_STAT_REG:
580 reg_offset = (offset / 32) * 4;
581 break;
582 case BYT_DEBOUNCE_REG:
583 reg_offset = 0;
584 break;
585 default:
586 reg_offset = comm->pad_map[offset] * 16;
587 break;
588 }
589
590 return comm->pad_regs + reg_offset + reg;
591 }
592
byt_get_groups_count(struct pinctrl_dev * pctldev)593 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
594 {
595 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
596
597 return vg->soc_data->ngroups;
598 }
599
byt_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)600 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
601 unsigned int selector)
602 {
603 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
604
605 return vg->soc_data->groups[selector].name;
606 }
607
byt_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)608 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
609 unsigned int selector,
610 const unsigned int **pins,
611 unsigned int *num_pins)
612 {
613 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
614
615 *pins = vg->soc_data->groups[selector].pins;
616 *num_pins = vg->soc_data->groups[selector].npins;
617
618 return 0;
619 }
620
621 static const struct pinctrl_ops byt_pinctrl_ops = {
622 .get_groups_count = byt_get_groups_count,
623 .get_group_name = byt_get_group_name,
624 .get_group_pins = byt_get_group_pins,
625 };
626
byt_get_functions_count(struct pinctrl_dev * pctldev)627 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
628 {
629 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
630
631 return vg->soc_data->nfunctions;
632 }
633
byt_get_function_name(struct pinctrl_dev * pctldev,unsigned int selector)634 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
635 unsigned int selector)
636 {
637 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
638
639 return vg->soc_data->functions[selector].name;
640 }
641
byt_get_function_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * num_groups)642 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
643 unsigned int selector,
644 const char * const **groups,
645 unsigned int *num_groups)
646 {
647 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
648
649 *groups = vg->soc_data->functions[selector].groups;
650 *num_groups = vg->soc_data->functions[selector].ngroups;
651
652 return 0;
653 }
654
byt_set_group_simple_mux(struct byt_gpio * vg,const struct intel_pingroup group,unsigned int func)655 static void byt_set_group_simple_mux(struct byt_gpio *vg,
656 const struct intel_pingroup group,
657 unsigned int func)
658 {
659 unsigned long flags;
660 int i;
661
662 raw_spin_lock_irqsave(&byt_lock, flags);
663
664 for (i = 0; i < group.npins; i++) {
665 void __iomem *padcfg0;
666 u32 value;
667
668 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
669 if (!padcfg0) {
670 dev_warn(&vg->pdev->dev,
671 "Group %s, pin %i not muxed (no padcfg0)\n",
672 group.name, i);
673 continue;
674 }
675
676 value = readl(padcfg0);
677 value &= ~BYT_PIN_MUX;
678 value |= func;
679 writel(value, padcfg0);
680 }
681
682 raw_spin_unlock_irqrestore(&byt_lock, flags);
683 }
684
byt_set_group_mixed_mux(struct byt_gpio * vg,const struct intel_pingroup group,const unsigned int * func)685 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
686 const struct intel_pingroup group,
687 const unsigned int *func)
688 {
689 unsigned long flags;
690 int i;
691
692 raw_spin_lock_irqsave(&byt_lock, flags);
693
694 for (i = 0; i < group.npins; i++) {
695 void __iomem *padcfg0;
696 u32 value;
697
698 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
699 if (!padcfg0) {
700 dev_warn(&vg->pdev->dev,
701 "Group %s, pin %i not muxed (no padcfg0)\n",
702 group.name, i);
703 continue;
704 }
705
706 value = readl(padcfg0);
707 value &= ~BYT_PIN_MUX;
708 value |= func[i];
709 writel(value, padcfg0);
710 }
711
712 raw_spin_unlock_irqrestore(&byt_lock, flags);
713 }
714
byt_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)715 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
716 unsigned int group_selector)
717 {
718 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
719 const struct intel_function func = vg->soc_data->functions[func_selector];
720 const struct intel_pingroup group = vg->soc_data->groups[group_selector];
721
722 if (group.modes)
723 byt_set_group_mixed_mux(vg, group, group.modes);
724 else if (!strcmp(func.name, "gpio"))
725 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
726 else
727 byt_set_group_simple_mux(vg, group, group.mode);
728
729 return 0;
730 }
731
byt_get_gpio_mux(struct byt_gpio * vg,unsigned int offset)732 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned int offset)
733 {
734 /* SCORE pin 92-93 */
735 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
736 offset >= 92 && offset <= 93)
737 return BYT_ALTER_GPIO_MUX;
738
739 /* SUS pin 11-21 */
740 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
741 offset >= 11 && offset <= 21)
742 return BYT_ALTER_GPIO_MUX;
743
744 return BYT_DEFAULT_GPIO_MUX;
745 }
746
byt_gpio_clear_triggering(struct byt_gpio * vg,unsigned int offset)747 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
748 {
749 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
750 unsigned long flags;
751 u32 value;
752
753 raw_spin_lock_irqsave(&byt_lock, flags);
754 value = readl(reg);
755
756 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
757 if (value & BYT_DIRECT_IRQ_EN)
758 /* nothing to do */ ;
759 else
760 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
761
762 writel(value, reg);
763 raw_spin_unlock_irqrestore(&byt_lock, flags);
764 }
765
byt_gpio_request_enable(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)766 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
767 struct pinctrl_gpio_range *range,
768 unsigned int offset)
769 {
770 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
771 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
772 u32 value, gpio_mux;
773 unsigned long flags;
774
775 raw_spin_lock_irqsave(&byt_lock, flags);
776
777 /*
778 * In most cases, func pin mux 000 means GPIO function.
779 * But, some pins may have func pin mux 001 represents
780 * GPIO function.
781 *
782 * Because there are devices out there where some pins were not
783 * configured correctly we allow changing the mux value from
784 * request (but print out warning about that).
785 */
786 value = readl(reg) & BYT_PIN_MUX;
787 gpio_mux = byt_get_gpio_mux(vg, offset);
788 if (gpio_mux != value) {
789 value = readl(reg) & ~BYT_PIN_MUX;
790 value |= gpio_mux;
791 writel(value, reg);
792
793 dev_warn(&vg->pdev->dev, FW_BUG
794 "pin %u forcibly re-configured as GPIO\n", offset);
795 }
796
797 raw_spin_unlock_irqrestore(&byt_lock, flags);
798
799 pm_runtime_get(&vg->pdev->dev);
800
801 return 0;
802 }
803
byt_gpio_disable_free(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)804 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
805 struct pinctrl_gpio_range *range,
806 unsigned int offset)
807 {
808 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
809
810 byt_gpio_clear_triggering(vg, offset);
811 pm_runtime_put(&vg->pdev->dev);
812 }
813
byt_gpio_direct_irq_check(struct byt_gpio * vg,unsigned int offset)814 static void byt_gpio_direct_irq_check(struct byt_gpio *vg,
815 unsigned int offset)
816 {
817 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
818
819 /*
820 * Before making any direction modifications, do a check if gpio is set
821 * for direct IRQ. On Bay Trail, setting GPIO to output does not make
822 * sense, so let's at least inform the caller before they shoot
823 * themselves in the foot.
824 */
825 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
826 dev_info_once(&vg->pdev->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
827 }
828
byt_gpio_set_direction(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)829 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
830 struct pinctrl_gpio_range *range,
831 unsigned int offset,
832 bool input)
833 {
834 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
835 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
836 unsigned long flags;
837 u32 value;
838
839 raw_spin_lock_irqsave(&byt_lock, flags);
840
841 value = readl(val_reg);
842 value &= ~BYT_DIR_MASK;
843 if (input)
844 value |= BYT_OUTPUT_EN;
845 else
846 byt_gpio_direct_irq_check(vg, offset);
847
848 writel(value, val_reg);
849
850 raw_spin_unlock_irqrestore(&byt_lock, flags);
851
852 return 0;
853 }
854
855 static const struct pinmux_ops byt_pinmux_ops = {
856 .get_functions_count = byt_get_functions_count,
857 .get_function_name = byt_get_function_name,
858 .get_function_groups = byt_get_function_groups,
859 .set_mux = byt_set_mux,
860 .gpio_request_enable = byt_gpio_request_enable,
861 .gpio_disable_free = byt_gpio_disable_free,
862 .gpio_set_direction = byt_gpio_set_direction,
863 };
864
byt_get_pull_strength(u32 reg,u16 * strength)865 static void byt_get_pull_strength(u32 reg, u16 *strength)
866 {
867 switch (reg & BYT_PULL_STR_MASK) {
868 case BYT_PULL_STR_2K:
869 *strength = 2000;
870 break;
871 case BYT_PULL_STR_10K:
872 *strength = 10000;
873 break;
874 case BYT_PULL_STR_20K:
875 *strength = 20000;
876 break;
877 case BYT_PULL_STR_40K:
878 *strength = 40000;
879 break;
880 }
881 }
882
byt_set_pull_strength(u32 * reg,u16 strength)883 static int byt_set_pull_strength(u32 *reg, u16 strength)
884 {
885 *reg &= ~BYT_PULL_STR_MASK;
886
887 switch (strength) {
888 case 2000:
889 *reg |= BYT_PULL_STR_2K;
890 break;
891 case 10000:
892 *reg |= BYT_PULL_STR_10K;
893 break;
894 case 20000:
895 *reg |= BYT_PULL_STR_20K;
896 break;
897 case 40000:
898 *reg |= BYT_PULL_STR_40K;
899 break;
900 default:
901 return -EINVAL;
902 }
903
904 return 0;
905 }
906
byt_pin_config_get(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * config)907 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
908 unsigned long *config)
909 {
910 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
911 enum pin_config_param param = pinconf_to_config_param(*config);
912 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
913 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
914 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
915 unsigned long flags;
916 u32 conf, pull, val, debounce;
917 u16 arg = 0;
918
919 raw_spin_lock_irqsave(&byt_lock, flags);
920 conf = readl(conf_reg);
921 pull = conf & BYT_PULL_ASSIGN_MASK;
922 val = readl(val_reg);
923 raw_spin_unlock_irqrestore(&byt_lock, flags);
924
925 switch (param) {
926 case PIN_CONFIG_BIAS_DISABLE:
927 if (pull)
928 return -EINVAL;
929 break;
930 case PIN_CONFIG_BIAS_PULL_DOWN:
931 /* Pull assignment is only applicable in input mode */
932 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
933 return -EINVAL;
934
935 byt_get_pull_strength(conf, &arg);
936
937 break;
938 case PIN_CONFIG_BIAS_PULL_UP:
939 /* Pull assignment is only applicable in input mode */
940 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
941 return -EINVAL;
942
943 byt_get_pull_strength(conf, &arg);
944
945 break;
946 case PIN_CONFIG_INPUT_DEBOUNCE:
947 if (!(conf & BYT_DEBOUNCE_EN))
948 return -EINVAL;
949
950 raw_spin_lock_irqsave(&byt_lock, flags);
951 debounce = readl(db_reg);
952 raw_spin_unlock_irqrestore(&byt_lock, flags);
953
954 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
955 case BYT_DEBOUNCE_PULSE_375US:
956 arg = 375;
957 break;
958 case BYT_DEBOUNCE_PULSE_750US:
959 arg = 750;
960 break;
961 case BYT_DEBOUNCE_PULSE_1500US:
962 arg = 1500;
963 break;
964 case BYT_DEBOUNCE_PULSE_3MS:
965 arg = 3000;
966 break;
967 case BYT_DEBOUNCE_PULSE_6MS:
968 arg = 6000;
969 break;
970 case BYT_DEBOUNCE_PULSE_12MS:
971 arg = 12000;
972 break;
973 case BYT_DEBOUNCE_PULSE_24MS:
974 arg = 24000;
975 break;
976 default:
977 return -EINVAL;
978 }
979
980 break;
981 default:
982 return -ENOTSUPP;
983 }
984
985 *config = pinconf_to_config_packed(param, arg);
986
987 return 0;
988 }
989
byt_pin_config_set(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * configs,unsigned int num_configs)990 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
991 unsigned int offset,
992 unsigned long *configs,
993 unsigned int num_configs)
994 {
995 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
996 unsigned int param, arg;
997 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
998 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
999 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1000 unsigned long flags;
1001 u32 conf, val, debounce;
1002 int i, ret = 0;
1003
1004 raw_spin_lock_irqsave(&byt_lock, flags);
1005
1006 conf = readl(conf_reg);
1007 val = readl(val_reg);
1008
1009 for (i = 0; i < num_configs; i++) {
1010 param = pinconf_to_config_param(configs[i]);
1011 arg = pinconf_to_config_argument(configs[i]);
1012
1013 switch (param) {
1014 case PIN_CONFIG_BIAS_DISABLE:
1015 conf &= ~BYT_PULL_ASSIGN_MASK;
1016 break;
1017 case PIN_CONFIG_BIAS_PULL_DOWN:
1018 /* Set default strength value in case none is given */
1019 if (arg == 1)
1020 arg = 2000;
1021
1022 /*
1023 * Pull assignment is only applicable in input mode. If
1024 * chip is not in input mode, set it and warn about it.
1025 */
1026 if (val & BYT_INPUT_EN) {
1027 val &= ~BYT_INPUT_EN;
1028 writel(val, val_reg);
1029 dev_warn(&vg->pdev->dev,
1030 "pin %u forcibly set to input mode\n",
1031 offset);
1032 }
1033
1034 conf &= ~BYT_PULL_ASSIGN_MASK;
1035 conf |= BYT_PULL_ASSIGN_DOWN;
1036 ret = byt_set_pull_strength(&conf, arg);
1037
1038 break;
1039 case PIN_CONFIG_BIAS_PULL_UP:
1040 /* Set default strength value in case none is given */
1041 if (arg == 1)
1042 arg = 2000;
1043
1044 /*
1045 * Pull assignment is only applicable in input mode. If
1046 * chip is not in input mode, set it and warn about it.
1047 */
1048 if (val & BYT_INPUT_EN) {
1049 val &= ~BYT_INPUT_EN;
1050 writel(val, val_reg);
1051 dev_warn(&vg->pdev->dev,
1052 "pin %u forcibly set to input mode\n",
1053 offset);
1054 }
1055
1056 conf &= ~BYT_PULL_ASSIGN_MASK;
1057 conf |= BYT_PULL_ASSIGN_UP;
1058 ret = byt_set_pull_strength(&conf, arg);
1059
1060 break;
1061 case PIN_CONFIG_INPUT_DEBOUNCE:
1062 debounce = readl(db_reg);
1063
1064 if (arg)
1065 conf |= BYT_DEBOUNCE_EN;
1066 else
1067 conf &= ~BYT_DEBOUNCE_EN;
1068
1069 switch (arg) {
1070 case 375:
1071 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1072 debounce |= BYT_DEBOUNCE_PULSE_375US;
1073 break;
1074 case 750:
1075 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1076 debounce |= BYT_DEBOUNCE_PULSE_750US;
1077 break;
1078 case 1500:
1079 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1080 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1081 break;
1082 case 3000:
1083 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1084 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1085 break;
1086 case 6000:
1087 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1088 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1089 break;
1090 case 12000:
1091 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1092 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1093 break;
1094 case 24000:
1095 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1096 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1097 break;
1098 default:
1099 if (arg)
1100 ret = -EINVAL;
1101 break;
1102 }
1103
1104 if (!ret)
1105 writel(debounce, db_reg);
1106 break;
1107 default:
1108 ret = -ENOTSUPP;
1109 }
1110
1111 if (ret)
1112 break;
1113 }
1114
1115 if (!ret)
1116 writel(conf, conf_reg);
1117
1118 raw_spin_unlock_irqrestore(&byt_lock, flags);
1119
1120 return ret;
1121 }
1122
1123 static const struct pinconf_ops byt_pinconf_ops = {
1124 .is_generic = true,
1125 .pin_config_get = byt_pin_config_get,
1126 .pin_config_set = byt_pin_config_set,
1127 };
1128
1129 static const struct pinctrl_desc byt_pinctrl_desc = {
1130 .pctlops = &byt_pinctrl_ops,
1131 .pmxops = &byt_pinmux_ops,
1132 .confops = &byt_pinconf_ops,
1133 .owner = THIS_MODULE,
1134 };
1135
byt_gpio_get(struct gpio_chip * chip,unsigned int offset)1136 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1137 {
1138 struct byt_gpio *vg = gpiochip_get_data(chip);
1139 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1140 unsigned long flags;
1141 u32 val;
1142
1143 raw_spin_lock_irqsave(&byt_lock, flags);
1144 val = readl(reg);
1145 raw_spin_unlock_irqrestore(&byt_lock, flags);
1146
1147 return !!(val & BYT_LEVEL);
1148 }
1149
byt_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)1150 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1151 {
1152 struct byt_gpio *vg = gpiochip_get_data(chip);
1153 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1154 unsigned long flags;
1155 u32 old_val;
1156
1157 if (!reg)
1158 return;
1159
1160 raw_spin_lock_irqsave(&byt_lock, flags);
1161 old_val = readl(reg);
1162 if (value)
1163 writel(old_val | BYT_LEVEL, reg);
1164 else
1165 writel(old_val & ~BYT_LEVEL, reg);
1166 raw_spin_unlock_irqrestore(&byt_lock, flags);
1167 }
1168
byt_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1169 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1170 {
1171 struct byt_gpio *vg = gpiochip_get_data(chip);
1172 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1173 unsigned long flags;
1174 u32 value;
1175
1176 if (!reg)
1177 return -EINVAL;
1178
1179 raw_spin_lock_irqsave(&byt_lock, flags);
1180 value = readl(reg);
1181 raw_spin_unlock_irqrestore(&byt_lock, flags);
1182
1183 if (!(value & BYT_OUTPUT_EN))
1184 return 0;
1185 if (!(value & BYT_INPUT_EN))
1186 return 1;
1187
1188 return -EINVAL;
1189 }
1190
byt_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1191 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1192 {
1193 struct byt_gpio *vg = gpiochip_get_data(chip);
1194 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1195 unsigned long flags;
1196 u32 reg;
1197
1198 raw_spin_lock_irqsave(&byt_lock, flags);
1199
1200 reg = readl(val_reg);
1201 reg &= ~BYT_DIR_MASK;
1202 reg |= BYT_OUTPUT_EN;
1203 writel(reg, val_reg);
1204
1205 raw_spin_unlock_irqrestore(&byt_lock, flags);
1206 return 0;
1207 }
1208
1209 /*
1210 * Note despite the temptation this MUST NOT be converted into a call to
1211 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1212 * MUST be done as a single BYT_VAL_REG register write.
1213 * See the commit message of the commit adding this comment for details.
1214 */
byt_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1215 static int byt_gpio_direction_output(struct gpio_chip *chip,
1216 unsigned int offset, int value)
1217 {
1218 struct byt_gpio *vg = gpiochip_get_data(chip);
1219 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1220 unsigned long flags;
1221 u32 reg;
1222
1223 raw_spin_lock_irqsave(&byt_lock, flags);
1224
1225 byt_gpio_direct_irq_check(vg, offset);
1226
1227 reg = readl(val_reg);
1228 reg &= ~BYT_DIR_MASK;
1229 if (value)
1230 reg |= BYT_LEVEL;
1231 else
1232 reg &= ~BYT_LEVEL;
1233
1234 writel(reg, val_reg);
1235
1236 raw_spin_unlock_irqrestore(&byt_lock, flags);
1237 return 0;
1238 }
1239
byt_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)1240 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1241 {
1242 struct byt_gpio *vg = gpiochip_get_data(chip);
1243 int i;
1244 u32 conf0, val;
1245
1246 for (i = 0; i < vg->soc_data->npins; i++) {
1247 const struct intel_community *comm;
1248 const char *pull_str = NULL;
1249 const char *pull = NULL;
1250 void __iomem *reg;
1251 unsigned long flags;
1252 const char *label;
1253 unsigned int pin;
1254
1255 raw_spin_lock_irqsave(&byt_lock, flags);
1256 pin = vg->soc_data->pins[i].number;
1257 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1258 if (!reg) {
1259 seq_printf(s,
1260 "Could not retrieve pin %i conf0 reg\n",
1261 pin);
1262 raw_spin_unlock_irqrestore(&byt_lock, flags);
1263 continue;
1264 }
1265 conf0 = readl(reg);
1266
1267 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1268 if (!reg) {
1269 seq_printf(s,
1270 "Could not retrieve pin %i val reg\n", pin);
1271 raw_spin_unlock_irqrestore(&byt_lock, flags);
1272 continue;
1273 }
1274 val = readl(reg);
1275 raw_spin_unlock_irqrestore(&byt_lock, flags);
1276
1277 comm = byt_get_community(vg, pin);
1278 if (!comm) {
1279 seq_printf(s,
1280 "Could not get community for pin %i\n", pin);
1281 continue;
1282 }
1283 label = gpiochip_is_requested(chip, i);
1284 if (!label)
1285 label = "Unrequested";
1286
1287 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1288 case BYT_PULL_ASSIGN_UP:
1289 pull = "up";
1290 break;
1291 case BYT_PULL_ASSIGN_DOWN:
1292 pull = "down";
1293 break;
1294 }
1295
1296 switch (conf0 & BYT_PULL_STR_MASK) {
1297 case BYT_PULL_STR_2K:
1298 pull_str = "2k";
1299 break;
1300 case BYT_PULL_STR_10K:
1301 pull_str = "10k";
1302 break;
1303 case BYT_PULL_STR_20K:
1304 pull_str = "20k";
1305 break;
1306 case BYT_PULL_STR_40K:
1307 pull_str = "40k";
1308 break;
1309 }
1310
1311 seq_printf(s,
1312 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1313 pin,
1314 label,
1315 val & BYT_INPUT_EN ? " " : "in",
1316 val & BYT_OUTPUT_EN ? " " : "out",
1317 val & BYT_LEVEL ? "hi" : "lo",
1318 comm->pad_map[i], comm->pad_map[i] * 16,
1319 conf0 & 0x7,
1320 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1321 conf0 & BYT_TRIG_POS ? " rise" : " ",
1322 conf0 & BYT_TRIG_LVL ? " level" : " ");
1323
1324 if (pull && pull_str)
1325 seq_printf(s, " %-4s %-3s", pull, pull_str);
1326 else
1327 seq_puts(s, " ");
1328
1329 if (conf0 & BYT_IODEN)
1330 seq_puts(s, " open-drain");
1331
1332 seq_puts(s, "\n");
1333 }
1334 }
1335
1336 static const struct gpio_chip byt_gpio_chip = {
1337 .owner = THIS_MODULE,
1338 .request = gpiochip_generic_request,
1339 .free = gpiochip_generic_free,
1340 .get_direction = byt_gpio_get_direction,
1341 .direction_input = byt_gpio_direction_input,
1342 .direction_output = byt_gpio_direction_output,
1343 .get = byt_gpio_get,
1344 .set = byt_gpio_set,
1345 .set_config = gpiochip_generic_config,
1346 .dbg_show = byt_gpio_dbg_show,
1347 };
1348
byt_irq_ack(struct irq_data * d)1349 static void byt_irq_ack(struct irq_data *d)
1350 {
1351 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1352 struct byt_gpio *vg = gpiochip_get_data(gc);
1353 unsigned int offset = irqd_to_hwirq(d);
1354 void __iomem *reg;
1355
1356 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1357 if (!reg)
1358 return;
1359
1360 raw_spin_lock(&byt_lock);
1361 writel(BIT(offset % 32), reg);
1362 raw_spin_unlock(&byt_lock);
1363 }
1364
byt_irq_mask(struct irq_data * d)1365 static void byt_irq_mask(struct irq_data *d)
1366 {
1367 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1368 struct byt_gpio *vg = gpiochip_get_data(gc);
1369
1370 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1371 }
1372
byt_irq_unmask(struct irq_data * d)1373 static void byt_irq_unmask(struct irq_data *d)
1374 {
1375 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1376 struct byt_gpio *vg = gpiochip_get_data(gc);
1377 unsigned int offset = irqd_to_hwirq(d);
1378 unsigned long flags;
1379 void __iomem *reg;
1380 u32 value;
1381
1382 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1383 if (!reg)
1384 return;
1385
1386 raw_spin_lock_irqsave(&byt_lock, flags);
1387 value = readl(reg);
1388
1389 switch (irqd_get_trigger_type(d)) {
1390 case IRQ_TYPE_LEVEL_HIGH:
1391 value |= BYT_TRIG_LVL;
1392 /* fall through */
1393 case IRQ_TYPE_EDGE_RISING:
1394 value |= BYT_TRIG_POS;
1395 break;
1396 case IRQ_TYPE_LEVEL_LOW:
1397 value |= BYT_TRIG_LVL;
1398 /* fall through */
1399 case IRQ_TYPE_EDGE_FALLING:
1400 value |= BYT_TRIG_NEG;
1401 break;
1402 case IRQ_TYPE_EDGE_BOTH:
1403 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1404 break;
1405 }
1406
1407 writel(value, reg);
1408
1409 raw_spin_unlock_irqrestore(&byt_lock, flags);
1410 }
1411
byt_irq_type(struct irq_data * d,unsigned int type)1412 static int byt_irq_type(struct irq_data *d, unsigned int type)
1413 {
1414 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1415 u32 offset = irqd_to_hwirq(d);
1416 u32 value;
1417 unsigned long flags;
1418 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1419
1420 if (!reg || offset >= vg->chip.ngpio)
1421 return -EINVAL;
1422
1423 raw_spin_lock_irqsave(&byt_lock, flags);
1424 value = readl(reg);
1425
1426 WARN(value & BYT_DIRECT_IRQ_EN,
1427 "Bad pad config for io mode, force direct_irq_en bit clearing");
1428
1429 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1430 * are used to indicate high and low level triggering
1431 */
1432 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1433 BYT_TRIG_LVL);
1434 /* Enable glitch filtering */
1435 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1436 BYT_GLITCH_F_FAST_CLK;
1437
1438 writel(value, reg);
1439
1440 if (type & IRQ_TYPE_EDGE_BOTH)
1441 irq_set_handler_locked(d, handle_edge_irq);
1442 else if (type & IRQ_TYPE_LEVEL_MASK)
1443 irq_set_handler_locked(d, handle_level_irq);
1444
1445 raw_spin_unlock_irqrestore(&byt_lock, flags);
1446
1447 return 0;
1448 }
1449
1450 static struct irq_chip byt_irqchip = {
1451 .name = "BYT-GPIO",
1452 .irq_ack = byt_irq_ack,
1453 .irq_mask = byt_irq_mask,
1454 .irq_unmask = byt_irq_unmask,
1455 .irq_set_type = byt_irq_type,
1456 .flags = IRQCHIP_SKIP_SET_WAKE,
1457 };
1458
byt_gpio_irq_handler(struct irq_desc * desc)1459 static void byt_gpio_irq_handler(struct irq_desc *desc)
1460 {
1461 struct irq_data *data = irq_desc_get_irq_data(desc);
1462 struct byt_gpio *vg = gpiochip_get_data(
1463 irq_desc_get_handler_data(desc));
1464 struct irq_chip *chip = irq_data_get_irq_chip(data);
1465 u32 base, pin;
1466 void __iomem *reg;
1467 unsigned long pending;
1468 unsigned int virq;
1469
1470 /* check from GPIO controller which pin triggered the interrupt */
1471 for (base = 0; base < vg->chip.ngpio; base += 32) {
1472 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1473
1474 if (!reg) {
1475 dev_warn(&vg->pdev->dev,
1476 "Pin %i: could not retrieve interrupt status register\n",
1477 base);
1478 continue;
1479 }
1480
1481 raw_spin_lock(&byt_lock);
1482 pending = readl(reg);
1483 raw_spin_unlock(&byt_lock);
1484 for_each_set_bit(pin, &pending, 32) {
1485 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1486 generic_handle_irq(virq);
1487 }
1488 }
1489 chip->irq_eoi(data);
1490 }
1491
byt_init_irq_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1492 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1493 unsigned long *valid_mask,
1494 unsigned int ngpios)
1495 {
1496 /*
1497 * FIXME: currently the valid_mask is filled in as part of
1498 * initializing the irq_chip below in byt_gpio_irq_init_hw().
1499 * when converting this driver to the new way of passing the
1500 * gpio_irq_chip along when adding the gpio_chip, move the
1501 * mask initialization into this callback instead. Right now
1502 * this callback is here to make sure the mask gets allocated.
1503 */
1504 }
1505
byt_gpio_irq_init_hw(struct byt_gpio * vg)1506 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1507 {
1508 struct gpio_chip *gc = &vg->chip;
1509 struct device *dev = &vg->pdev->dev;
1510 void __iomem *reg;
1511 u32 base, value;
1512 int i;
1513
1514 /*
1515 * Clear interrupt triggers for all pins that are GPIOs and
1516 * do not use direct IRQ mode. This will prevent spurious
1517 * interrupts from misconfigured pins.
1518 */
1519 for (i = 0; i < vg->soc_data->npins; i++) {
1520 unsigned int pin = vg->soc_data->pins[i].number;
1521
1522 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1523 if (!reg) {
1524 dev_warn(&vg->pdev->dev,
1525 "Pin %i: could not retrieve conf0 register\n",
1526 i);
1527 continue;
1528 }
1529
1530 value = readl(reg);
1531 if (value & BYT_DIRECT_IRQ_EN) {
1532 clear_bit(i, gc->irq.valid_mask);
1533 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1534 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1535 byt_gpio_clear_triggering(vg, i);
1536 dev_dbg(dev, "disabling GPIO %d\n", i);
1537 }
1538 }
1539
1540 /* clear interrupt status trigger registers */
1541 for (base = 0; base < vg->soc_data->npins; base += 32) {
1542 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1543
1544 if (!reg) {
1545 dev_warn(&vg->pdev->dev,
1546 "Pin %i: could not retrieve irq status reg\n",
1547 base);
1548 continue;
1549 }
1550
1551 writel(0xffffffff, reg);
1552 /* make sure trigger bits are cleared, if not then a pin
1553 might be misconfigured in bios */
1554 value = readl(reg);
1555 if (value)
1556 dev_err(&vg->pdev->dev,
1557 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1558 base / 32, value);
1559 }
1560 }
1561
byt_gpio_probe(struct byt_gpio * vg)1562 static int byt_gpio_probe(struct byt_gpio *vg)
1563 {
1564 struct gpio_chip *gc;
1565 struct resource *irq_rc;
1566 int ret;
1567
1568 /* Set up gpio chip */
1569 vg->chip = byt_gpio_chip;
1570 gc = &vg->chip;
1571 gc->label = dev_name(&vg->pdev->dev);
1572 gc->base = -1;
1573 gc->can_sleep = false;
1574 gc->parent = &vg->pdev->dev;
1575 gc->ngpio = vg->soc_data->npins;
1576 gc->irq.init_valid_mask = byt_init_irq_valid_mask;
1577
1578 #ifdef CONFIG_PM_SLEEP
1579 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1580 sizeof(*vg->saved_context), GFP_KERNEL);
1581 if (!vg->saved_context)
1582 return -ENOMEM;
1583 #endif
1584 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1585 if (ret) {
1586 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1587 return ret;
1588 }
1589
1590 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1591 0, 0, vg->soc_data->npins);
1592 if (ret) {
1593 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1594 return ret;
1595 }
1596
1597 /* set up interrupts */
1598 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1599 if (irq_rc && irq_rc->start) {
1600 byt_gpio_irq_init_hw(vg);
1601 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1602 handle_bad_irq, IRQ_TYPE_NONE);
1603 if (ret) {
1604 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1605 return ret;
1606 }
1607
1608 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1609 (unsigned)irq_rc->start,
1610 byt_gpio_irq_handler);
1611 }
1612
1613 return ret;
1614 }
1615
byt_set_soc_data(struct byt_gpio * vg,const struct intel_pinctrl_soc_data * soc_data)1616 static int byt_set_soc_data(struct byt_gpio *vg,
1617 const struct intel_pinctrl_soc_data *soc_data)
1618 {
1619 int i;
1620
1621 vg->soc_data = soc_data;
1622 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1623 soc_data->ncommunities,
1624 sizeof(*vg->communities_copy),
1625 GFP_KERNEL);
1626 if (!vg->communities_copy)
1627 return -ENOMEM;
1628
1629 for (i = 0; i < soc_data->ncommunities; i++) {
1630 struct intel_community *comm = vg->communities_copy + i;
1631
1632 *comm = vg->soc_data->communities[i];
1633
1634 comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0);
1635 if (IS_ERR(comm->pad_regs))
1636 return PTR_ERR(comm->pad_regs);
1637 }
1638
1639 return 0;
1640 }
1641
1642 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1643 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1644 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1645 { }
1646 };
1647
byt_pinctrl_probe(struct platform_device * pdev)1648 static int byt_pinctrl_probe(struct platform_device *pdev)
1649 {
1650 const struct intel_pinctrl_soc_data *soc_data = NULL;
1651 const struct intel_pinctrl_soc_data **soc_table;
1652 struct acpi_device *acpi_dev;
1653 struct byt_gpio *vg;
1654 int i, ret;
1655
1656 acpi_dev = ACPI_COMPANION(&pdev->dev);
1657 if (!acpi_dev)
1658 return -ENODEV;
1659
1660 soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
1661
1662 for (i = 0; soc_table[i]; i++) {
1663 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1664 soc_data = soc_table[i];
1665 break;
1666 }
1667 }
1668
1669 if (!soc_data)
1670 return -ENODEV;
1671
1672 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1673 if (!vg)
1674 return -ENOMEM;
1675
1676 vg->pdev = pdev;
1677 ret = byt_set_soc_data(vg, soc_data);
1678 if (ret) {
1679 dev_err(&pdev->dev, "failed to set soc data\n");
1680 return ret;
1681 }
1682
1683 vg->pctl_desc = byt_pinctrl_desc;
1684 vg->pctl_desc.name = dev_name(&pdev->dev);
1685 vg->pctl_desc.pins = vg->soc_data->pins;
1686 vg->pctl_desc.npins = vg->soc_data->npins;
1687
1688 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
1689 if (IS_ERR(vg->pctl_dev)) {
1690 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1691 return PTR_ERR(vg->pctl_dev);
1692 }
1693
1694 ret = byt_gpio_probe(vg);
1695 if (ret)
1696 return ret;
1697
1698 platform_set_drvdata(pdev, vg);
1699 pm_runtime_enable(&pdev->dev);
1700
1701 return 0;
1702 }
1703
1704 #ifdef CONFIG_PM_SLEEP
byt_gpio_suspend(struct device * dev)1705 static int byt_gpio_suspend(struct device *dev)
1706 {
1707 struct byt_gpio *vg = dev_get_drvdata(dev);
1708 unsigned long flags;
1709 int i;
1710
1711 raw_spin_lock_irqsave(&byt_lock, flags);
1712
1713 for (i = 0; i < vg->soc_data->npins; i++) {
1714 void __iomem *reg;
1715 u32 value;
1716 unsigned int pin = vg->soc_data->pins[i].number;
1717
1718 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1719 if (!reg) {
1720 dev_warn(&vg->pdev->dev,
1721 "Pin %i: could not retrieve conf0 register\n",
1722 i);
1723 continue;
1724 }
1725 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1726 vg->saved_context[i].conf0 = value;
1727
1728 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1729 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1730 vg->saved_context[i].val = value;
1731 }
1732
1733 raw_spin_unlock_irqrestore(&byt_lock, flags);
1734 return 0;
1735 }
1736
byt_gpio_resume(struct device * dev)1737 static int byt_gpio_resume(struct device *dev)
1738 {
1739 struct byt_gpio *vg = dev_get_drvdata(dev);
1740 unsigned long flags;
1741 int i;
1742
1743 raw_spin_lock_irqsave(&byt_lock, flags);
1744
1745 for (i = 0; i < vg->soc_data->npins; i++) {
1746 void __iomem *reg;
1747 u32 value;
1748 unsigned int pin = vg->soc_data->pins[i].number;
1749
1750 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1751 if (!reg) {
1752 dev_warn(&vg->pdev->dev,
1753 "Pin %i: could not retrieve conf0 register\n",
1754 i);
1755 continue;
1756 }
1757 value = readl(reg);
1758 if ((value & BYT_CONF0_RESTORE_MASK) !=
1759 vg->saved_context[i].conf0) {
1760 value &= ~BYT_CONF0_RESTORE_MASK;
1761 value |= vg->saved_context[i].conf0;
1762 writel(value, reg);
1763 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1764 }
1765
1766 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1767 value = readl(reg);
1768 if ((value & BYT_VAL_RESTORE_MASK) !=
1769 vg->saved_context[i].val) {
1770 u32 v;
1771
1772 v = value & ~BYT_VAL_RESTORE_MASK;
1773 v |= vg->saved_context[i].val;
1774 if (v != value) {
1775 writel(v, reg);
1776 dev_dbg(dev, "restored pin %d val %#08x\n",
1777 i, v);
1778 }
1779 }
1780 }
1781
1782 raw_spin_unlock_irqrestore(&byt_lock, flags);
1783 return 0;
1784 }
1785 #endif
1786
1787 #ifdef CONFIG_PM
byt_gpio_runtime_suspend(struct device * dev)1788 static int byt_gpio_runtime_suspend(struct device *dev)
1789 {
1790 return 0;
1791 }
1792
byt_gpio_runtime_resume(struct device * dev)1793 static int byt_gpio_runtime_resume(struct device *dev)
1794 {
1795 return 0;
1796 }
1797 #endif
1798
1799 static const struct dev_pm_ops byt_gpio_pm_ops = {
1800 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1801 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1802 NULL)
1803 };
1804
1805 static struct platform_driver byt_gpio_driver = {
1806 .probe = byt_pinctrl_probe,
1807 .driver = {
1808 .name = "byt_gpio",
1809 .pm = &byt_gpio_pm_ops,
1810 .suppress_bind_attrs = true,
1811
1812 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1813 },
1814 };
1815
byt_gpio_init(void)1816 static int __init byt_gpio_init(void)
1817 {
1818 return platform_driver_register(&byt_gpio_driver);
1819 }
1820 subsys_initcall(byt_gpio_init);
1821