1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Cherryview/Braswell pinctrl driver
4 *
5 * Copyright (C) 2014, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This driver is based on the original Cherryview GPIO driver by
9 * Ning Li <ning.li@intel.com>
10 * Alan Cox <alan@linux.intel.com>
11 */
12
13 #include <linux/acpi.h>
14 #include <linux/dmi.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/types.h>
20
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25
26 #include "pinctrl-intel.h"
27
28 #define CHV_INTSTAT 0x300
29 #define CHV_INTMASK 0x380
30
31 #define FAMILY_PAD_REGS_OFF 0x4400
32 #define FAMILY_PAD_REGS_SIZE 0x400
33 #define MAX_FAMILY_PAD_GPIO_NO 15
34 #define GPIO_REGS_SIZE 8
35
36 #define CHV_PADCTRL0 0x000
37 #define CHV_PADCTRL0_INTSEL_SHIFT 28
38 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
39 #define CHV_PADCTRL0_TERM_UP BIT(23)
40 #define CHV_PADCTRL0_TERM_SHIFT 20
41 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
42 #define CHV_PADCTRL0_TERM_20K 1
43 #define CHV_PADCTRL0_TERM_5K 2
44 #define CHV_PADCTRL0_TERM_1K 4
45 #define CHV_PADCTRL0_PMODE_SHIFT 16
46 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
47 #define CHV_PADCTRL0_GPIOEN BIT(15)
48 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
49 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
50 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
51 #define CHV_PADCTRL0_GPIOCFG_GPO 1
52 #define CHV_PADCTRL0_GPIOCFG_GPI 2
53 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
54 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
55 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
56
57 #define CHV_PADCTRL1 0x004
58 #define CHV_PADCTRL1_CFGLOCK BIT(31)
59 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
60 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
61 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
62 #define CHV_PADCTRL1_ODEN BIT(3)
63 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
64 #define CHV_PADCTRL1_INTWAKECFG_MASK 7
65 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
66 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
67 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
68 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
69
70 /**
71 * struct chv_alternate_function - A per group or per pin alternate function
72 * @pin: Pin number (only used in per pin configs)
73 * @mode: Mode the pin should be set in
74 * @invert_oe: Invert OE for this pin
75 */
76 struct chv_alternate_function {
77 unsigned int pin;
78 u8 mode;
79 bool invert_oe;
80 };
81
82 /**
83 * struct chv_pincgroup - describes a CHV pin group
84 * @name: Name of the group
85 * @pins: An array of pins in this group
86 * @npins: Number of pins in this group
87 * @altfunc: Alternate function applied to all pins in this group
88 * @overrides: Alternate function override per pin or %NULL if not used
89 * @noverrides: Number of per pin alternate function overrides if
90 * @overrides != NULL.
91 */
92 struct chv_pingroup {
93 const char *name;
94 const unsigned int *pins;
95 size_t npins;
96 struct chv_alternate_function altfunc;
97 const struct chv_alternate_function *overrides;
98 size_t noverrides;
99 };
100
101 /**
102 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
103 * @base: Start pin number
104 * @npins: Number of pins in this range
105 */
106 struct chv_gpio_pinrange {
107 unsigned int base;
108 unsigned int npins;
109 };
110
111 /**
112 * struct chv_community - A community specific configuration
113 * @uid: ACPI _UID used to match the community
114 * @pins: All pins in this community
115 * @npins: Number of pins
116 * @groups: All groups in this community
117 * @ngroups: Number of groups
118 * @functions: All functions in this community
119 * @nfunctions: Number of functions
120 * @gpio_ranges: An array of GPIO ranges in this community
121 * @ngpio_ranges: Number of GPIO ranges
122 * @nirqs: Total number of IRQs this community can generate
123 * @acpi_space_id: An address space ID for ACPI OpRegion handler
124 */
125 struct chv_community {
126 const char *uid;
127 const struct pinctrl_pin_desc *pins;
128 size_t npins;
129 const struct chv_pingroup *groups;
130 size_t ngroups;
131 const struct intel_function *functions;
132 size_t nfunctions;
133 const struct chv_gpio_pinrange *gpio_ranges;
134 size_t ngpio_ranges;
135 size_t nirqs;
136 acpi_adr_space_type acpi_space_id;
137 };
138
139 struct chv_pin_context {
140 u32 padctrl0;
141 u32 padctrl1;
142 };
143
144 /**
145 * struct chv_pinctrl - CHV pinctrl private structure
146 * @dev: Pointer to the parent device
147 * @pctldesc: Pin controller description
148 * @pctldev: Pointer to the pin controller device
149 * @chip: GPIO chip in this pin controller
150 * @irqchip: IRQ chip in this pin controller
151 * @regs: MMIO registers
152 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
153 * offset (in GPIO number space)
154 * @community: Community this pinctrl instance represents
155 * @saved_intmask: Interrupt mask saved for system sleep
156 * @saved_pin_context: Pointer to a context of the pins saved for system sleep
157 *
158 * The first group in @groups is expected to contain all pins that can be
159 * used as GPIOs.
160 */
161 struct chv_pinctrl {
162 struct device *dev;
163 struct pinctrl_desc pctldesc;
164 struct pinctrl_dev *pctldev;
165 struct gpio_chip chip;
166 struct irq_chip irqchip;
167 void __iomem *regs;
168 unsigned intr_lines[16];
169 const struct chv_community *community;
170 u32 saved_intmask;
171 struct chv_pin_context *saved_pin_context;
172 };
173
174 #define ALTERNATE_FUNCTION(p, m, i) \
175 { \
176 .pin = (p), \
177 .mode = (m), \
178 .invert_oe = (i), \
179 }
180
181 #define PIN_GROUP_WITH_ALT(n, p, m, i) \
182 { \
183 .name = (n), \
184 .pins = (p), \
185 .npins = ARRAY_SIZE((p)), \
186 .altfunc.mode = (m), \
187 .altfunc.invert_oe = (i), \
188 }
189
190 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
191 { \
192 .name = (n), \
193 .pins = (p), \
194 .npins = ARRAY_SIZE((p)), \
195 .altfunc.mode = (m), \
196 .altfunc.invert_oe = (i), \
197 .overrides = (o), \
198 .noverrides = ARRAY_SIZE((o)), \
199 }
200
201 #define GPIO_PINRANGE(start, end) \
202 { \
203 .base = (start), \
204 .npins = (end) - (start) + 1, \
205 }
206
207 static const struct pinctrl_pin_desc southwest_pins[] = {
208 PINCTRL_PIN(0, "FST_SPI_D2"),
209 PINCTRL_PIN(1, "FST_SPI_D0"),
210 PINCTRL_PIN(2, "FST_SPI_CLK"),
211 PINCTRL_PIN(3, "FST_SPI_D3"),
212 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
213 PINCTRL_PIN(5, "FST_SPI_D1"),
214 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
215 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
216
217 PINCTRL_PIN(15, "UART1_RTS_B"),
218 PINCTRL_PIN(16, "UART1_RXD"),
219 PINCTRL_PIN(17, "UART2_RXD"),
220 PINCTRL_PIN(18, "UART1_CTS_B"),
221 PINCTRL_PIN(19, "UART2_RTS_B"),
222 PINCTRL_PIN(20, "UART1_TXD"),
223 PINCTRL_PIN(21, "UART2_TXD"),
224 PINCTRL_PIN(22, "UART2_CTS_B"),
225
226 PINCTRL_PIN(30, "MF_HDA_CLK"),
227 PINCTRL_PIN(31, "MF_HDA_RSTB"),
228 PINCTRL_PIN(32, "MF_HDA_SDIO"),
229 PINCTRL_PIN(33, "MF_HDA_SDO"),
230 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
231 PINCTRL_PIN(35, "MF_HDA_SYNC"),
232 PINCTRL_PIN(36, "MF_HDA_SDI1"),
233 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
234
235 PINCTRL_PIN(45, "I2C5_SDA"),
236 PINCTRL_PIN(46, "I2C4_SDA"),
237 PINCTRL_PIN(47, "I2C6_SDA"),
238 PINCTRL_PIN(48, "I2C5_SCL"),
239 PINCTRL_PIN(49, "I2C_NFC_SDA"),
240 PINCTRL_PIN(50, "I2C4_SCL"),
241 PINCTRL_PIN(51, "I2C6_SCL"),
242 PINCTRL_PIN(52, "I2C_NFC_SCL"),
243
244 PINCTRL_PIN(60, "I2C1_SDA"),
245 PINCTRL_PIN(61, "I2C0_SDA"),
246 PINCTRL_PIN(62, "I2C2_SDA"),
247 PINCTRL_PIN(63, "I2C1_SCL"),
248 PINCTRL_PIN(64, "I2C3_SDA"),
249 PINCTRL_PIN(65, "I2C0_SCL"),
250 PINCTRL_PIN(66, "I2C2_SCL"),
251 PINCTRL_PIN(67, "I2C3_SCL"),
252
253 PINCTRL_PIN(75, "SATA_GP0"),
254 PINCTRL_PIN(76, "SATA_GP1"),
255 PINCTRL_PIN(77, "SATA_LEDN"),
256 PINCTRL_PIN(78, "SATA_GP2"),
257 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
258 PINCTRL_PIN(80, "SATA_GP3"),
259 PINCTRL_PIN(81, "MF_SMB_CLK"),
260 PINCTRL_PIN(82, "MF_SMB_DATA"),
261
262 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
263 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
264 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
265 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
266 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
267 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
268 PINCTRL_PIN(96, "GP_SSP_2_FS"),
269 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
270 };
271
272 static const unsigned southwest_uart0_pins[] = { 16, 20 };
273 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
274 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
275 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
276 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
277 static const unsigned southwest_lpe_pins[] = {
278 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
279 };
280 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
281 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
282 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
283 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
284 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
285 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
286 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
287 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
288
289 /* LPE I2S TXD pins need to have invert_oe set */
290 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
291 ALTERNATE_FUNCTION(30, 1, true),
292 ALTERNATE_FUNCTION(34, 1, true),
293 ALTERNATE_FUNCTION(97, 1, true),
294 };
295
296 /*
297 * Two spi3 chipselects are available in different mode than the main spi3
298 * functionality, which is using mode 1.
299 */
300 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
301 ALTERNATE_FUNCTION(76, 3, false),
302 ALTERNATE_FUNCTION(80, 3, false),
303 };
304
305 static const struct chv_pingroup southwest_groups[] = {
306 PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false),
307 PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false),
308 PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false),
309 PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false),
310 PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true),
311 PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true),
312 PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true),
313 PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true),
314 PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true),
315 PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true),
316 PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true),
317 PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
318
319 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
320 southwest_lpe_altfuncs),
321 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
322 southwest_spi3_altfuncs),
323 };
324
325 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
326 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
327 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
328 static const char * const southwest_hda_groups[] = { "hda_grp" };
329 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
330 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
331 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
332 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
333 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
334 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
335 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
336 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
337 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
338 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
339
340 /*
341 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
342 * enabled only as GPIOs.
343 */
344 static const struct intel_function southwest_functions[] = {
345 FUNCTION("uart0", southwest_uart0_groups),
346 FUNCTION("uart1", southwest_uart1_groups),
347 FUNCTION("uart2", southwest_uart2_groups),
348 FUNCTION("hda", southwest_hda_groups),
349 FUNCTION("lpe", southwest_lpe_groups),
350 FUNCTION("i2c0", southwest_i2c0_groups),
351 FUNCTION("i2c1", southwest_i2c1_groups),
352 FUNCTION("i2c2", southwest_i2c2_groups),
353 FUNCTION("i2c3", southwest_i2c3_groups),
354 FUNCTION("i2c4", southwest_i2c4_groups),
355 FUNCTION("i2c5", southwest_i2c5_groups),
356 FUNCTION("i2c6", southwest_i2c6_groups),
357 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
358 FUNCTION("spi3", southwest_spi3_groups),
359 };
360
361 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
362 GPIO_PINRANGE(0, 7),
363 GPIO_PINRANGE(15, 22),
364 GPIO_PINRANGE(30, 37),
365 GPIO_PINRANGE(45, 52),
366 GPIO_PINRANGE(60, 67),
367 GPIO_PINRANGE(75, 82),
368 GPIO_PINRANGE(90, 97),
369 };
370
371 static const struct chv_community southwest_community = {
372 .uid = "1",
373 .pins = southwest_pins,
374 .npins = ARRAY_SIZE(southwest_pins),
375 .groups = southwest_groups,
376 .ngroups = ARRAY_SIZE(southwest_groups),
377 .functions = southwest_functions,
378 .nfunctions = ARRAY_SIZE(southwest_functions),
379 .gpio_ranges = southwest_gpio_ranges,
380 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
381 /*
382 * Southwest community can benerate GPIO interrupts only for the
383 * first 8 interrupts. The upper half (8-15) can only be used to
384 * trigger GPEs.
385 */
386 .nirqs = 8,
387 .acpi_space_id = 0x91,
388 };
389
390 static const struct pinctrl_pin_desc north_pins[] = {
391 PINCTRL_PIN(0, "GPIO_DFX_0"),
392 PINCTRL_PIN(1, "GPIO_DFX_3"),
393 PINCTRL_PIN(2, "GPIO_DFX_7"),
394 PINCTRL_PIN(3, "GPIO_DFX_1"),
395 PINCTRL_PIN(4, "GPIO_DFX_5"),
396 PINCTRL_PIN(5, "GPIO_DFX_4"),
397 PINCTRL_PIN(6, "GPIO_DFX_8"),
398 PINCTRL_PIN(7, "GPIO_DFX_2"),
399 PINCTRL_PIN(8, "GPIO_DFX_6"),
400
401 PINCTRL_PIN(15, "GPIO_SUS0"),
402 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
403 PINCTRL_PIN(17, "GPIO_SUS3"),
404 PINCTRL_PIN(18, "GPIO_SUS7"),
405 PINCTRL_PIN(19, "GPIO_SUS1"),
406 PINCTRL_PIN(20, "GPIO_SUS5"),
407 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
408 PINCTRL_PIN(22, "GPIO_SUS4"),
409 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
410 PINCTRL_PIN(24, "GPIO_SUS2"),
411 PINCTRL_PIN(25, "GPIO_SUS6"),
412 PINCTRL_PIN(26, "CX_PREQ_B"),
413 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
414
415 PINCTRL_PIN(30, "TRST_B"),
416 PINCTRL_PIN(31, "TCK"),
417 PINCTRL_PIN(32, "PROCHOT_B"),
418 PINCTRL_PIN(33, "SVIDO_DATA"),
419 PINCTRL_PIN(34, "TMS"),
420 PINCTRL_PIN(35, "CX_PRDY_B_2"),
421 PINCTRL_PIN(36, "TDO_2"),
422 PINCTRL_PIN(37, "CX_PRDY_B"),
423 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
424 PINCTRL_PIN(39, "TDO"),
425 PINCTRL_PIN(40, "SVIDO_CLK"),
426 PINCTRL_PIN(41, "TDI"),
427
428 PINCTRL_PIN(45, "GP_CAMERASB_05"),
429 PINCTRL_PIN(46, "GP_CAMERASB_02"),
430 PINCTRL_PIN(47, "GP_CAMERASB_08"),
431 PINCTRL_PIN(48, "GP_CAMERASB_00"),
432 PINCTRL_PIN(49, "GP_CAMERASB_06"),
433 PINCTRL_PIN(50, "GP_CAMERASB_10"),
434 PINCTRL_PIN(51, "GP_CAMERASB_03"),
435 PINCTRL_PIN(52, "GP_CAMERASB_09"),
436 PINCTRL_PIN(53, "GP_CAMERASB_01"),
437 PINCTRL_PIN(54, "GP_CAMERASB_07"),
438 PINCTRL_PIN(55, "GP_CAMERASB_11"),
439 PINCTRL_PIN(56, "GP_CAMERASB_04"),
440
441 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
442 PINCTRL_PIN(61, "HV_DDI0_HPD"),
443 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
444 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
445 PINCTRL_PIN(64, "HV_DDI1_HPD"),
446 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
447 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
448 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
449 PINCTRL_PIN(68, "HV_DDI2_HPD"),
450 PINCTRL_PIN(69, "PANEL1_VDDEN"),
451 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
452 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
453 PINCTRL_PIN(72, "PANEL0_VDDEN"),
454 };
455
456 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
457 GPIO_PINRANGE(0, 8),
458 GPIO_PINRANGE(15, 27),
459 GPIO_PINRANGE(30, 41),
460 GPIO_PINRANGE(45, 56),
461 GPIO_PINRANGE(60, 72),
462 };
463
464 static const struct chv_community north_community = {
465 .uid = "2",
466 .pins = north_pins,
467 .npins = ARRAY_SIZE(north_pins),
468 .gpio_ranges = north_gpio_ranges,
469 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
470 /*
471 * North community can generate GPIO interrupts only for the first
472 * 8 interrupts. The upper half (8-15) can only be used to trigger
473 * GPEs.
474 */
475 .nirqs = 8,
476 .acpi_space_id = 0x92,
477 };
478
479 static const struct pinctrl_pin_desc east_pins[] = {
480 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
481 PINCTRL_PIN(1, "PMU_BATLOW_B"),
482 PINCTRL_PIN(2, "SUS_STAT_B"),
483 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
484 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
485 PINCTRL_PIN(5, "PMU_PLTRST_B"),
486 PINCTRL_PIN(6, "PMU_SUSCLK"),
487 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
488 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
489 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
490 PINCTRL_PIN(10, "PMU_WAKE_B"),
491 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
492
493 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
494 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
495 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
496 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
497 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
498 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
499 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
500 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
501 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
502 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
503 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
504 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
505 };
506
507 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
508 GPIO_PINRANGE(0, 11),
509 GPIO_PINRANGE(15, 26),
510 };
511
512 static const struct chv_community east_community = {
513 .uid = "3",
514 .pins = east_pins,
515 .npins = ARRAY_SIZE(east_pins),
516 .gpio_ranges = east_gpio_ranges,
517 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
518 .nirqs = 16,
519 .acpi_space_id = 0x93,
520 };
521
522 static const struct pinctrl_pin_desc southeast_pins[] = {
523 PINCTRL_PIN(0, "MF_PLT_CLK0"),
524 PINCTRL_PIN(1, "PWM1"),
525 PINCTRL_PIN(2, "MF_PLT_CLK1"),
526 PINCTRL_PIN(3, "MF_PLT_CLK4"),
527 PINCTRL_PIN(4, "MF_PLT_CLK3"),
528 PINCTRL_PIN(5, "PWM0"),
529 PINCTRL_PIN(6, "MF_PLT_CLK5"),
530 PINCTRL_PIN(7, "MF_PLT_CLK2"),
531
532 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
533 PINCTRL_PIN(16, "SDMMC1_CLK"),
534 PINCTRL_PIN(17, "SDMMC1_D0"),
535 PINCTRL_PIN(18, "SDMMC2_D1"),
536 PINCTRL_PIN(19, "SDMMC2_CLK"),
537 PINCTRL_PIN(20, "SDMMC1_D2"),
538 PINCTRL_PIN(21, "SDMMC2_D2"),
539 PINCTRL_PIN(22, "SDMMC2_CMD"),
540 PINCTRL_PIN(23, "SDMMC1_CMD"),
541 PINCTRL_PIN(24, "SDMMC1_D1"),
542 PINCTRL_PIN(25, "SDMMC2_D0"),
543 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
544
545 PINCTRL_PIN(30, "SDMMC3_D1"),
546 PINCTRL_PIN(31, "SDMMC3_CLK"),
547 PINCTRL_PIN(32, "SDMMC3_D3"),
548 PINCTRL_PIN(33, "SDMMC3_D2"),
549 PINCTRL_PIN(34, "SDMMC3_CMD"),
550 PINCTRL_PIN(35, "SDMMC3_D0"),
551
552 PINCTRL_PIN(45, "MF_LPC_AD2"),
553 PINCTRL_PIN(46, "LPC_CLKRUNB"),
554 PINCTRL_PIN(47, "MF_LPC_AD0"),
555 PINCTRL_PIN(48, "LPC_FRAMEB"),
556 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
557 PINCTRL_PIN(50, "MF_LPC_AD3"),
558 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
559 PINCTRL_PIN(52, "MF_LPC_AD1"),
560
561 PINCTRL_PIN(60, "SPI1_MISO"),
562 PINCTRL_PIN(61, "SPI1_CSO_B"),
563 PINCTRL_PIN(62, "SPI1_CLK"),
564 PINCTRL_PIN(63, "MMC1_D6"),
565 PINCTRL_PIN(64, "SPI1_MOSI"),
566 PINCTRL_PIN(65, "MMC1_D5"),
567 PINCTRL_PIN(66, "SPI1_CS1_B"),
568 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
569 PINCTRL_PIN(68, "MMC1_D7"),
570 PINCTRL_PIN(69, "MMC1_RCLK"),
571
572 PINCTRL_PIN(75, "USB_OC1_B"),
573 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
574 PINCTRL_PIN(77, "GPIO_ALERT"),
575 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
576 PINCTRL_PIN(79, "ILB_SERIRQ"),
577 PINCTRL_PIN(80, "USB_OC0_B"),
578 PINCTRL_PIN(81, "SDMMC3_CD_B"),
579 PINCTRL_PIN(82, "SPKR"),
580 PINCTRL_PIN(83, "SUSPWRDNACK"),
581 PINCTRL_PIN(84, "SPARE_PIN"),
582 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
583 };
584
585 static const unsigned southeast_pwm0_pins[] = { 5 };
586 static const unsigned southeast_pwm1_pins[] = { 1 };
587 static const unsigned southeast_sdmmc1_pins[] = {
588 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
589 };
590 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
591 static const unsigned southeast_sdmmc3_pins[] = {
592 30, 31, 32, 33, 34, 35, 78, 81, 85,
593 };
594 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
595 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
596
597 static const struct chv_pingroup southeast_groups[] = {
598 PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false),
599 PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false),
600 PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
601 PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
602 PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
603 PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false),
604 PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false),
605 };
606
607 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
608 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
609 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
610 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
611 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
612 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
613 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
614
615 static const struct intel_function southeast_functions[] = {
616 FUNCTION("pwm0", southeast_pwm0_groups),
617 FUNCTION("pwm1", southeast_pwm1_groups),
618 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
619 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
620 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
621 FUNCTION("spi1", southeast_spi1_groups),
622 FUNCTION("spi2", southeast_spi2_groups),
623 };
624
625 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
626 GPIO_PINRANGE(0, 7),
627 GPIO_PINRANGE(15, 26),
628 GPIO_PINRANGE(30, 35),
629 GPIO_PINRANGE(45, 52),
630 GPIO_PINRANGE(60, 69),
631 GPIO_PINRANGE(75, 85),
632 };
633
634 static const struct chv_community southeast_community = {
635 .uid = "4",
636 .pins = southeast_pins,
637 .npins = ARRAY_SIZE(southeast_pins),
638 .groups = southeast_groups,
639 .ngroups = ARRAY_SIZE(southeast_groups),
640 .functions = southeast_functions,
641 .nfunctions = ARRAY_SIZE(southeast_functions),
642 .gpio_ranges = southeast_gpio_ranges,
643 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
644 .nirqs = 16,
645 .acpi_space_id = 0x94,
646 };
647
648 static const struct chv_community *chv_communities[] = {
649 &southwest_community,
650 &north_community,
651 &east_community,
652 &southeast_community,
653 };
654
655 /*
656 * Lock to serialize register accesses
657 *
658 * Due to a silicon issue, a shared lock must be used to prevent
659 * concurrent accesses across the 4 GPIO controllers.
660 *
661 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
662 * errata #CHT34, for further information.
663 */
664 static DEFINE_RAW_SPINLOCK(chv_lock);
665
chv_padreg(struct chv_pinctrl * pctrl,unsigned int offset,unsigned int reg)666 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
667 unsigned int reg)
668 {
669 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
670 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
671
672 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
673 GPIO_REGS_SIZE * pad_no;
674
675 return pctrl->regs + offset + reg;
676 }
677
chv_writel(u32 value,void __iomem * reg)678 static void chv_writel(u32 value, void __iomem *reg)
679 {
680 writel(value, reg);
681 /* simple readback to confirm the bus transferring done */
682 readl(reg);
683 }
684
685 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
chv_pad_locked(struct chv_pinctrl * pctrl,unsigned int offset)686 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
687 {
688 void __iomem *reg;
689
690 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
691 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
692 }
693
chv_get_groups_count(struct pinctrl_dev * pctldev)694 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
695 {
696 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
697
698 return pctrl->community->ngroups;
699 }
700
chv_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)701 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
702 unsigned int group)
703 {
704 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
705
706 return pctrl->community->groups[group].name;
707 }
708
chv_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * npins)709 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
710 const unsigned int **pins, unsigned int *npins)
711 {
712 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
713
714 *pins = pctrl->community->groups[group].pins;
715 *npins = pctrl->community->groups[group].npins;
716 return 0;
717 }
718
chv_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int offset)719 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
720 unsigned int offset)
721 {
722 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
723 unsigned long flags;
724 u32 ctrl0, ctrl1;
725 bool locked;
726
727 raw_spin_lock_irqsave(&chv_lock, flags);
728
729 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
730 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
731 locked = chv_pad_locked(pctrl, offset);
732
733 raw_spin_unlock_irqrestore(&chv_lock, flags);
734
735 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
736 seq_puts(s, "GPIO ");
737 } else {
738 u32 mode;
739
740 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
741 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
742
743 seq_printf(s, "mode %d ", mode);
744 }
745
746 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
747
748 if (locked)
749 seq_puts(s, " [LOCKED]");
750 }
751
752 static const struct pinctrl_ops chv_pinctrl_ops = {
753 .get_groups_count = chv_get_groups_count,
754 .get_group_name = chv_get_group_name,
755 .get_group_pins = chv_get_group_pins,
756 .pin_dbg_show = chv_pin_dbg_show,
757 };
758
chv_get_functions_count(struct pinctrl_dev * pctldev)759 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
760 {
761 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
762
763 return pctrl->community->nfunctions;
764 }
765
chv_get_function_name(struct pinctrl_dev * pctldev,unsigned int function)766 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
767 unsigned int function)
768 {
769 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
770
771 return pctrl->community->functions[function].name;
772 }
773
chv_get_function_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned int * const ngroups)774 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
775 unsigned int function,
776 const char * const **groups,
777 unsigned int * const ngroups)
778 {
779 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
780
781 *groups = pctrl->community->functions[function].groups;
782 *ngroups = pctrl->community->functions[function].ngroups;
783 return 0;
784 }
785
chv_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)786 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
787 unsigned int function, unsigned int group)
788 {
789 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
790 const struct chv_pingroup *grp;
791 unsigned long flags;
792 int i;
793
794 grp = &pctrl->community->groups[group];
795
796 raw_spin_lock_irqsave(&chv_lock, flags);
797
798 /* Check first that the pad is not locked */
799 for (i = 0; i < grp->npins; i++) {
800 if (chv_pad_locked(pctrl, grp->pins[i])) {
801 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
802 grp->pins[i]);
803 raw_spin_unlock_irqrestore(&chv_lock, flags);
804 return -EBUSY;
805 }
806 }
807
808 for (i = 0; i < grp->npins; i++) {
809 const struct chv_alternate_function *altfunc = &grp->altfunc;
810 int pin = grp->pins[i];
811 void __iomem *reg;
812 u32 value;
813
814 /* Check if there is pin-specific config */
815 if (grp->overrides) {
816 int j;
817
818 for (j = 0; j < grp->noverrides; j++) {
819 if (grp->overrides[j].pin == pin) {
820 altfunc = &grp->overrides[j];
821 break;
822 }
823 }
824 }
825
826 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
827 value = readl(reg);
828 /* Disable GPIO mode */
829 value &= ~CHV_PADCTRL0_GPIOEN;
830 /* Set to desired mode */
831 value &= ~CHV_PADCTRL0_PMODE_MASK;
832 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
833 chv_writel(value, reg);
834
835 /* Update for invert_oe */
836 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
837 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
838 if (altfunc->invert_oe)
839 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
840 chv_writel(value, reg);
841
842 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
843 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
844 }
845
846 raw_spin_unlock_irqrestore(&chv_lock, flags);
847
848 return 0;
849 }
850
chv_gpio_clear_triggering(struct chv_pinctrl * pctrl,unsigned int offset)851 static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
852 unsigned int offset)
853 {
854 void __iomem *reg;
855 u32 value;
856
857 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
858 value = readl(reg);
859 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
860 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
861 chv_writel(value, reg);
862 }
863
chv_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)864 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
865 struct pinctrl_gpio_range *range,
866 unsigned int offset)
867 {
868 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
869 unsigned long flags;
870 void __iomem *reg;
871 u32 value;
872
873 raw_spin_lock_irqsave(&chv_lock, flags);
874
875 if (chv_pad_locked(pctrl, offset)) {
876 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
877 if (!(value & CHV_PADCTRL0_GPIOEN)) {
878 /* Locked so cannot enable */
879 raw_spin_unlock_irqrestore(&chv_lock, flags);
880 return -EBUSY;
881 }
882 } else {
883 int i;
884
885 /* Reset the interrupt mapping */
886 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
887 if (pctrl->intr_lines[i] == offset) {
888 pctrl->intr_lines[i] = 0;
889 break;
890 }
891 }
892
893 /* Disable interrupt generation */
894 chv_gpio_clear_triggering(pctrl, offset);
895
896 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
897 value = readl(reg);
898
899 /*
900 * If the pin is in HiZ mode (both TX and RX buffers are
901 * disabled) we turn it to be input now.
902 */
903 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
904 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
905 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
906 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
907 CHV_PADCTRL0_GPIOCFG_SHIFT;
908 }
909
910 /* Switch to a GPIO mode */
911 value |= CHV_PADCTRL0_GPIOEN;
912 chv_writel(value, reg);
913 }
914
915 raw_spin_unlock_irqrestore(&chv_lock, flags);
916
917 return 0;
918 }
919
chv_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)920 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
921 struct pinctrl_gpio_range *range,
922 unsigned int offset)
923 {
924 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
925 unsigned long flags;
926
927 raw_spin_lock_irqsave(&chv_lock, flags);
928
929 if (!chv_pad_locked(pctrl, offset))
930 chv_gpio_clear_triggering(pctrl, offset);
931
932 raw_spin_unlock_irqrestore(&chv_lock, flags);
933 }
934
chv_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)935 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
936 struct pinctrl_gpio_range *range,
937 unsigned int offset, bool input)
938 {
939 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
940 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
941 unsigned long flags;
942 u32 ctrl0;
943
944 raw_spin_lock_irqsave(&chv_lock, flags);
945
946 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
947 if (input)
948 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
949 else
950 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
951 chv_writel(ctrl0, reg);
952
953 raw_spin_unlock_irqrestore(&chv_lock, flags);
954
955 return 0;
956 }
957
958 static const struct pinmux_ops chv_pinmux_ops = {
959 .get_functions_count = chv_get_functions_count,
960 .get_function_name = chv_get_function_name,
961 .get_function_groups = chv_get_function_groups,
962 .set_mux = chv_pinmux_set_mux,
963 .gpio_request_enable = chv_gpio_request_enable,
964 .gpio_disable_free = chv_gpio_disable_free,
965 .gpio_set_direction = chv_gpio_set_direction,
966 };
967
chv_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)968 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
969 unsigned long *config)
970 {
971 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
972 enum pin_config_param param = pinconf_to_config_param(*config);
973 unsigned long flags;
974 u32 ctrl0, ctrl1;
975 u16 arg = 0;
976 u32 term;
977
978 raw_spin_lock_irqsave(&chv_lock, flags);
979 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
980 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
981 raw_spin_unlock_irqrestore(&chv_lock, flags);
982
983 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
984
985 switch (param) {
986 case PIN_CONFIG_BIAS_DISABLE:
987 if (term)
988 return -EINVAL;
989 break;
990
991 case PIN_CONFIG_BIAS_PULL_UP:
992 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
993 return -EINVAL;
994
995 switch (term) {
996 case CHV_PADCTRL0_TERM_20K:
997 arg = 20000;
998 break;
999 case CHV_PADCTRL0_TERM_5K:
1000 arg = 5000;
1001 break;
1002 case CHV_PADCTRL0_TERM_1K:
1003 arg = 1000;
1004 break;
1005 }
1006
1007 break;
1008
1009 case PIN_CONFIG_BIAS_PULL_DOWN:
1010 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1011 return -EINVAL;
1012
1013 switch (term) {
1014 case CHV_PADCTRL0_TERM_20K:
1015 arg = 20000;
1016 break;
1017 case CHV_PADCTRL0_TERM_5K:
1018 arg = 5000;
1019 break;
1020 }
1021
1022 break;
1023
1024 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1025 u32 cfg;
1026
1027 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1028 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1029 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1030 return -EINVAL;
1031
1032 break;
1033
1034 case PIN_CONFIG_DRIVE_PUSH_PULL:
1035 if (ctrl1 & CHV_PADCTRL1_ODEN)
1036 return -EINVAL;
1037 break;
1038
1039 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1040 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1041 return -EINVAL;
1042 break;
1043 }
1044
1045 default:
1046 return -ENOTSUPP;
1047 }
1048
1049 *config = pinconf_to_config_packed(param, arg);
1050 return 0;
1051 }
1052
chv_config_set_pull(struct chv_pinctrl * pctrl,unsigned int pin,enum pin_config_param param,u32 arg)1053 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
1054 enum pin_config_param param, u32 arg)
1055 {
1056 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1057 unsigned long flags;
1058 u32 ctrl0, pull;
1059
1060 raw_spin_lock_irqsave(&chv_lock, flags);
1061 ctrl0 = readl(reg);
1062
1063 switch (param) {
1064 case PIN_CONFIG_BIAS_DISABLE:
1065 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1066 break;
1067
1068 case PIN_CONFIG_BIAS_PULL_UP:
1069 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1070
1071 switch (arg) {
1072 case 1000:
1073 /* For 1k there is only pull up */
1074 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1075 break;
1076 case 5000:
1077 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1078 break;
1079 case 20000:
1080 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1081 break;
1082 default:
1083 raw_spin_unlock_irqrestore(&chv_lock, flags);
1084 return -EINVAL;
1085 }
1086
1087 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1088 break;
1089
1090 case PIN_CONFIG_BIAS_PULL_DOWN:
1091 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1092
1093 switch (arg) {
1094 case 5000:
1095 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1096 break;
1097 case 20000:
1098 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1099 break;
1100 default:
1101 raw_spin_unlock_irqrestore(&chv_lock, flags);
1102 return -EINVAL;
1103 }
1104
1105 ctrl0 |= pull;
1106 break;
1107
1108 default:
1109 raw_spin_unlock_irqrestore(&chv_lock, flags);
1110 return -EINVAL;
1111 }
1112
1113 chv_writel(ctrl0, reg);
1114 raw_spin_unlock_irqrestore(&chv_lock, flags);
1115
1116 return 0;
1117 }
1118
chv_config_set_oden(struct chv_pinctrl * pctrl,unsigned int pin,bool enable)1119 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1120 bool enable)
1121 {
1122 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1123 unsigned long flags;
1124 u32 ctrl1;
1125
1126 raw_spin_lock_irqsave(&chv_lock, flags);
1127 ctrl1 = readl(reg);
1128
1129 if (enable)
1130 ctrl1 |= CHV_PADCTRL1_ODEN;
1131 else
1132 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1133
1134 chv_writel(ctrl1, reg);
1135 raw_spin_unlock_irqrestore(&chv_lock, flags);
1136
1137 return 0;
1138 }
1139
chv_config_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int nconfigs)1140 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1141 unsigned long *configs, unsigned int nconfigs)
1142 {
1143 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1144 enum pin_config_param param;
1145 int i, ret;
1146 u32 arg;
1147
1148 if (chv_pad_locked(pctrl, pin))
1149 return -EBUSY;
1150
1151 for (i = 0; i < nconfigs; i++) {
1152 param = pinconf_to_config_param(configs[i]);
1153 arg = pinconf_to_config_argument(configs[i]);
1154
1155 switch (param) {
1156 case PIN_CONFIG_BIAS_DISABLE:
1157 case PIN_CONFIG_BIAS_PULL_UP:
1158 case PIN_CONFIG_BIAS_PULL_DOWN:
1159 ret = chv_config_set_pull(pctrl, pin, param, arg);
1160 if (ret)
1161 return ret;
1162 break;
1163
1164 case PIN_CONFIG_DRIVE_PUSH_PULL:
1165 ret = chv_config_set_oden(pctrl, pin, false);
1166 if (ret)
1167 return ret;
1168 break;
1169
1170 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1171 ret = chv_config_set_oden(pctrl, pin, true);
1172 if (ret)
1173 return ret;
1174 break;
1175
1176 default:
1177 return -ENOTSUPP;
1178 }
1179
1180 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1181 param, arg);
1182 }
1183
1184 return 0;
1185 }
1186
chv_config_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)1187 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1188 unsigned int group,
1189 unsigned long *config)
1190 {
1191 const unsigned int *pins;
1192 unsigned int npins;
1193 int ret;
1194
1195 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1196 if (ret)
1197 return ret;
1198
1199 ret = chv_config_get(pctldev, pins[0], config);
1200 if (ret)
1201 return ret;
1202
1203 return 0;
1204 }
1205
chv_config_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)1206 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1207 unsigned int group, unsigned long *configs,
1208 unsigned int num_configs)
1209 {
1210 const unsigned int *pins;
1211 unsigned int npins;
1212 int i, ret;
1213
1214 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1215 if (ret)
1216 return ret;
1217
1218 for (i = 0; i < npins; i++) {
1219 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1220 if (ret)
1221 return ret;
1222 }
1223
1224 return 0;
1225 }
1226
1227 static const struct pinconf_ops chv_pinconf_ops = {
1228 .is_generic = true,
1229 .pin_config_set = chv_config_set,
1230 .pin_config_get = chv_config_get,
1231 .pin_config_group_get = chv_config_group_get,
1232 .pin_config_group_set = chv_config_group_set,
1233 };
1234
1235 static struct pinctrl_desc chv_pinctrl_desc = {
1236 .pctlops = &chv_pinctrl_ops,
1237 .pmxops = &chv_pinmux_ops,
1238 .confops = &chv_pinconf_ops,
1239 .owner = THIS_MODULE,
1240 };
1241
chv_gpio_get(struct gpio_chip * chip,unsigned int offset)1242 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1243 {
1244 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1245 unsigned long flags;
1246 u32 ctrl0, cfg;
1247
1248 raw_spin_lock_irqsave(&chv_lock, flags);
1249 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1250 raw_spin_unlock_irqrestore(&chv_lock, flags);
1251
1252 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1253 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1254
1255 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1256 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1257 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1258 }
1259
chv_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)1260 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1261 {
1262 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1263 unsigned long flags;
1264 void __iomem *reg;
1265 u32 ctrl0;
1266
1267 raw_spin_lock_irqsave(&chv_lock, flags);
1268
1269 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
1270 ctrl0 = readl(reg);
1271
1272 if (value)
1273 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1274 else
1275 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1276
1277 chv_writel(ctrl0, reg);
1278
1279 raw_spin_unlock_irqrestore(&chv_lock, flags);
1280 }
1281
chv_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1282 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1283 {
1284 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1285 u32 ctrl0, direction;
1286 unsigned long flags;
1287
1288 raw_spin_lock_irqsave(&chv_lock, flags);
1289 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1290 raw_spin_unlock_irqrestore(&chv_lock, flags);
1291
1292 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1293 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1294
1295 return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1296 }
1297
chv_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1298 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1299 {
1300 return pinctrl_gpio_direction_input(chip->base + offset);
1301 }
1302
chv_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1303 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1304 int value)
1305 {
1306 chv_gpio_set(chip, offset, value);
1307 return pinctrl_gpio_direction_output(chip->base + offset);
1308 }
1309
1310 static const struct gpio_chip chv_gpio_chip = {
1311 .owner = THIS_MODULE,
1312 .request = gpiochip_generic_request,
1313 .free = gpiochip_generic_free,
1314 .get_direction = chv_gpio_get_direction,
1315 .direction_input = chv_gpio_direction_input,
1316 .direction_output = chv_gpio_direction_output,
1317 .get = chv_gpio_get,
1318 .set = chv_gpio_set,
1319 };
1320
chv_gpio_irq_ack(struct irq_data * d)1321 static void chv_gpio_irq_ack(struct irq_data *d)
1322 {
1323 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1324 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1325 int pin = irqd_to_hwirq(d);
1326 u32 intr_line;
1327
1328 raw_spin_lock(&chv_lock);
1329
1330 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1331 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1332 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1333 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1334
1335 raw_spin_unlock(&chv_lock);
1336 }
1337
chv_gpio_irq_mask_unmask(struct irq_data * d,bool mask)1338 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1339 {
1340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1341 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1342 int pin = irqd_to_hwirq(d);
1343 u32 value, intr_line;
1344 unsigned long flags;
1345
1346 raw_spin_lock_irqsave(&chv_lock, flags);
1347
1348 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1349 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1350 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1351
1352 value = readl(pctrl->regs + CHV_INTMASK);
1353 if (mask)
1354 value &= ~BIT(intr_line);
1355 else
1356 value |= BIT(intr_line);
1357 chv_writel(value, pctrl->regs + CHV_INTMASK);
1358
1359 raw_spin_unlock_irqrestore(&chv_lock, flags);
1360 }
1361
chv_gpio_irq_mask(struct irq_data * d)1362 static void chv_gpio_irq_mask(struct irq_data *d)
1363 {
1364 chv_gpio_irq_mask_unmask(d, true);
1365 }
1366
chv_gpio_irq_unmask(struct irq_data * d)1367 static void chv_gpio_irq_unmask(struct irq_data *d)
1368 {
1369 chv_gpio_irq_mask_unmask(d, false);
1370 }
1371
chv_gpio_irq_startup(struct irq_data * d)1372 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1373 {
1374 /*
1375 * Check if the interrupt has been requested with 0 as triggering
1376 * type. In that case it is assumed that the current values
1377 * programmed to the hardware are used (e.g BIOS configured
1378 * defaults).
1379 *
1380 * In that case ->irq_set_type() will never be called so we need to
1381 * read back the values from hardware now, set correct flow handler
1382 * and update mappings before the interrupt is being used.
1383 */
1384 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1385 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1386 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1387 unsigned int pin = irqd_to_hwirq(d);
1388 irq_flow_handler_t handler;
1389 unsigned long flags;
1390 u32 intsel, value;
1391
1392 raw_spin_lock_irqsave(&chv_lock, flags);
1393 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1394 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1395 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1396
1397 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1398 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1399 handler = handle_level_irq;
1400 else
1401 handler = handle_edge_irq;
1402
1403 if (!pctrl->intr_lines[intsel]) {
1404 irq_set_handler_locked(d, handler);
1405 pctrl->intr_lines[intsel] = pin;
1406 }
1407 raw_spin_unlock_irqrestore(&chv_lock, flags);
1408 }
1409
1410 chv_gpio_irq_unmask(d);
1411 return 0;
1412 }
1413
chv_gpio_irq_type(struct irq_data * d,unsigned int type)1414 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1415 {
1416 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1417 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1418 unsigned int pin = irqd_to_hwirq(d);
1419 unsigned long flags;
1420 u32 value;
1421
1422 raw_spin_lock_irqsave(&chv_lock, flags);
1423
1424 /*
1425 * Pins which can be used as shared interrupt are configured in
1426 * BIOS. Driver trusts BIOS configurations and assigns different
1427 * handler according to the irq type.
1428 *
1429 * Driver needs to save the mapping between each pin and
1430 * its interrupt line.
1431 * 1. If the pin cfg is locked in BIOS:
1432 * Trust BIOS has programmed IntWakeCfg bits correctly,
1433 * driver just needs to save the mapping.
1434 * 2. If the pin cfg is not locked in BIOS:
1435 * Driver programs the IntWakeCfg bits and save the mapping.
1436 */
1437 if (!chv_pad_locked(pctrl, pin)) {
1438 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1439
1440 value = readl(reg);
1441 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1442 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1443
1444 if (type & IRQ_TYPE_EDGE_BOTH) {
1445 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1446 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1447 else if (type & IRQ_TYPE_EDGE_RISING)
1448 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1449 else if (type & IRQ_TYPE_EDGE_FALLING)
1450 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1451 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1452 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1453 if (type & IRQ_TYPE_LEVEL_LOW)
1454 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1455 }
1456
1457 chv_writel(value, reg);
1458 }
1459
1460 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1461 value &= CHV_PADCTRL0_INTSEL_MASK;
1462 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1463
1464 pctrl->intr_lines[value] = pin;
1465
1466 if (type & IRQ_TYPE_EDGE_BOTH)
1467 irq_set_handler_locked(d, handle_edge_irq);
1468 else if (type & IRQ_TYPE_LEVEL_MASK)
1469 irq_set_handler_locked(d, handle_level_irq);
1470
1471 raw_spin_unlock_irqrestore(&chv_lock, flags);
1472
1473 return 0;
1474 }
1475
chv_gpio_irq_handler(struct irq_desc * desc)1476 static void chv_gpio_irq_handler(struct irq_desc *desc)
1477 {
1478 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1479 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1480 struct irq_chip *chip = irq_desc_get_chip(desc);
1481 unsigned long pending;
1482 unsigned long flags;
1483 u32 intr_line;
1484
1485 chained_irq_enter(chip, desc);
1486
1487 raw_spin_lock_irqsave(&chv_lock, flags);
1488 pending = readl(pctrl->regs + CHV_INTSTAT);
1489 raw_spin_unlock_irqrestore(&chv_lock, flags);
1490
1491 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1492 unsigned irq, offset;
1493
1494 offset = pctrl->intr_lines[intr_line];
1495 irq = irq_find_mapping(gc->irq.domain, offset);
1496 generic_handle_irq(irq);
1497 }
1498
1499 chained_irq_exit(chip, desc);
1500 }
1501
1502 /*
1503 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1504 * tables. Since we leave GPIOs that are not capable of generating
1505 * interrupts out of the irqdomain the numbering will be different and
1506 * cause devices using the hardcoded IRQ numbers fail. In order not to
1507 * break such machines we will only mask pins from irqdomain if the machine
1508 * is not listed below.
1509 */
1510 static const struct dmi_system_id chv_no_valid_mask[] = {
1511 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1512 {
1513 .ident = "Intel_Strago based Chromebooks (All models)",
1514 .matches = {
1515 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1516 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1517 },
1518 },
1519 {
1520 .ident = "HP Chromebook 11 G5 (Setzer)",
1521 .matches = {
1522 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1523 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1524 },
1525 },
1526 {
1527 .ident = "Acer Chromebook R11 (Cyan)",
1528 .matches = {
1529 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1530 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1531 },
1532 },
1533 {
1534 .ident = "Samsung Chromebook 3 (Celes)",
1535 .matches = {
1536 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1537 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1538 },
1539 },
1540 {}
1541 };
1542
chv_init_irq_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1543 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1544 unsigned long *valid_mask,
1545 unsigned int ngpios)
1546 {
1547 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1548 const struct chv_community *community = pctrl->community;
1549 int i;
1550
1551 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1552 for (i = 0; i < community->npins; i++) {
1553 const struct pinctrl_pin_desc *desc;
1554 u32 intsel;
1555
1556 desc = &community->pins[i];
1557
1558 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1559 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1560 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1561
1562 if (intsel >= community->nirqs)
1563 clear_bit(desc->number, valid_mask);
1564 }
1565 }
1566
chv_gpio_probe(struct chv_pinctrl * pctrl,int irq)1567 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1568 {
1569 const struct chv_gpio_pinrange *range;
1570 struct gpio_chip *chip = &pctrl->chip;
1571 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1572 const struct chv_community *community = pctrl->community;
1573 int ret, i, irq_base;
1574
1575 *chip = chv_gpio_chip;
1576
1577 chip->ngpio = community->pins[community->npins - 1].number + 1;
1578 chip->label = dev_name(pctrl->dev);
1579 chip->parent = pctrl->dev;
1580 chip->base = -1;
1581 if (need_valid_mask)
1582 chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1583
1584 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1585 if (ret) {
1586 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1587 return ret;
1588 }
1589
1590 for (i = 0; i < community->ngpio_ranges; i++) {
1591 range = &community->gpio_ranges[i];
1592 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1593 range->base, range->base,
1594 range->npins);
1595 if (ret) {
1596 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1597 return ret;
1598 }
1599 }
1600
1601 /*
1602 * The same set of machines in chv_no_valid_mask[] have incorrectly
1603 * configured GPIOs that generate spurious interrupts so we use
1604 * this same list to apply another quirk for them.
1605 *
1606 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1607 */
1608 if (!need_valid_mask) {
1609 /*
1610 * Mask all interrupts the community is able to generate
1611 * but leave the ones that can only generate GPEs unmasked.
1612 */
1613 chv_writel(GENMASK(31, pctrl->community->nirqs),
1614 pctrl->regs + CHV_INTMASK);
1615 }
1616
1617 /* Clear all interrupts */
1618 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1619
1620 if (!need_valid_mask) {
1621 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1622 community->npins, NUMA_NO_NODE);
1623 if (irq_base < 0) {
1624 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1625 return irq_base;
1626 }
1627 }
1628
1629 pctrl->irqchip.name = "chv-gpio";
1630 pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1631 pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1632 pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1633 pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1634 pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1635 pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
1636
1637 ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
1638 handle_bad_irq, IRQ_TYPE_NONE);
1639 if (ret) {
1640 dev_err(pctrl->dev, "failed to add IRQ chip\n");
1641 return ret;
1642 }
1643
1644 if (!need_valid_mask) {
1645 for (i = 0; i < community->ngpio_ranges; i++) {
1646 range = &community->gpio_ranges[i];
1647
1648 irq_domain_associate_many(chip->irq.domain, irq_base,
1649 range->base, range->npins);
1650 irq_base += range->npins;
1651 }
1652 }
1653
1654 gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
1655 chv_gpio_irq_handler);
1656 return 0;
1657 }
1658
chv_pinctrl_mmio_access_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1659 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1660 acpi_physical_address address, u32 bits, u64 *value,
1661 void *handler_context, void *region_context)
1662 {
1663 struct chv_pinctrl *pctrl = region_context;
1664 unsigned long flags;
1665 acpi_status ret = AE_OK;
1666
1667 raw_spin_lock_irqsave(&chv_lock, flags);
1668
1669 if (function == ACPI_WRITE)
1670 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1671 else if (function == ACPI_READ)
1672 *value = readl(pctrl->regs + (u32)address);
1673 else
1674 ret = AE_BAD_PARAMETER;
1675
1676 raw_spin_unlock_irqrestore(&chv_lock, flags);
1677
1678 return ret;
1679 }
1680
chv_pinctrl_probe(struct platform_device * pdev)1681 static int chv_pinctrl_probe(struct platform_device *pdev)
1682 {
1683 struct chv_pinctrl *pctrl;
1684 struct acpi_device *adev;
1685 acpi_status status;
1686 int ret, irq, i;
1687
1688 adev = ACPI_COMPANION(&pdev->dev);
1689 if (!adev)
1690 return -ENODEV;
1691
1692 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1693 if (!pctrl)
1694 return -ENOMEM;
1695
1696 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1697 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1698 pctrl->community = chv_communities[i];
1699 break;
1700 }
1701 if (i == ARRAY_SIZE(chv_communities))
1702 return -ENODEV;
1703
1704 pctrl->dev = &pdev->dev;
1705
1706 #ifdef CONFIG_PM_SLEEP
1707 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1708 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1709 GFP_KERNEL);
1710 if (!pctrl->saved_pin_context)
1711 return -ENOMEM;
1712 #endif
1713
1714 pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
1715 if (IS_ERR(pctrl->regs))
1716 return PTR_ERR(pctrl->regs);
1717
1718 irq = platform_get_irq(pdev, 0);
1719 if (irq < 0)
1720 return irq;
1721
1722 pctrl->pctldesc = chv_pinctrl_desc;
1723 pctrl->pctldesc.name = dev_name(&pdev->dev);
1724 pctrl->pctldesc.pins = pctrl->community->pins;
1725 pctrl->pctldesc.npins = pctrl->community->npins;
1726
1727 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1728 pctrl);
1729 if (IS_ERR(pctrl->pctldev)) {
1730 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1731 return PTR_ERR(pctrl->pctldev);
1732 }
1733
1734 ret = chv_gpio_probe(pctrl, irq);
1735 if (ret)
1736 return ret;
1737
1738 status = acpi_install_address_space_handler(adev->handle,
1739 pctrl->community->acpi_space_id,
1740 chv_pinctrl_mmio_access_handler,
1741 NULL, pctrl);
1742 if (ACPI_FAILURE(status))
1743 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1744
1745 platform_set_drvdata(pdev, pctrl);
1746
1747 return 0;
1748 }
1749
chv_pinctrl_remove(struct platform_device * pdev)1750 static int chv_pinctrl_remove(struct platform_device *pdev)
1751 {
1752 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1753
1754 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1755 pctrl->community->acpi_space_id,
1756 chv_pinctrl_mmio_access_handler);
1757
1758 return 0;
1759 }
1760
1761 #ifdef CONFIG_PM_SLEEP
chv_pinctrl_suspend_noirq(struct device * dev)1762 static int chv_pinctrl_suspend_noirq(struct device *dev)
1763 {
1764 struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1765 unsigned long flags;
1766 int i;
1767
1768 raw_spin_lock_irqsave(&chv_lock, flags);
1769
1770 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1771
1772 for (i = 0; i < pctrl->community->npins; i++) {
1773 const struct pinctrl_pin_desc *desc;
1774 struct chv_pin_context *ctx;
1775 void __iomem *reg;
1776
1777 desc = &pctrl->community->pins[i];
1778 if (chv_pad_locked(pctrl, desc->number))
1779 continue;
1780
1781 ctx = &pctrl->saved_pin_context[i];
1782
1783 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1784 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1785
1786 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1787 ctx->padctrl1 = readl(reg);
1788 }
1789
1790 raw_spin_unlock_irqrestore(&chv_lock, flags);
1791
1792 return 0;
1793 }
1794
chv_pinctrl_resume_noirq(struct device * dev)1795 static int chv_pinctrl_resume_noirq(struct device *dev)
1796 {
1797 struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1798 unsigned long flags;
1799 int i;
1800
1801 raw_spin_lock_irqsave(&chv_lock, flags);
1802
1803 /*
1804 * Mask all interrupts before restoring per-pin configuration
1805 * registers because we don't know in which state BIOS left them
1806 * upon exiting suspend.
1807 */
1808 chv_writel(0, pctrl->regs + CHV_INTMASK);
1809
1810 for (i = 0; i < pctrl->community->npins; i++) {
1811 const struct pinctrl_pin_desc *desc;
1812 const struct chv_pin_context *ctx;
1813 void __iomem *reg;
1814 u32 val;
1815
1816 desc = &pctrl->community->pins[i];
1817 if (chv_pad_locked(pctrl, desc->number))
1818 continue;
1819
1820 ctx = &pctrl->saved_pin_context[i];
1821
1822 /* Only restore if our saved state differs from the current */
1823 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1824 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1825 if (ctx->padctrl0 != val) {
1826 chv_writel(ctx->padctrl0, reg);
1827 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1828 desc->number, readl(reg));
1829 }
1830
1831 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1832 val = readl(reg);
1833 if (ctx->padctrl1 != val) {
1834 chv_writel(ctx->padctrl1, reg);
1835 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1836 desc->number, readl(reg));
1837 }
1838 }
1839
1840 /*
1841 * Now that all pins are restored to known state, we can restore
1842 * the interrupt mask register as well.
1843 */
1844 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1845 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1846
1847 raw_spin_unlock_irqrestore(&chv_lock, flags);
1848
1849 return 0;
1850 }
1851 #endif
1852
1853 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1854 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1855 chv_pinctrl_resume_noirq)
1856 };
1857
1858 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1859 { "INT33FF" },
1860 { }
1861 };
1862 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1863
1864 static struct platform_driver chv_pinctrl_driver = {
1865 .probe = chv_pinctrl_probe,
1866 .remove = chv_pinctrl_remove,
1867 .driver = {
1868 .name = "cherryview-pinctrl",
1869 .pm = &chv_pinctrl_pm_ops,
1870 .acpi_match_table = chv_pinctrl_acpi_match,
1871 },
1872 };
1873
chv_pinctrl_init(void)1874 static int __init chv_pinctrl_init(void)
1875 {
1876 return platform_driver_register(&chv_pinctrl_driver);
1877 }
1878 subsys_initcall(chv_pinctrl_init);
1879
chv_pinctrl_exit(void)1880 static void __exit chv_pinctrl_exit(void)
1881 {
1882 platform_driver_unregister(&chv_pinctrl_driver);
1883 }
1884 module_exit(chv_pinctrl_exit);
1885
1886 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1887 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1888 MODULE_LICENSE("GPL v2");
1889