1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 MediaTek Inc.
3
4 /*
5 * Library for MediaTek External Interrupt Support
6 *
7 * Author: Maoguang Meng <maoguang.meng@mediatek.com>
8 * Sean Wang <sean.wang@mediatek.com>
9 *
10 */
11
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/io.h>
16 #include <linux/irqchip/chained_irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/of_irq.h>
19 #include <linux/platform_device.h>
20
21 #include "mtk-eint.h"
22
23 #define MTK_EINT_EDGE_SENSITIVE 0
24 #define MTK_EINT_LEVEL_SENSITIVE 1
25 #define MTK_EINT_DBNC_SET_DBNC_BITS 4
26 #define MTK_EINT_DBNC_RST_BIT (0x1 << 1)
27 #define MTK_EINT_DBNC_SET_EN (0x1 << 0)
28
29 static const struct mtk_eint_regs mtk_generic_eint_regs = {
30 .stat = 0x000,
31 .ack = 0x040,
32 .mask = 0x080,
33 .mask_set = 0x0c0,
34 .mask_clr = 0x100,
35 .sens = 0x140,
36 .sens_set = 0x180,
37 .sens_clr = 0x1c0,
38 .soft = 0x200,
39 .soft_set = 0x240,
40 .soft_clr = 0x280,
41 .pol = 0x300,
42 .pol_set = 0x340,
43 .pol_clr = 0x380,
44 .dom_en = 0x400,
45 .dbnc_ctrl = 0x500,
46 .dbnc_set = 0x600,
47 .dbnc_clr = 0x700,
48 };
49
mtk_eint_get_offset(struct mtk_eint * eint,unsigned int eint_num,unsigned int offset)50 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
51 unsigned int eint_num,
52 unsigned int offset)
53 {
54 unsigned int eint_base = 0;
55 void __iomem *reg;
56
57 if (eint_num >= eint->hw->ap_num)
58 eint_base = eint->hw->ap_num;
59
60 reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;
61
62 return reg;
63 }
64
mtk_eint_can_en_debounce(struct mtk_eint * eint,unsigned int eint_num)65 static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
66 unsigned int eint_num)
67 {
68 unsigned int sens;
69 unsigned int bit = BIT(eint_num % 32);
70 void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
71 eint->regs->sens);
72
73 if (readl(reg) & bit)
74 sens = MTK_EINT_LEVEL_SENSITIVE;
75 else
76 sens = MTK_EINT_EDGE_SENSITIVE;
77
78 if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)
79 return 1;
80 else
81 return 0;
82 }
83
mtk_eint_flip_edge(struct mtk_eint * eint,int hwirq)84 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
85 {
86 int start_level, curr_level;
87 unsigned int reg_offset;
88 u32 mask = BIT(hwirq & 0x1f);
89 u32 port = (hwirq >> 5) & eint->hw->port_mask;
90 void __iomem *reg = eint->base + (port << 2);
91
92 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
93
94 do {
95 start_level = curr_level;
96 if (start_level)
97 reg_offset = eint->regs->pol_clr;
98 else
99 reg_offset = eint->regs->pol_set;
100 writel(mask, reg + reg_offset);
101
102 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
103 hwirq);
104 } while (start_level != curr_level);
105
106 return start_level;
107 }
108
mtk_eint_mask(struct irq_data * d)109 static void mtk_eint_mask(struct irq_data *d)
110 {
111 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
112 u32 mask = BIT(d->hwirq & 0x1f);
113 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
114 eint->regs->mask_set);
115
116 eint->cur_mask[d->hwirq >> 5] &= ~mask;
117
118 writel(mask, reg);
119 }
120
mtk_eint_unmask(struct irq_data * d)121 static void mtk_eint_unmask(struct irq_data *d)
122 {
123 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
124 u32 mask = BIT(d->hwirq & 0x1f);
125 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
126 eint->regs->mask_clr);
127
128 eint->cur_mask[d->hwirq >> 5] |= mask;
129
130 writel(mask, reg);
131
132 if (eint->dual_edge[d->hwirq])
133 mtk_eint_flip_edge(eint, d->hwirq);
134 }
135
mtk_eint_get_mask(struct mtk_eint * eint,unsigned int eint_num)136 static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
137 unsigned int eint_num)
138 {
139 unsigned int bit = BIT(eint_num % 32);
140 void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
141 eint->regs->mask);
142
143 return !!(readl(reg) & bit);
144 }
145
mtk_eint_ack(struct irq_data * d)146 static void mtk_eint_ack(struct irq_data *d)
147 {
148 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
149 u32 mask = BIT(d->hwirq & 0x1f);
150 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
151 eint->regs->ack);
152
153 writel(mask, reg);
154 }
155
mtk_eint_set_type(struct irq_data * d,unsigned int type)156 static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
157 {
158 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
159 u32 mask = BIT(d->hwirq & 0x1f);
160 void __iomem *reg;
161
162 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
163 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
164 dev_err(eint->dev,
165 "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
166 d->irq, d->hwirq, type);
167 return -EINVAL;
168 }
169
170 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
171 eint->dual_edge[d->hwirq] = 1;
172 else
173 eint->dual_edge[d->hwirq] = 0;
174
175 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
176 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
177 writel(mask, reg);
178 } else {
179 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
180 writel(mask, reg);
181 }
182
183 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
184 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
185 writel(mask, reg);
186 } else {
187 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
188 writel(mask, reg);
189 }
190
191 if (eint->dual_edge[d->hwirq])
192 mtk_eint_flip_edge(eint, d->hwirq);
193
194 return 0;
195 }
196
mtk_eint_irq_set_wake(struct irq_data * d,unsigned int on)197 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
198 {
199 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
200 int shift = d->hwirq & 0x1f;
201 int reg = d->hwirq >> 5;
202
203 if (on)
204 eint->wake_mask[reg] |= BIT(shift);
205 else
206 eint->wake_mask[reg] &= ~BIT(shift);
207
208 return 0;
209 }
210
mtk_eint_chip_write_mask(const struct mtk_eint * eint,void __iomem * base,u32 * buf)211 static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
212 void __iomem *base, u32 *buf)
213 {
214 int port;
215 void __iomem *reg;
216
217 for (port = 0; port < eint->hw->ports; port++) {
218 reg = base + (port << 2);
219 writel_relaxed(~buf[port], reg + eint->regs->mask_set);
220 writel_relaxed(buf[port], reg + eint->regs->mask_clr);
221 }
222 }
223
mtk_eint_irq_request_resources(struct irq_data * d)224 static int mtk_eint_irq_request_resources(struct irq_data *d)
225 {
226 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
227 struct gpio_chip *gpio_c;
228 unsigned int gpio_n;
229 int err;
230
231 err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
232 &gpio_n, &gpio_c);
233 if (err < 0) {
234 dev_err(eint->dev, "Can not find pin\n");
235 return err;
236 }
237
238 err = gpiochip_lock_as_irq(gpio_c, gpio_n);
239 if (err < 0) {
240 dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
241 irqd_to_hwirq(d));
242 return err;
243 }
244
245 err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
246 if (err < 0) {
247 dev_err(eint->dev, "Can not eint mode\n");
248 return err;
249 }
250
251 return 0;
252 }
253
mtk_eint_irq_release_resources(struct irq_data * d)254 static void mtk_eint_irq_release_resources(struct irq_data *d)
255 {
256 struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
257 struct gpio_chip *gpio_c;
258 unsigned int gpio_n;
259
260 eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
261 &gpio_c);
262
263 gpiochip_unlock_as_irq(gpio_c, gpio_n);
264 }
265
266 static struct irq_chip mtk_eint_irq_chip = {
267 .name = "mt-eint",
268 .irq_disable = mtk_eint_mask,
269 .irq_mask = mtk_eint_mask,
270 .irq_unmask = mtk_eint_unmask,
271 .irq_ack = mtk_eint_ack,
272 .irq_set_type = mtk_eint_set_type,
273 .irq_set_wake = mtk_eint_irq_set_wake,
274 .irq_request_resources = mtk_eint_irq_request_resources,
275 .irq_release_resources = mtk_eint_irq_release_resources,
276 };
277
mtk_eint_hw_init(struct mtk_eint * eint)278 static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
279 {
280 void __iomem *dom_en = eint->base + eint->regs->dom_en;
281 void __iomem *mask_set = eint->base + eint->regs->mask_set;
282 unsigned int i;
283
284 for (i = 0; i < eint->hw->ap_num; i += 32) {
285 writel(0xffffffff, dom_en);
286 writel(0xffffffff, mask_set);
287 dom_en += 4;
288 mask_set += 4;
289 }
290
291 return 0;
292 }
293
294 static inline void
mtk_eint_debounce_process(struct mtk_eint * eint,int index)295 mtk_eint_debounce_process(struct mtk_eint *eint, int index)
296 {
297 unsigned int rst, ctrl_offset;
298 unsigned int bit, dbnc;
299
300 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
301 dbnc = readl(eint->base + ctrl_offset);
302 bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8);
303 if ((bit & dbnc) > 0) {
304 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
305 rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8);
306 writel(rst, eint->base + ctrl_offset);
307 }
308 }
309
mtk_eint_irq_handler(struct irq_desc * desc)310 static void mtk_eint_irq_handler(struct irq_desc *desc)
311 {
312 struct irq_chip *chip = irq_desc_get_chip(desc);
313 struct mtk_eint *eint = irq_desc_get_handler_data(desc);
314 unsigned int status, eint_num;
315 int offset, mask_offset, index, virq;
316 void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
317 int dual_edge, start_level, curr_level;
318
319 chained_irq_enter(chip, desc);
320 for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,
321 reg += 4) {
322 status = readl(reg);
323 while (status) {
324 offset = __ffs(status);
325 mask_offset = eint_num >> 5;
326 index = eint_num + offset;
327 virq = irq_find_mapping(eint->domain, index);
328 status &= ~BIT(offset);
329
330 /*
331 * If we get an interrupt on pin that was only required
332 * for wake (but no real interrupt requested), mask the
333 * interrupt (as would mtk_eint_resume do anyway later
334 * in the resume sequence).
335 */
336 if (eint->wake_mask[mask_offset] & BIT(offset) &&
337 !(eint->cur_mask[mask_offset] & BIT(offset))) {
338 writel_relaxed(BIT(offset), reg -
339 eint->regs->stat +
340 eint->regs->mask_set);
341 }
342
343 dual_edge = eint->dual_edge[index];
344 if (dual_edge) {
345 /*
346 * Clear soft-irq in case we raised it last
347 * time.
348 */
349 writel(BIT(offset), reg - eint->regs->stat +
350 eint->regs->soft_clr);
351
352 start_level =
353 eint->gpio_xlate->get_gpio_state(eint->pctl,
354 index);
355 }
356
357 generic_handle_irq(virq);
358
359 if (dual_edge) {
360 curr_level = mtk_eint_flip_edge(eint, index);
361
362 /*
363 * If level changed, we might lost one edge
364 * interrupt, raised it through soft-irq.
365 */
366 if (start_level != curr_level)
367 writel(BIT(offset), reg -
368 eint->regs->stat +
369 eint->regs->soft_set);
370 }
371
372 if (index < eint->hw->db_cnt)
373 mtk_eint_debounce_process(eint, index);
374 }
375 }
376 chained_irq_exit(chip, desc);
377 }
378
mtk_eint_do_suspend(struct mtk_eint * eint)379 int mtk_eint_do_suspend(struct mtk_eint *eint)
380 {
381 mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
382
383 return 0;
384 }
385
mtk_eint_do_resume(struct mtk_eint * eint)386 int mtk_eint_do_resume(struct mtk_eint *eint)
387 {
388 mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
389
390 return 0;
391 }
392
mtk_eint_set_debounce(struct mtk_eint * eint,unsigned long eint_num,unsigned int debounce)393 int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
394 unsigned int debounce)
395 {
396 int virq, eint_offset;
397 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
398 dbnc;
399 static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
400 64000, 128000, 256000};
401 struct irq_data *d;
402
403 virq = irq_find_mapping(eint->domain, eint_num);
404 eint_offset = (eint_num % 4) * 8;
405 d = irq_get_irq_data(virq);
406
407 set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;
408 clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;
409
410 if (!mtk_eint_can_en_debounce(eint, eint_num))
411 return -EINVAL;
412
413 dbnc = ARRAY_SIZE(debounce_time);
414 for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
415 if (debounce <= debounce_time[i]) {
416 dbnc = i;
417 break;
418 }
419 }
420
421 if (!mtk_eint_get_mask(eint, eint_num)) {
422 mtk_eint_mask(d);
423 unmask = 1;
424 } else {
425 unmask = 0;
426 }
427
428 clr_bit = 0xff << eint_offset;
429 writel(clr_bit, eint->base + clr_offset);
430
431 bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
432 eint_offset;
433 rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
434 writel(rst | bit, eint->base + set_offset);
435
436 /*
437 * Delay a while (more than 2T) to wait for hw debounce counter reset
438 * work correctly.
439 */
440 udelay(1);
441 if (unmask == 1)
442 mtk_eint_unmask(d);
443
444 return 0;
445 }
446
mtk_eint_find_irq(struct mtk_eint * eint,unsigned long eint_n)447 int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
448 {
449 int irq;
450
451 irq = irq_find_mapping(eint->domain, eint_n);
452 if (!irq)
453 return -EINVAL;
454
455 return irq;
456 }
457
mtk_eint_do_init(struct mtk_eint * eint)458 int mtk_eint_do_init(struct mtk_eint *eint)
459 {
460 int i;
461
462 /* If clients don't assign a specific regs, let's use generic one */
463 if (!eint->regs)
464 eint->regs = &mtk_generic_eint_regs;
465
466 eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,
467 sizeof(*eint->wake_mask), GFP_KERNEL);
468 if (!eint->wake_mask)
469 return -ENOMEM;
470
471 eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,
472 sizeof(*eint->cur_mask), GFP_KERNEL);
473 if (!eint->cur_mask)
474 return -ENOMEM;
475
476 eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,
477 sizeof(int), GFP_KERNEL);
478 if (!eint->dual_edge)
479 return -ENOMEM;
480
481 eint->domain = irq_domain_add_linear(eint->dev->of_node,
482 eint->hw->ap_num,
483 &irq_domain_simple_ops, NULL);
484 if (!eint->domain)
485 return -ENOMEM;
486
487 mtk_eint_hw_init(eint);
488 for (i = 0; i < eint->hw->ap_num; i++) {
489 int virq = irq_create_mapping(eint->domain, i);
490
491 irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
492 handle_level_irq);
493 irq_set_chip_data(virq, eint);
494 }
495
496 irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
497 eint);
498
499 return 0;
500 }
501