1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
4 * bindings for MediaTek SoC.
5 *
6 * Copyright (C) 2018 MediaTek Inc.
7 * Author: Sean Wang <sean.wang@mediatek.com>
8 * Zhiyong Tao <zhiyong.tao@mediatek.com>
9 * Hongzhou.Yang <hongzhou.yang@mediatek.com>
10 */
11
12 #include <linux/gpio/driver.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-paris.h"
15
16 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
17
18 /* Custom pinconf parameters */
19 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
20 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
21 #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
22 #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
23 #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
24
25 static const struct pinconf_generic_params mtk_custom_bindings[] = {
26 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
27 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
28 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
29 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
30 {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
31 };
32
33 #ifdef CONFIG_DEBUG_FS
34 static const struct pin_config_item mtk_conf_items[] = {
35 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
36 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
37 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
38 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
39 PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
40 };
41 #endif
42
43 static const char * const mtk_gpio_functions[] = {
44 "func0", "func1", "func2", "func3",
45 "func4", "func5", "func6", "func7",
46 "func8", "func9", "func10", "func11",
47 "func12", "func13", "func14", "func15",
48 };
49
mtk_pinmux_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin)50 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
51 struct pinctrl_gpio_range *range,
52 unsigned int pin)
53 {
54 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
55 const struct mtk_pin_desc *desc;
56
57 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
58
59 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
60 hw->soc->gpio_m);
61 }
62
mtk_pinmux_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)63 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
64 struct pinctrl_gpio_range *range,
65 unsigned int pin, bool input)
66 {
67 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
68 const struct mtk_pin_desc *desc;
69
70 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
71
72 /* hardware would take 0 as input direction */
73 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
74 }
75
mtk_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)76 static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
77 unsigned int pin, unsigned long *config)
78 {
79 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
80 u32 param = pinconf_to_config_param(*config);
81 int val, val2, err, reg, ret = 1;
82 const struct mtk_pin_desc *desc;
83
84 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
85
86 switch (param) {
87 case PIN_CONFIG_BIAS_DISABLE:
88 if (hw->soc->bias_disable_get) {
89 err = hw->soc->bias_disable_get(hw, desc, &ret);
90 if (err)
91 return err;
92 } else {
93 return -ENOTSUPP;
94 }
95 break;
96 case PIN_CONFIG_BIAS_PULL_UP:
97 if (hw->soc->bias_get) {
98 err = hw->soc->bias_get(hw, desc, 1, &ret);
99 if (err)
100 return err;
101 } else {
102 return -ENOTSUPP;
103 }
104 break;
105 case PIN_CONFIG_BIAS_PULL_DOWN:
106 if (hw->soc->bias_get) {
107 err = hw->soc->bias_get(hw, desc, 0, &ret);
108 if (err)
109 return err;
110 } else {
111 return -ENOTSUPP;
112 }
113 break;
114 case PIN_CONFIG_SLEW_RATE:
115 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
116 if (err)
117 return err;
118
119 if (!val)
120 return -EINVAL;
121
122 break;
123 case PIN_CONFIG_INPUT_ENABLE:
124 case PIN_CONFIG_OUTPUT_ENABLE:
125 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
126 if (err)
127 return err;
128
129 /* HW takes input mode as zero; output mode as non-zero */
130 if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
131 (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
132 return -EINVAL;
133
134 break;
135 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
136 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
137 if (err)
138 return err;
139
140 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
141 if (err)
142 return err;
143
144 if (val || !val2)
145 return -EINVAL;
146
147 break;
148 case PIN_CONFIG_DRIVE_STRENGTH:
149 if (hw->soc->drive_get) {
150 err = hw->soc->drive_get(hw, desc, &ret);
151 if (err)
152 return err;
153 } else {
154 err = -ENOTSUPP;
155 }
156 break;
157 case MTK_PIN_CONFIG_TDSEL:
158 case MTK_PIN_CONFIG_RDSEL:
159 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
160 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
161
162 err = mtk_hw_get_value(hw, desc, reg, &val);
163 if (err)
164 return err;
165
166 ret = val;
167
168 break;
169 case MTK_PIN_CONFIG_PU_ADV:
170 case MTK_PIN_CONFIG_PD_ADV:
171 if (hw->soc->adv_pull_get) {
172 bool pullup;
173
174 pullup = param == MTK_PIN_CONFIG_PU_ADV;
175 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
176 if (err)
177 return err;
178 } else {
179 return -ENOTSUPP;
180 }
181 break;
182 case MTK_PIN_CONFIG_DRV_ADV:
183 if (hw->soc->adv_drive_get) {
184 err = hw->soc->adv_drive_get(hw, desc, &ret);
185 if (err)
186 return err;
187 } else {
188 return -ENOTSUPP;
189 }
190 break;
191 default:
192 return -ENOTSUPP;
193 }
194
195 *config = pinconf_to_config_packed(param, ret);
196
197 return 0;
198 }
199
mtk_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,enum pin_config_param param,u32 arg)200 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
201 enum pin_config_param param, u32 arg)
202 {
203 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
204 const struct mtk_pin_desc *desc;
205 int err = 0;
206 u32 reg;
207
208 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
209
210 switch ((u32)param) {
211 case PIN_CONFIG_BIAS_DISABLE:
212 if (hw->soc->bias_disable_set) {
213 err = hw->soc->bias_disable_set(hw, desc);
214 if (err)
215 return err;
216 } else {
217 return -ENOTSUPP;
218 }
219 break;
220 case PIN_CONFIG_BIAS_PULL_UP:
221 if (hw->soc->bias_set) {
222 err = hw->soc->bias_set(hw, desc, 1);
223 if (err)
224 return err;
225 } else {
226 return -ENOTSUPP;
227 }
228 break;
229 case PIN_CONFIG_BIAS_PULL_DOWN:
230 if (hw->soc->bias_set) {
231 err = hw->soc->bias_set(hw, desc, 0);
232 if (err)
233 return err;
234 } else {
235 return -ENOTSUPP;
236 }
237 break;
238 case PIN_CONFIG_OUTPUT_ENABLE:
239 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
240 MTK_DISABLE);
241 if (err)
242 goto err;
243
244 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
245 MTK_OUTPUT);
246 if (err)
247 goto err;
248 break;
249 case PIN_CONFIG_INPUT_ENABLE:
250 if (hw->soc->ies_present) {
251 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
252 MTK_ENABLE);
253 }
254
255 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
256 MTK_INPUT);
257 if (err)
258 goto err;
259 break;
260 case PIN_CONFIG_SLEW_RATE:
261 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
262 arg);
263 if (err)
264 goto err;
265
266 break;
267 case PIN_CONFIG_OUTPUT:
268 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
269 MTK_OUTPUT);
270 if (err)
271 goto err;
272
273 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
274 arg);
275 if (err)
276 goto err;
277 break;
278 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
279 /* arg = 1: Input mode & SMT enable ;
280 * arg = 0: Output mode & SMT disable
281 */
282 arg = arg ? 2 : 1;
283 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
284 arg & 1);
285 if (err)
286 goto err;
287
288 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
289 !!(arg & 2));
290 if (err)
291 goto err;
292 break;
293 case PIN_CONFIG_DRIVE_STRENGTH:
294 if (hw->soc->drive_set) {
295 err = hw->soc->drive_set(hw, desc, arg);
296 if (err)
297 return err;
298 } else {
299 return -ENOTSUPP;
300 }
301 break;
302 case MTK_PIN_CONFIG_TDSEL:
303 case MTK_PIN_CONFIG_RDSEL:
304 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
305 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
306
307 err = mtk_hw_set_value(hw, desc, reg, arg);
308 if (err)
309 goto err;
310 break;
311 case MTK_PIN_CONFIG_PU_ADV:
312 case MTK_PIN_CONFIG_PD_ADV:
313 if (hw->soc->adv_pull_set) {
314 bool pullup;
315
316 pullup = param == MTK_PIN_CONFIG_PU_ADV;
317 err = hw->soc->adv_pull_set(hw, desc, pullup,
318 arg);
319 if (err)
320 return err;
321 } else {
322 return -ENOTSUPP;
323 }
324 break;
325 case MTK_PIN_CONFIG_DRV_ADV:
326 if (hw->soc->adv_drive_set) {
327 err = hw->soc->adv_drive_set(hw, desc, arg);
328 if (err)
329 return err;
330 } else {
331 return -ENOTSUPP;
332 }
333 break;
334 default:
335 err = -ENOTSUPP;
336 }
337
338 err:
339 return err;
340 }
341
342 static struct mtk_pinctrl_group *
mtk_pctrl_find_group_by_pin(struct mtk_pinctrl * hw,u32 pin)343 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
344 {
345 int i;
346
347 for (i = 0; i < hw->soc->ngrps; i++) {
348 struct mtk_pinctrl_group *grp = hw->groups + i;
349
350 if (grp->pin == pin)
351 return grp;
352 }
353
354 return NULL;
355 }
356
357 static const struct mtk_func_desc *
mtk_pctrl_find_function_by_pin(struct mtk_pinctrl * hw,u32 pin_num,u32 fnum)358 mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
359 {
360 const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
361 const struct mtk_func_desc *func = pin->funcs;
362
363 while (func && func->name) {
364 if (func->muxval == fnum)
365 return func;
366 func++;
367 }
368
369 return NULL;
370 }
371
mtk_pctrl_is_function_valid(struct mtk_pinctrl * hw,u32 pin_num,u32 fnum)372 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
373 u32 fnum)
374 {
375 int i;
376
377 for (i = 0; i < hw->soc->npins; i++) {
378 const struct mtk_pin_desc *pin = hw->soc->pins + i;
379
380 if (pin->number == pin_num) {
381 const struct mtk_func_desc *func = pin->funcs;
382
383 while (func && func->name) {
384 if (func->muxval == fnum)
385 return true;
386 func++;
387 }
388
389 break;
390 }
391 }
392
393 return false;
394 }
395
mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl * pctl,u32 pin,u32 fnum,struct mtk_pinctrl_group * grp,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)396 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
397 u32 pin, u32 fnum,
398 struct mtk_pinctrl_group *grp,
399 struct pinctrl_map **map,
400 unsigned *reserved_maps,
401 unsigned *num_maps)
402 {
403 bool ret;
404
405 if (*num_maps == *reserved_maps)
406 return -ENOSPC;
407
408 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
409 (*map)[*num_maps].data.mux.group = grp->name;
410
411 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
412 if (!ret) {
413 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
414 fnum, pin);
415 return -EINVAL;
416 }
417
418 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
419 (*num_maps)++;
420
421 return 0;
422 }
423
mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * node,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)424 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
425 struct device_node *node,
426 struct pinctrl_map **map,
427 unsigned *reserved_maps,
428 unsigned *num_maps)
429 {
430 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
431 int num_pins, num_funcs, maps_per_pin, i, err;
432 struct mtk_pinctrl_group *grp;
433 unsigned int num_configs;
434 bool has_config = false;
435 unsigned long *configs;
436 u32 pinfunc, pin, func;
437 struct property *pins;
438 unsigned reserve = 0;
439
440 pins = of_find_property(node, "pinmux", NULL);
441 if (!pins) {
442 dev_err(hw->dev, "missing pins property in node %pOFn .\n",
443 node);
444 return -EINVAL;
445 }
446
447 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
448 &num_configs);
449 if (err)
450 return err;
451
452 if (num_configs)
453 has_config = true;
454
455 num_pins = pins->length / sizeof(u32);
456 num_funcs = num_pins;
457 maps_per_pin = 0;
458 if (num_funcs)
459 maps_per_pin++;
460 if (has_config && num_pins >= 1)
461 maps_per_pin++;
462
463 if (!num_pins || !maps_per_pin) {
464 err = -EINVAL;
465 goto exit;
466 }
467
468 reserve = num_pins * maps_per_pin;
469
470 err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
471 reserve);
472 if (err < 0)
473 goto exit;
474
475 for (i = 0; i < num_pins; i++) {
476 err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
477 if (err)
478 goto exit;
479
480 pin = MTK_GET_PIN_NO(pinfunc);
481 func = MTK_GET_PIN_FUNC(pinfunc);
482
483 if (pin >= hw->soc->npins ||
484 func >= ARRAY_SIZE(mtk_gpio_functions)) {
485 dev_err(hw->dev, "invalid pins value.\n");
486 err = -EINVAL;
487 goto exit;
488 }
489
490 grp = mtk_pctrl_find_group_by_pin(hw, pin);
491 if (!grp) {
492 dev_err(hw->dev, "unable to match pin %d to group\n",
493 pin);
494 err = -EINVAL;
495 goto exit;
496 }
497
498 err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
499 reserved_maps, num_maps);
500 if (err < 0)
501 goto exit;
502
503 if (has_config) {
504 err = pinctrl_utils_add_map_configs(pctldev, map,
505 reserved_maps,
506 num_maps,
507 grp->name,
508 configs,
509 num_configs,
510 PIN_MAP_TYPE_CONFIGS_GROUP);
511 if (err < 0)
512 goto exit;
513 }
514 }
515
516 err = 0;
517
518 exit:
519 kfree(configs);
520 return err;
521 }
522
mtk_pctrl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,unsigned * num_maps)523 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
524 struct device_node *np_config,
525 struct pinctrl_map **map,
526 unsigned *num_maps)
527 {
528 struct device_node *np;
529 unsigned reserved_maps;
530 int ret;
531
532 *map = NULL;
533 *num_maps = 0;
534 reserved_maps = 0;
535
536 for_each_child_of_node(np_config, np) {
537 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
538 &reserved_maps,
539 num_maps);
540 if (ret < 0) {
541 pinctrl_utils_free_map(pctldev, *map, *num_maps);
542 of_node_put(np);
543 return ret;
544 }
545 }
546
547 return 0;
548 }
549
mtk_pctrl_get_groups_count(struct pinctrl_dev * pctldev)550 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
551 {
552 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
553
554 return hw->soc->ngrps;
555 }
556
mtk_pctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned group)557 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
558 unsigned group)
559 {
560 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
561
562 return hw->groups[group].name;
563 }
564
mtk_pctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)565 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
566 unsigned group, const unsigned **pins,
567 unsigned *num_pins)
568 {
569 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
570
571 *pins = (unsigned *)&hw->groups[group].pin;
572 *num_pins = 1;
573
574 return 0;
575 }
576
577 static const struct pinctrl_ops mtk_pctlops = {
578 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
579 .dt_free_map = pinctrl_utils_free_map,
580 .get_groups_count = mtk_pctrl_get_groups_count,
581 .get_group_name = mtk_pctrl_get_group_name,
582 .get_group_pins = mtk_pctrl_get_group_pins,
583 };
584
mtk_pmx_get_funcs_cnt(struct pinctrl_dev * pctldev)585 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
586 {
587 return ARRAY_SIZE(mtk_gpio_functions);
588 }
589
mtk_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)590 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
591 unsigned selector)
592 {
593 return mtk_gpio_functions[selector];
594 }
595
mtk_pmx_get_func_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_groups)596 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
597 unsigned function,
598 const char * const **groups,
599 unsigned * const num_groups)
600 {
601 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
602
603 *groups = hw->grp_names;
604 *num_groups = hw->soc->ngrps;
605
606 return 0;
607 }
608
mtk_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned function,unsigned group)609 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
610 unsigned function,
611 unsigned group)
612 {
613 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
614 struct mtk_pinctrl_group *grp = hw->groups + group;
615 const struct mtk_func_desc *desc_func;
616 const struct mtk_pin_desc *desc;
617 bool ret;
618
619 ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
620 if (!ret) {
621 dev_err(hw->dev, "invalid function %d on group %d .\n",
622 function, group);
623 return -EINVAL;
624 }
625
626 desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
627 if (!desc_func)
628 return -EINVAL;
629
630 desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
631 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
632
633 return 0;
634 }
635
636 static const struct pinmux_ops mtk_pmxops = {
637 .get_functions_count = mtk_pmx_get_funcs_cnt,
638 .get_function_name = mtk_pmx_get_func_name,
639 .get_function_groups = mtk_pmx_get_func_groups,
640 .set_mux = mtk_pmx_set_mux,
641 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
642 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
643 };
644
mtk_pconf_group_get(struct pinctrl_dev * pctldev,unsigned group,unsigned long * config)645 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
646 unsigned long *config)
647 {
648 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
649 struct mtk_pinctrl_group *grp = &hw->groups[group];
650
651 /* One pin per group only */
652 return mtk_pinconf_get(pctldev, grp->pin, config);
653 }
654
mtk_pconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)655 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
656 unsigned long *configs, unsigned num_configs)
657 {
658 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
659 struct mtk_pinctrl_group *grp = &hw->groups[group];
660 int i, ret;
661
662 for (i = 0; i < num_configs; i++) {
663 ret = mtk_pinconf_set(pctldev, grp->pin,
664 pinconf_to_config_param(configs[i]),
665 pinconf_to_config_argument(configs[i]));
666 if (ret < 0)
667 return ret;
668 }
669
670 return 0;
671 }
672
673 static const struct pinconf_ops mtk_confops = {
674 .pin_config_get = mtk_pinconf_get,
675 .pin_config_group_get = mtk_pconf_group_get,
676 .pin_config_group_set = mtk_pconf_group_set,
677 };
678
679 static struct pinctrl_desc mtk_desc = {
680 .name = PINCTRL_PINCTRL_DEV,
681 .pctlops = &mtk_pctlops,
682 .pmxops = &mtk_pmxops,
683 .confops = &mtk_confops,
684 .owner = THIS_MODULE,
685 };
686
mtk_gpio_get_direction(struct gpio_chip * chip,unsigned int gpio)687 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
688 {
689 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
690 const struct mtk_pin_desc *desc;
691 int value, err;
692
693 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
694
695 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
696 if (err)
697 return err;
698
699 return !value;
700 }
701
mtk_gpio_get(struct gpio_chip * chip,unsigned int gpio)702 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
703 {
704 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
705 const struct mtk_pin_desc *desc;
706 int value, err;
707
708 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
709
710 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
711 if (err)
712 return err;
713
714 return !!value;
715 }
716
mtk_gpio_set(struct gpio_chip * chip,unsigned int gpio,int value)717 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
718 {
719 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
720 const struct mtk_pin_desc *desc;
721
722 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
723
724 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
725 }
726
mtk_gpio_direction_input(struct gpio_chip * chip,unsigned int gpio)727 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
728 {
729 return pinctrl_gpio_direction_input(chip->base + gpio);
730 }
731
mtk_gpio_direction_output(struct gpio_chip * chip,unsigned int gpio,int value)732 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
733 int value)
734 {
735 mtk_gpio_set(chip, gpio, value);
736
737 return pinctrl_gpio_direction_output(chip->base + gpio);
738 }
739
mtk_gpio_to_irq(struct gpio_chip * chip,unsigned int offset)740 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
741 {
742 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
743 const struct mtk_pin_desc *desc;
744
745 if (!hw->eint)
746 return -ENOTSUPP;
747
748 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
749
750 if (desc->eint.eint_n == EINT_NA)
751 return -ENOTSUPP;
752
753 return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
754 }
755
mtk_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)756 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
757 unsigned long config)
758 {
759 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
760 const struct mtk_pin_desc *desc;
761 u32 debounce;
762
763 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
764
765 if (!hw->eint ||
766 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
767 desc->eint.eint_n == EINT_NA)
768 return -ENOTSUPP;
769
770 debounce = pinconf_to_config_argument(config);
771
772 return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
773 }
774
mtk_build_gpiochip(struct mtk_pinctrl * hw,struct device_node * np)775 static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
776 {
777 struct gpio_chip *chip = &hw->chip;
778 int ret;
779
780 chip->label = PINCTRL_PINCTRL_DEV;
781 chip->parent = hw->dev;
782 chip->request = gpiochip_generic_request;
783 chip->free = gpiochip_generic_free;
784 chip->get_direction = mtk_gpio_get_direction;
785 chip->direction_input = mtk_gpio_direction_input;
786 chip->direction_output = mtk_gpio_direction_output;
787 chip->get = mtk_gpio_get;
788 chip->set = mtk_gpio_set;
789 chip->to_irq = mtk_gpio_to_irq,
790 chip->set_config = mtk_gpio_set_config,
791 chip->base = -1;
792 chip->ngpio = hw->soc->npins;
793 chip->of_node = np;
794 chip->of_gpio_n_cells = 2;
795
796 ret = gpiochip_add_data(chip, hw);
797 if (ret < 0)
798 return ret;
799
800 return 0;
801 }
802
mtk_pctrl_build_state(struct platform_device * pdev)803 static int mtk_pctrl_build_state(struct platform_device *pdev)
804 {
805 struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
806 int i;
807
808 /* Allocate groups */
809 hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
810 sizeof(*hw->groups), GFP_KERNEL);
811 if (!hw->groups)
812 return -ENOMEM;
813
814 /* We assume that one pin is one group, use pin name as group name. */
815 hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
816 sizeof(*hw->grp_names), GFP_KERNEL);
817 if (!hw->grp_names)
818 return -ENOMEM;
819
820 for (i = 0; i < hw->soc->npins; i++) {
821 const struct mtk_pin_desc *pin = hw->soc->pins + i;
822 struct mtk_pinctrl_group *group = hw->groups + i;
823
824 group->name = pin->name;
825 group->pin = pin->number;
826
827 hw->grp_names[i] = pin->name;
828 }
829
830 return 0;
831 }
832
mtk_paris_pinctrl_probe(struct platform_device * pdev,const struct mtk_pin_soc * soc)833 int mtk_paris_pinctrl_probe(struct platform_device *pdev,
834 const struct mtk_pin_soc *soc)
835 {
836 struct pinctrl_pin_desc *pins;
837 struct mtk_pinctrl *hw;
838 struct resource *res;
839 int err, i;
840
841 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
842 if (!hw)
843 return -ENOMEM;
844
845 platform_set_drvdata(pdev, hw);
846 hw->soc = soc;
847 hw->dev = &pdev->dev;
848
849 if (!hw->soc->nbase_names) {
850 dev_err(&pdev->dev,
851 "SoC should be assigned at least one register base\n");
852 return -EINVAL;
853 }
854
855 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
856 sizeof(*hw->base), GFP_KERNEL);
857 if (!hw->base)
858 return -ENOMEM;
859
860 for (i = 0; i < hw->soc->nbase_names; i++) {
861 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
862 hw->soc->base_names[i]);
863 if (!res) {
864 dev_err(&pdev->dev, "missing IO resource\n");
865 return -ENXIO;
866 }
867
868 hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
869 if (IS_ERR(hw->base[i]))
870 return PTR_ERR(hw->base[i]);
871 }
872
873 hw->nbase = hw->soc->nbase_names;
874
875 err = mtk_pctrl_build_state(pdev);
876 if (err) {
877 dev_err(&pdev->dev, "build state failed: %d\n", err);
878 return -EINVAL;
879 }
880
881 /* Copy from internal struct mtk_pin_desc to register to the core */
882 pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
883 GFP_KERNEL);
884 if (!pins)
885 return -ENOMEM;
886
887 for (i = 0; i < hw->soc->npins; i++) {
888 pins[i].number = hw->soc->pins[i].number;
889 pins[i].name = hw->soc->pins[i].name;
890 }
891
892 /* Setup pins descriptions per SoC types */
893 mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
894 mtk_desc.npins = hw->soc->npins;
895 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
896 mtk_desc.custom_params = mtk_custom_bindings;
897 #ifdef CONFIG_DEBUG_FS
898 mtk_desc.custom_conf_items = mtk_conf_items;
899 #endif
900
901 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
902 &hw->pctrl);
903 if (err)
904 return err;
905
906 err = pinctrl_enable(hw->pctrl);
907 if (err)
908 return err;
909
910 err = mtk_build_eint(hw, pdev);
911 if (err)
912 dev_warn(&pdev->dev,
913 "Failed to add EINT, but pinctrl still can work\n");
914
915 /* Build gpiochip should be after pinctrl_enable is done */
916 err = mtk_build_gpiochip(hw, pdev->dev.of_node);
917 if (err) {
918 dev_err(&pdev->dev, "Failed to add gpio_chip\n");
919 return err;
920 }
921
922 platform_set_drvdata(pdev, hw);
923
924 return 0;
925 }
926
mtk_paris_pinctrl_suspend(struct device * device)927 static int mtk_paris_pinctrl_suspend(struct device *device)
928 {
929 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
930
931 return mtk_eint_do_suspend(pctl->eint);
932 }
933
mtk_paris_pinctrl_resume(struct device * device)934 static int mtk_paris_pinctrl_resume(struct device *device)
935 {
936 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
937
938 return mtk_eint_do_resume(pctl->eint);
939 }
940
941 const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
942 .suspend_noirq = mtk_paris_pinctrl_suspend,
943 .resume_noirq = mtk_paris_pinctrl_resume,
944 };
945