1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
11 */
12
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34
35 #include "core.h"
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
38
amd_gpio_get_direction(struct gpio_chip * gc,unsigned offset)39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
40 {
41 unsigned long flags;
42 u32 pin_reg;
43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
44
45 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
46 pin_reg = readl(gpio_dev->base + offset * 4);
47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
48
49 return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
50 }
51
amd_gpio_direction_input(struct gpio_chip * gc,unsigned offset)52 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
53 {
54 unsigned long flags;
55 u32 pin_reg;
56 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
57
58 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
59 pin_reg = readl(gpio_dev->base + offset * 4);
60 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
61 writel(pin_reg, gpio_dev->base + offset * 4);
62 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
63
64 return 0;
65 }
66
amd_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)67 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
68 int value)
69 {
70 u32 pin_reg;
71 unsigned long flags;
72 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
73
74 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
75 pin_reg = readl(gpio_dev->base + offset * 4);
76 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
77 if (value)
78 pin_reg |= BIT(OUTPUT_VALUE_OFF);
79 else
80 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
81 writel(pin_reg, gpio_dev->base + offset * 4);
82 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
83
84 return 0;
85 }
86
amd_gpio_get_value(struct gpio_chip * gc,unsigned offset)87 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
88 {
89 u32 pin_reg;
90 unsigned long flags;
91 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
92
93 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
94 pin_reg = readl(gpio_dev->base + offset * 4);
95 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
96
97 return !!(pin_reg & BIT(PIN_STS_OFF));
98 }
99
amd_gpio_set_value(struct gpio_chip * gc,unsigned offset,int value)100 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
101 {
102 u32 pin_reg;
103 unsigned long flags;
104 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
105
106 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
107 pin_reg = readl(gpio_dev->base + offset * 4);
108 if (value)
109 pin_reg |= BIT(OUTPUT_VALUE_OFF);
110 else
111 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
112 writel(pin_reg, gpio_dev->base + offset * 4);
113 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
114 }
115
amd_gpio_set_debounce(struct gpio_chip * gc,unsigned offset,unsigned debounce)116 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
117 unsigned debounce)
118 {
119 u32 time;
120 u32 pin_reg;
121 int ret = 0;
122 unsigned long flags;
123 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
124
125 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
126
127 /* Use special handling for Pin0 debounce */
128 if (offset == 0) {
129 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
130 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
131 debounce = 0;
132 }
133
134 pin_reg = readl(gpio_dev->base + offset * 4);
135
136 if (debounce) {
137 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
138 pin_reg &= ~DB_TMR_OUT_MASK;
139 /*
140 Debounce Debounce Timer Max
141 TmrLarge TmrOutUnit Unit Debounce
142 Time
143 0 0 61 usec (2 RtcClk) 976 usec
144 0 1 244 usec (8 RtcClk) 3.9 msec
145 1 0 15.6 msec (512 RtcClk) 250 msec
146 1 1 62.5 msec (2048 RtcClk) 1 sec
147 */
148
149 if (debounce < 61) {
150 pin_reg |= 1;
151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
153 } else if (debounce < 976) {
154 time = debounce / 61;
155 pin_reg |= time & DB_TMR_OUT_MASK;
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 } else if (debounce < 3900) {
159 time = debounce / 244;
160 pin_reg |= time & DB_TMR_OUT_MASK;
161 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
162 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
163 } else if (debounce < 250000) {
164 time = debounce / 15625;
165 pin_reg |= time & DB_TMR_OUT_MASK;
166 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
167 pin_reg |= BIT(DB_TMR_LARGE_OFF);
168 } else if (debounce < 1000000) {
169 time = debounce / 62500;
170 pin_reg |= time & DB_TMR_OUT_MASK;
171 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
172 pin_reg |= BIT(DB_TMR_LARGE_OFF);
173 } else {
174 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
175 ret = -EINVAL;
176 }
177 } else {
178 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
179 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
180 pin_reg &= ~DB_TMR_OUT_MASK;
181 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
182 }
183 writel(pin_reg, gpio_dev->base + offset * 4);
184 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
185
186 return ret;
187 }
188
189 #ifdef CONFIG_DEBUG_FS
amd_gpio_dbg_show(struct seq_file * s,struct gpio_chip * gc)190 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
191 {
192 u32 pin_reg;
193 unsigned long flags;
194 unsigned int bank, i, pin_num;
195 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
196
197 char *level_trig;
198 char *active_level;
199 char *interrupt_enable;
200 char *interrupt_mask;
201 char *wake_cntrl0;
202 char *wake_cntrl1;
203 char *wake_cntrl2;
204 char *pin_sts;
205 char *pull_up_sel;
206 char *pull_up_enable;
207 char *pull_down_enable;
208 char *output_value;
209 char *output_enable;
210
211 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
212 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
213 seq_printf(s, "GPIO bank%d\t", bank);
214
215 switch (bank) {
216 case 0:
217 i = 0;
218 pin_num = AMD_GPIO_PINS_BANK0;
219 break;
220 case 1:
221 i = 64;
222 pin_num = AMD_GPIO_PINS_BANK1 + i;
223 break;
224 case 2:
225 i = 128;
226 pin_num = AMD_GPIO_PINS_BANK2 + i;
227 break;
228 case 3:
229 i = 192;
230 pin_num = AMD_GPIO_PINS_BANK3 + i;
231 break;
232 default:
233 /* Illegal bank number, ignore */
234 continue;
235 }
236 for (; i < pin_num; i++) {
237 seq_printf(s, "pin%d\t", i);
238 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
239 pin_reg = readl(gpio_dev->base + i * 4);
240 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
241
242 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
243 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
244 ACTIVE_LEVEL_MASK;
245 interrupt_enable = "interrupt is enabled|";
246
247 if (level == ACTIVE_LEVEL_HIGH)
248 active_level = "Active high|";
249 else if (level == ACTIVE_LEVEL_LOW)
250 active_level = "Active low|";
251 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
252 level == ACTIVE_LEVEL_BOTH)
253 active_level = "Active on both|";
254 else
255 active_level = "Unknown Active level|";
256
257 if (pin_reg & BIT(LEVEL_TRIG_OFF))
258 level_trig = "Level trigger|";
259 else
260 level_trig = "Edge trigger|";
261
262 } else {
263 interrupt_enable =
264 "interrupt is disabled|";
265 active_level = " ";
266 level_trig = " ";
267 }
268
269 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
270 interrupt_mask =
271 "interrupt is unmasked|";
272 else
273 interrupt_mask =
274 "interrupt is masked|";
275
276 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
277 wake_cntrl0 = "enable wakeup in S0i3 state|";
278 else
279 wake_cntrl0 = "disable wakeup in S0i3 state|";
280
281 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
282 wake_cntrl1 = "enable wakeup in S3 state|";
283 else
284 wake_cntrl1 = "disable wakeup in S3 state|";
285
286 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
287 wake_cntrl2 = "enable wakeup in S4/S5 state|";
288 else
289 wake_cntrl2 = "disable wakeup in S4/S5 state|";
290
291 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
292 pull_up_enable = "pull-up is enabled|";
293 if (pin_reg & BIT(PULL_UP_SEL_OFF))
294 pull_up_sel = "8k pull-up|";
295 else
296 pull_up_sel = "4k pull-up|";
297 } else {
298 pull_up_enable = "pull-up is disabled|";
299 pull_up_sel = " ";
300 }
301
302 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
303 pull_down_enable = "pull-down is enabled|";
304 else
305 pull_down_enable = "Pull-down is disabled|";
306
307 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
308 pin_sts = " ";
309 output_enable = "output is enabled|";
310 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
311 output_value = "output is high|";
312 else
313 output_value = "output is low|";
314 } else {
315 output_enable = "output is disabled|";
316 output_value = " ";
317
318 if (pin_reg & BIT(PIN_STS_OFF))
319 pin_sts = "input is high|";
320 else
321 pin_sts = "input is low|";
322 }
323
324 seq_printf(s, "%s %s %s %s %s %s\n"
325 " %s %s %s %s %s %s %s 0x%x\n",
326 level_trig, active_level, interrupt_enable,
327 interrupt_mask, wake_cntrl0, wake_cntrl1,
328 wake_cntrl2, pin_sts, pull_up_sel,
329 pull_up_enable, pull_down_enable,
330 output_value, output_enable, pin_reg);
331 }
332 }
333 }
334 #else
335 #define amd_gpio_dbg_show NULL
336 #endif
337
amd_gpio_irq_enable(struct irq_data * d)338 static void amd_gpio_irq_enable(struct irq_data *d)
339 {
340 u32 pin_reg;
341 unsigned long flags;
342 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
343 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
344
345 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
346 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
347 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
348 pin_reg |= BIT(INTERRUPT_MASK_OFF);
349 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
350 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
351 }
352
amd_gpio_irq_disable(struct irq_data * d)353 static void amd_gpio_irq_disable(struct irq_data *d)
354 {
355 u32 pin_reg;
356 unsigned long flags;
357 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
358 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
359
360 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
361 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
362 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
363 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
364 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
365 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
366 }
367
amd_gpio_irq_mask(struct irq_data * d)368 static void amd_gpio_irq_mask(struct irq_data *d)
369 {
370 u32 pin_reg;
371 unsigned long flags;
372 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
373 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
374
375 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
376 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
377 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
378 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
379 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
380 }
381
amd_gpio_irq_unmask(struct irq_data * d)382 static void amd_gpio_irq_unmask(struct irq_data *d)
383 {
384 u32 pin_reg;
385 unsigned long flags;
386 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
387 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
388
389 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
390 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
391 pin_reg |= BIT(INTERRUPT_MASK_OFF);
392 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
393 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
394 }
395
amd_gpio_irq_eoi(struct irq_data * d)396 static void amd_gpio_irq_eoi(struct irq_data *d)
397 {
398 u32 reg;
399 unsigned long flags;
400 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
401 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
402
403 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
404 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
405 reg |= EOI_MASK;
406 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
407 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
408 }
409
amd_gpio_irq_set_type(struct irq_data * d,unsigned int type)410 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
411 {
412 int ret = 0;
413 u32 pin_reg, pin_reg_irq_en, mask;
414 unsigned long flags, irq_flags;
415 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
416 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
417
418 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
419 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
420
421 /* Ignore the settings coming from the client and
422 * read the values from the ACPI tables
423 * while setting the trigger type
424 */
425
426 irq_flags = irq_get_trigger_type(d->irq);
427 if (irq_flags != IRQ_TYPE_NONE)
428 type = irq_flags;
429
430 switch (type & IRQ_TYPE_SENSE_MASK) {
431 case IRQ_TYPE_EDGE_RISING:
432 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
433 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
434 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
435 irq_set_handler_locked(d, handle_edge_irq);
436 break;
437
438 case IRQ_TYPE_EDGE_FALLING:
439 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
440 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
441 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
442 irq_set_handler_locked(d, handle_edge_irq);
443 break;
444
445 case IRQ_TYPE_EDGE_BOTH:
446 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
447 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
448 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
449 irq_set_handler_locked(d, handle_edge_irq);
450 break;
451
452 case IRQ_TYPE_LEVEL_HIGH:
453 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
454 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
455 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
456 irq_set_handler_locked(d, handle_level_irq);
457 break;
458
459 case IRQ_TYPE_LEVEL_LOW:
460 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
461 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
462 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
463 irq_set_handler_locked(d, handle_level_irq);
464 break;
465
466 case IRQ_TYPE_NONE:
467 break;
468
469 default:
470 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
471 ret = -EINVAL;
472 }
473
474 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
475 /*
476 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
477 * debounce registers of any GPIO will block wake/interrupt status
478 * generation for *all* GPIOs for a length of time that depends on
479 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
480 * INTERRUPT_ENABLE bit will read as 0.
481 *
482 * We temporarily enable irq for the GPIO whose configuration is
483 * changing, and then wait for it to read back as 1 to know when
484 * debounce has settled and then disable the irq again.
485 * We do this polling with the spinlock held to ensure other GPIO
486 * access routines do not read an incorrect value for the irq enable
487 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
488 * spurious irqs, and disable the irq again after polling.
489 */
490 mask = BIT(INTERRUPT_ENABLE_OFF);
491 pin_reg_irq_en = pin_reg;
492 pin_reg_irq_en |= mask;
493 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
494 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
495 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
496 continue;
497 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
498 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
499
500 return ret;
501 }
502
amd_irq_ack(struct irq_data * d)503 static void amd_irq_ack(struct irq_data *d)
504 {
505 /*
506 * based on HW design,there is no need to ack HW
507 * before handle current irq. But this routine is
508 * necessary for handle_edge_irq
509 */
510 }
511
512 static struct irq_chip amd_gpio_irqchip = {
513 .name = "amd_gpio",
514 .irq_ack = amd_irq_ack,
515 .irq_enable = amd_gpio_irq_enable,
516 .irq_disable = amd_gpio_irq_disable,
517 .irq_mask = amd_gpio_irq_mask,
518 .irq_unmask = amd_gpio_irq_unmask,
519 .irq_eoi = amd_gpio_irq_eoi,
520 .irq_set_type = amd_gpio_irq_set_type,
521 .flags = IRQCHIP_SKIP_SET_WAKE,
522 };
523
524 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
525
amd_gpio_irq_handler(int irq,void * dev_id)526 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
527 {
528 struct amd_gpio *gpio_dev = dev_id;
529 struct gpio_chip *gc = &gpio_dev->gc;
530 irqreturn_t ret = IRQ_NONE;
531 unsigned int i, irqnr;
532 unsigned long flags;
533 u32 __iomem *regs;
534 u32 regval;
535 u64 status, mask;
536
537 /* Read the wake status */
538 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
539 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
540 status <<= 32;
541 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
542 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
543
544 /* Bit 0-45 contain the relevant status bits */
545 status &= (1ULL << 46) - 1;
546 regs = gpio_dev->base;
547 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
548 if (!(status & mask))
549 continue;
550 status &= ~mask;
551
552 /* Each status bit covers four pins */
553 for (i = 0; i < 4; i++) {
554 regval = readl(regs + i);
555 if (!(regval & PIN_IRQ_PENDING) ||
556 !(regval & BIT(INTERRUPT_MASK_OFF)))
557 continue;
558 irq = irq_find_mapping(gc->irq.domain, irqnr + i);
559 if (irq != 0)
560 generic_handle_irq(irq);
561
562 /* Clear interrupt.
563 * We must read the pin register again, in case the
564 * value was changed while executing
565 * generic_handle_irq() above.
566 * If we didn't find a mapping for the interrupt,
567 * disable it in order to avoid a system hang caused
568 * by an interrupt storm.
569 */
570 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
571 regval = readl(regs + i);
572 if (irq == 0) {
573 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
574 dev_dbg(&gpio_dev->pdev->dev,
575 "Disabling spurious GPIO IRQ %d\n",
576 irqnr + i);
577 }
578 writel(regval, regs + i);
579 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
580 ret = IRQ_HANDLED;
581 }
582 }
583
584 /* Signal EOI to the GPIO unit */
585 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
586 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
587 regval |= EOI_MASK;
588 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
589 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
590
591 return ret;
592 }
593
amd_get_groups_count(struct pinctrl_dev * pctldev)594 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
595 {
596 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
597
598 return gpio_dev->ngroups;
599 }
600
amd_get_group_name(struct pinctrl_dev * pctldev,unsigned group)601 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
602 unsigned group)
603 {
604 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
605
606 return gpio_dev->groups[group].name;
607 }
608
amd_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)609 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
610 unsigned group,
611 const unsigned **pins,
612 unsigned *num_pins)
613 {
614 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
615
616 *pins = gpio_dev->groups[group].pins;
617 *num_pins = gpio_dev->groups[group].npins;
618 return 0;
619 }
620
621 static const struct pinctrl_ops amd_pinctrl_ops = {
622 .get_groups_count = amd_get_groups_count,
623 .get_group_name = amd_get_group_name,
624 .get_group_pins = amd_get_group_pins,
625 #ifdef CONFIG_OF
626 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
627 .dt_free_map = pinctrl_utils_free_map,
628 #endif
629 };
630
amd_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)631 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
632 unsigned int pin,
633 unsigned long *config)
634 {
635 u32 pin_reg;
636 unsigned arg;
637 unsigned long flags;
638 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
639 enum pin_config_param param = pinconf_to_config_param(*config);
640
641 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
642 pin_reg = readl(gpio_dev->base + pin*4);
643 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
644 switch (param) {
645 case PIN_CONFIG_INPUT_DEBOUNCE:
646 arg = pin_reg & DB_TMR_OUT_MASK;
647 break;
648
649 case PIN_CONFIG_BIAS_PULL_DOWN:
650 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
651 break;
652
653 case PIN_CONFIG_BIAS_PULL_UP:
654 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
655 break;
656
657 case PIN_CONFIG_DRIVE_STRENGTH:
658 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
659 break;
660
661 default:
662 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
663 param);
664 return -ENOTSUPP;
665 }
666
667 *config = pinconf_to_config_packed(param, arg);
668
669 return 0;
670 }
671
amd_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)672 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
673 unsigned long *configs, unsigned int num_configs)
674 {
675 int i;
676 u32 arg;
677 int ret = 0;
678 u32 pin_reg;
679 unsigned long flags;
680 enum pin_config_param param;
681 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
682
683 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
684 for (i = 0; i < num_configs; i++) {
685 param = pinconf_to_config_param(configs[i]);
686 arg = pinconf_to_config_argument(configs[i]);
687 pin_reg = readl(gpio_dev->base + pin*4);
688
689 switch (param) {
690 case PIN_CONFIG_INPUT_DEBOUNCE:
691 pin_reg &= ~DB_TMR_OUT_MASK;
692 pin_reg |= arg & DB_TMR_OUT_MASK;
693 break;
694
695 case PIN_CONFIG_BIAS_PULL_DOWN:
696 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
697 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
698 break;
699
700 case PIN_CONFIG_BIAS_PULL_UP:
701 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
702 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
703 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
704 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
705 break;
706
707 case PIN_CONFIG_DRIVE_STRENGTH:
708 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
709 << DRV_STRENGTH_SEL_OFF);
710 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
711 << DRV_STRENGTH_SEL_OFF;
712 break;
713
714 default:
715 dev_dbg(&gpio_dev->pdev->dev,
716 "Invalid config param %04x\n", param);
717 ret = -ENOTSUPP;
718 }
719
720 writel(pin_reg, gpio_dev->base + pin*4);
721 }
722 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
723
724 return ret;
725 }
726
amd_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)727 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
728 unsigned int group,
729 unsigned long *config)
730 {
731 const unsigned *pins;
732 unsigned npins;
733 int ret;
734
735 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
736 if (ret)
737 return ret;
738
739 if (amd_pinconf_get(pctldev, pins[0], config))
740 return -ENOTSUPP;
741
742 return 0;
743 }
744
amd_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)745 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
746 unsigned group, unsigned long *configs,
747 unsigned num_configs)
748 {
749 const unsigned *pins;
750 unsigned npins;
751 int i, ret;
752
753 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
754 if (ret)
755 return ret;
756 for (i = 0; i < npins; i++) {
757 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
758 return -ENOTSUPP;
759 }
760 return 0;
761 }
762
amd_gpio_set_config(struct gpio_chip * gc,unsigned int pin,unsigned long config)763 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
764 unsigned long config)
765 {
766 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
767
768 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
769 u32 debounce = pinconf_to_config_argument(config);
770
771 return amd_gpio_set_debounce(gc, pin, debounce);
772 }
773
774 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
775 }
776
777 static const struct pinconf_ops amd_pinconf_ops = {
778 .pin_config_get = amd_pinconf_get,
779 .pin_config_set = amd_pinconf_set,
780 .pin_config_group_get = amd_pinconf_group_get,
781 .pin_config_group_set = amd_pinconf_group_set,
782 };
783
amd_gpio_irq_init(struct amd_gpio * gpio_dev)784 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
785 {
786 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
787 unsigned long flags;
788 u32 pin_reg, mask;
789 int i;
790
791 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
792 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
793 BIT(WAKE_CNTRL_OFF_S4);
794
795 for (i = 0; i < desc->npins; i++) {
796 int pin = desc->pins[i].number;
797 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
798
799 if (!pd)
800 continue;
801
802 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
803
804 pin_reg = readl(gpio_dev->base + pin * 4);
805 pin_reg &= ~mask;
806 writel(pin_reg, gpio_dev->base + pin * 4);
807
808 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
809 }
810 }
811
812 #ifdef CONFIG_PM_SLEEP
amd_gpio_should_save(struct amd_gpio * gpio_dev,unsigned int pin)813 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
814 {
815 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
816
817 if (!pd)
818 return false;
819
820 /*
821 * Only restore the pin if it is actually in use by the kernel (or
822 * by userspace).
823 */
824 if (pd->mux_owner || pd->gpio_owner ||
825 gpiochip_line_is_irq(&gpio_dev->gc, pin))
826 return true;
827
828 return false;
829 }
830
amd_gpio_suspend(struct device * dev)831 static int amd_gpio_suspend(struct device *dev)
832 {
833 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
834 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
835 unsigned long flags;
836 int i;
837
838 for (i = 0; i < desc->npins; i++) {
839 int pin = desc->pins[i].number;
840
841 if (!amd_gpio_should_save(gpio_dev, pin))
842 continue;
843
844 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
845 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
846 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
847 }
848
849 return 0;
850 }
851
amd_gpio_resume(struct device * dev)852 static int amd_gpio_resume(struct device *dev)
853 {
854 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
855 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
856 unsigned long flags;
857 int i;
858
859 for (i = 0; i < desc->npins; i++) {
860 int pin = desc->pins[i].number;
861
862 if (!amd_gpio_should_save(gpio_dev, pin))
863 continue;
864
865 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
866 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
867 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
868 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
869 }
870
871 return 0;
872 }
873
874 static const struct dev_pm_ops amd_gpio_pm_ops = {
875 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
876 amd_gpio_resume)
877 };
878 #endif
879
880 static struct pinctrl_desc amd_pinctrl_desc = {
881 .pins = kerncz_pins,
882 .npins = ARRAY_SIZE(kerncz_pins),
883 .pctlops = &amd_pinctrl_ops,
884 .confops = &amd_pinconf_ops,
885 .owner = THIS_MODULE,
886 };
887
amd_gpio_probe(struct platform_device * pdev)888 static int amd_gpio_probe(struct platform_device *pdev)
889 {
890 int ret = 0;
891 int irq_base;
892 struct resource *res;
893 struct amd_gpio *gpio_dev;
894 struct gpio_irq_chip *girq;
895
896 gpio_dev = devm_kzalloc(&pdev->dev,
897 sizeof(struct amd_gpio), GFP_KERNEL);
898 if (!gpio_dev)
899 return -ENOMEM;
900
901 raw_spin_lock_init(&gpio_dev->lock);
902
903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
904 if (!res) {
905 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
906 return -EINVAL;
907 }
908
909 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
910 resource_size(res));
911 if (!gpio_dev->base)
912 return -ENOMEM;
913
914 irq_base = platform_get_irq(pdev, 0);
915 if (irq_base < 0)
916 return irq_base;
917
918 #ifdef CONFIG_PM_SLEEP
919 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
920 sizeof(*gpio_dev->saved_regs),
921 GFP_KERNEL);
922 if (!gpio_dev->saved_regs)
923 return -ENOMEM;
924 #endif
925
926 gpio_dev->pdev = pdev;
927 gpio_dev->gc.get_direction = amd_gpio_get_direction;
928 gpio_dev->gc.direction_input = amd_gpio_direction_input;
929 gpio_dev->gc.direction_output = amd_gpio_direction_output;
930 gpio_dev->gc.get = amd_gpio_get_value;
931 gpio_dev->gc.set = amd_gpio_set_value;
932 gpio_dev->gc.set_config = amd_gpio_set_config;
933 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
934
935 gpio_dev->gc.base = -1;
936 gpio_dev->gc.label = pdev->name;
937 gpio_dev->gc.owner = THIS_MODULE;
938 gpio_dev->gc.parent = &pdev->dev;
939 gpio_dev->gc.ngpio = resource_size(res) / 4;
940 #if defined(CONFIG_OF_GPIO)
941 gpio_dev->gc.of_node = pdev->dev.of_node;
942 #endif
943
944 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
945 gpio_dev->groups = kerncz_groups;
946 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
947
948 amd_pinctrl_desc.name = dev_name(&pdev->dev);
949 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
950 gpio_dev);
951 if (IS_ERR(gpio_dev->pctrl)) {
952 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
953 return PTR_ERR(gpio_dev->pctrl);
954 }
955
956 /* Disable and mask interrupts */
957 amd_gpio_irq_init(gpio_dev);
958
959 girq = &gpio_dev->gc.irq;
960 girq->chip = &amd_gpio_irqchip;
961 /* This will let us handle the parent IRQ in the driver */
962 girq->parent_handler = NULL;
963 girq->num_parents = 0;
964 girq->parents = NULL;
965 girq->default_type = IRQ_TYPE_NONE;
966 girq->handler = handle_simple_irq;
967
968 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
969 if (ret)
970 return ret;
971
972 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
973 0, 0, gpio_dev->gc.ngpio);
974 if (ret) {
975 dev_err(&pdev->dev, "Failed to add pin range\n");
976 goto out2;
977 }
978
979 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
980 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
981 if (ret)
982 goto out2;
983
984 platform_set_drvdata(pdev, gpio_dev);
985
986 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
987 return ret;
988
989 out2:
990 gpiochip_remove(&gpio_dev->gc);
991
992 return ret;
993 }
994
amd_gpio_remove(struct platform_device * pdev)995 static int amd_gpio_remove(struct platform_device *pdev)
996 {
997 struct amd_gpio *gpio_dev;
998
999 gpio_dev = platform_get_drvdata(pdev);
1000
1001 gpiochip_remove(&gpio_dev->gc);
1002
1003 return 0;
1004 }
1005
1006 static const struct acpi_device_id amd_gpio_acpi_match[] = {
1007 { "AMD0030", 0 },
1008 { "AMDI0030", 0},
1009 { "AMDI0031", 0},
1010 { },
1011 };
1012 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1013
1014 static struct platform_driver amd_gpio_driver = {
1015 .driver = {
1016 .name = "amd_gpio",
1017 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1018 #ifdef CONFIG_PM_SLEEP
1019 .pm = &amd_gpio_pm_ops,
1020 #endif
1021 },
1022 .probe = amd_gpio_probe,
1023 .remove = amd_gpio_remove,
1024 };
1025
1026 module_platform_driver(amd_gpio_driver);
1027
1028 MODULE_LICENSE("GPL v2");
1029 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1030 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
1031