1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 Ken Xue <Ken.Xue@amd.com> 6 * Jeff Wu <Jeff.Wu@amd.com> 7 */ 8 9 #ifndef _PINCTRL_AMD_H 10 #define _PINCTRL_AMD_H 11 12 #define AMD_GPIO_PINS_PER_BANK 64 13 14 #define AMD_GPIO_PINS_BANK0 63 15 #define AMD_GPIO_PINS_BANK1 64 16 #define AMD_GPIO_PINS_BANK2 56 17 #define AMD_GPIO_PINS_BANK3 32 18 19 #define WAKE_INT_MASTER_REG 0xfc 20 #define INTERNAL_GPIO0_DEBOUNCE (1 << 15) 21 #define EOI_MASK (1 << 29) 22 23 #define WAKE_INT_STATUS_REG0 0x2f8 24 #define WAKE_INT_STATUS_REG1 0x2fc 25 26 #define DB_TMR_OUT_OFF 0 27 #define DB_TMR_OUT_UNIT_OFF 4 28 #define DB_CNTRL_OFF 5 29 #define DB_TMR_LARGE_OFF 7 30 #define LEVEL_TRIG_OFF 8 31 #define ACTIVE_LEVEL_OFF 9 32 #define INTERRUPT_ENABLE_OFF 11 33 #define INTERRUPT_MASK_OFF 12 34 #define WAKE_CNTRL_OFF_S0I3 13 35 #define WAKE_CNTRL_OFF_S3 14 36 #define WAKE_CNTRL_OFF_S4 15 37 #define PIN_STS_OFF 16 38 #define DRV_STRENGTH_SEL_OFF 17 39 #define PULL_UP_SEL_OFF 19 40 #define PULL_UP_ENABLE_OFF 20 41 #define PULL_DOWN_ENABLE_OFF 21 42 #define OUTPUT_VALUE_OFF 22 43 #define OUTPUT_ENABLE_OFF 23 44 #define SW_CNTRL_IN_OFF 24 45 #define SW_CNTRL_EN_OFF 25 46 #define INTERRUPT_STS_OFF 28 47 #define WAKE_STS_OFF 29 48 49 #define DB_TMR_OUT_MASK 0xFUL 50 #define DB_CNTRl_MASK 0x3UL 51 #define ACTIVE_LEVEL_MASK 0x3UL 52 #define DRV_STRENGTH_SEL_MASK 0x3UL 53 54 #define ACTIVE_LEVEL_HIGH 0x0UL 55 #define ACTIVE_LEVEL_LOW 0x1UL 56 #define ACTIVE_LEVEL_BOTH 0x2UL 57 58 #define DB_TYPE_NO_DEBOUNCE 0x0UL 59 #define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL 60 #define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL 61 #define DB_TYPE_REMOVE_GLITCH 0x3UL 62 63 #define EDGE_TRAGGER 0x0UL 64 #define LEVEL_TRIGGER 0x1UL 65 66 #define ACTIVE_HIGH 0x0UL 67 #define ACTIVE_LOW 0x1UL 68 #define BOTH_EADGE 0x2UL 69 70 #define ENABLE_INTERRUPT 0x1UL 71 #define DISABLE_INTERRUPT 0x0UL 72 73 #define ENABLE_INTERRUPT_MASK 0x0UL 74 #define DISABLE_INTERRUPT_MASK 0x1UL 75 76 #define CLR_INTR_STAT 0x1UL 77 78 struct amd_pingroup { 79 const char *name; 80 const unsigned *pins; 81 unsigned npins; 82 }; 83 84 struct amd_function { 85 const char *name; 86 const char * const *groups; 87 unsigned ngroups; 88 }; 89 90 struct amd_gpio { 91 raw_spinlock_t lock; 92 void __iomem *base; 93 94 const struct amd_pingroup *groups; 95 u32 ngroups; 96 struct pinctrl_dev *pctrl; 97 struct gpio_chip gc; 98 unsigned int hwbank_num; 99 struct resource *res; 100 struct platform_device *pdev; 101 u32 *saved_regs; 102 }; 103 104 /* KERNCZ configuration*/ 105 static const struct pinctrl_pin_desc kerncz_pins[] = { 106 PINCTRL_PIN(0, "GPIO_0"), 107 PINCTRL_PIN(1, "GPIO_1"), 108 PINCTRL_PIN(2, "GPIO_2"), 109 PINCTRL_PIN(3, "GPIO_3"), 110 PINCTRL_PIN(4, "GPIO_4"), 111 PINCTRL_PIN(5, "GPIO_5"), 112 PINCTRL_PIN(6, "GPIO_6"), 113 PINCTRL_PIN(7, "GPIO_7"), 114 PINCTRL_PIN(8, "GPIO_8"), 115 PINCTRL_PIN(9, "GPIO_9"), 116 PINCTRL_PIN(10, "GPIO_10"), 117 PINCTRL_PIN(11, "GPIO_11"), 118 PINCTRL_PIN(12, "GPIO_12"), 119 PINCTRL_PIN(13, "GPIO_13"), 120 PINCTRL_PIN(14, "GPIO_14"), 121 PINCTRL_PIN(15, "GPIO_15"), 122 PINCTRL_PIN(16, "GPIO_16"), 123 PINCTRL_PIN(17, "GPIO_17"), 124 PINCTRL_PIN(18, "GPIO_18"), 125 PINCTRL_PIN(19, "GPIO_19"), 126 PINCTRL_PIN(20, "GPIO_20"), 127 PINCTRL_PIN(23, "GPIO_23"), 128 PINCTRL_PIN(24, "GPIO_24"), 129 PINCTRL_PIN(25, "GPIO_25"), 130 PINCTRL_PIN(26, "GPIO_26"), 131 PINCTRL_PIN(39, "GPIO_39"), 132 PINCTRL_PIN(40, "GPIO_40"), 133 PINCTRL_PIN(43, "GPIO_42"), 134 PINCTRL_PIN(46, "GPIO_46"), 135 PINCTRL_PIN(47, "GPIO_47"), 136 PINCTRL_PIN(48, "GPIO_48"), 137 PINCTRL_PIN(49, "GPIO_49"), 138 PINCTRL_PIN(50, "GPIO_50"), 139 PINCTRL_PIN(51, "GPIO_51"), 140 PINCTRL_PIN(52, "GPIO_52"), 141 PINCTRL_PIN(53, "GPIO_53"), 142 PINCTRL_PIN(54, "GPIO_54"), 143 PINCTRL_PIN(55, "GPIO_55"), 144 PINCTRL_PIN(56, "GPIO_56"), 145 PINCTRL_PIN(57, "GPIO_57"), 146 PINCTRL_PIN(58, "GPIO_58"), 147 PINCTRL_PIN(59, "GPIO_59"), 148 PINCTRL_PIN(60, "GPIO_60"), 149 PINCTRL_PIN(61, "GPIO_61"), 150 PINCTRL_PIN(62, "GPIO_62"), 151 PINCTRL_PIN(64, "GPIO_64"), 152 PINCTRL_PIN(65, "GPIO_65"), 153 PINCTRL_PIN(66, "GPIO_66"), 154 PINCTRL_PIN(68, "GPIO_68"), 155 PINCTRL_PIN(69, "GPIO_69"), 156 PINCTRL_PIN(70, "GPIO_70"), 157 PINCTRL_PIN(71, "GPIO_71"), 158 PINCTRL_PIN(72, "GPIO_72"), 159 PINCTRL_PIN(74, "GPIO_74"), 160 PINCTRL_PIN(75, "GPIO_75"), 161 PINCTRL_PIN(76, "GPIO_76"), 162 PINCTRL_PIN(84, "GPIO_84"), 163 PINCTRL_PIN(85, "GPIO_85"), 164 PINCTRL_PIN(86, "GPIO_86"), 165 PINCTRL_PIN(87, "GPIO_87"), 166 PINCTRL_PIN(88, "GPIO_88"), 167 PINCTRL_PIN(89, "GPIO_89"), 168 PINCTRL_PIN(90, "GPIO_90"), 169 PINCTRL_PIN(91, "GPIO_91"), 170 PINCTRL_PIN(92, "GPIO_92"), 171 PINCTRL_PIN(93, "GPIO_93"), 172 PINCTRL_PIN(95, "GPIO_95"), 173 PINCTRL_PIN(96, "GPIO_96"), 174 PINCTRL_PIN(97, "GPIO_97"), 175 PINCTRL_PIN(98, "GPIO_98"), 176 PINCTRL_PIN(99, "GPIO_99"), 177 PINCTRL_PIN(100, "GPIO_100"), 178 PINCTRL_PIN(101, "GPIO_101"), 179 PINCTRL_PIN(102, "GPIO_102"), 180 PINCTRL_PIN(113, "GPIO_113"), 181 PINCTRL_PIN(114, "GPIO_114"), 182 PINCTRL_PIN(115, "GPIO_115"), 183 PINCTRL_PIN(116, "GPIO_116"), 184 PINCTRL_PIN(117, "GPIO_117"), 185 PINCTRL_PIN(118, "GPIO_118"), 186 PINCTRL_PIN(119, "GPIO_119"), 187 PINCTRL_PIN(120, "GPIO_120"), 188 PINCTRL_PIN(121, "GPIO_121"), 189 PINCTRL_PIN(122, "GPIO_122"), 190 PINCTRL_PIN(126, "GPIO_126"), 191 PINCTRL_PIN(129, "GPIO_129"), 192 PINCTRL_PIN(130, "GPIO_130"), 193 PINCTRL_PIN(131, "GPIO_131"), 194 PINCTRL_PIN(132, "GPIO_132"), 195 PINCTRL_PIN(133, "GPIO_133"), 196 PINCTRL_PIN(135, "GPIO_135"), 197 PINCTRL_PIN(136, "GPIO_136"), 198 PINCTRL_PIN(137, "GPIO_137"), 199 PINCTRL_PIN(138, "GPIO_138"), 200 PINCTRL_PIN(139, "GPIO_139"), 201 PINCTRL_PIN(140, "GPIO_140"), 202 PINCTRL_PIN(141, "GPIO_141"), 203 PINCTRL_PIN(142, "GPIO_142"), 204 PINCTRL_PIN(143, "GPIO_143"), 205 PINCTRL_PIN(144, "GPIO_144"), 206 PINCTRL_PIN(145, "GPIO_145"), 207 PINCTRL_PIN(146, "GPIO_146"), 208 PINCTRL_PIN(147, "GPIO_147"), 209 PINCTRL_PIN(148, "GPIO_148"), 210 PINCTRL_PIN(166, "GPIO_166"), 211 PINCTRL_PIN(167, "GPIO_167"), 212 PINCTRL_PIN(168, "GPIO_168"), 213 PINCTRL_PIN(169, "GPIO_169"), 214 PINCTRL_PIN(170, "GPIO_170"), 215 PINCTRL_PIN(171, "GPIO_171"), 216 PINCTRL_PIN(172, "GPIO_172"), 217 PINCTRL_PIN(173, "GPIO_173"), 218 PINCTRL_PIN(174, "GPIO_174"), 219 PINCTRL_PIN(175, "GPIO_175"), 220 PINCTRL_PIN(176, "GPIO_176"), 221 PINCTRL_PIN(177, "GPIO_177"), 222 }; 223 224 static const unsigned i2c0_pins[] = {145, 146}; 225 static const unsigned i2c1_pins[] = {147, 148}; 226 static const unsigned i2c2_pins[] = {113, 114}; 227 static const unsigned i2c3_pins[] = {19, 20}; 228 229 static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; 230 static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; 231 232 static const struct amd_pingroup kerncz_groups[] = { 233 { 234 .name = "i2c0", 235 .pins = i2c0_pins, 236 .npins = 2, 237 }, 238 { 239 .name = "i2c1", 240 .pins = i2c1_pins, 241 .npins = 2, 242 }, 243 { 244 .name = "i2c2", 245 .pins = i2c2_pins, 246 .npins = 2, 247 }, 248 { 249 .name = "i2c3", 250 .pins = i2c3_pins, 251 .npins = 2, 252 }, 253 { 254 .name = "uart0", 255 .pins = uart0_pins, 256 .npins = 5, 257 }, 258 { 259 .name = "uart1", 260 .pins = uart1_pins, 261 .npins = 5, 262 }, 263 }; 264 265 #endif 266