1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl driver for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * http://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/io.h>
21 #include <linux/bitops.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/clk.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
35
36 #include "core.h"
37 #include "pinconf.h"
38
39 /* GPIO control registers */
40 #define GPIO_SWPORT_DR 0x00
41 #define GPIO_SWPORT_DDR 0x04
42 #define GPIO_INTEN 0x30
43 #define GPIO_INTMASK 0x34
44 #define GPIO_INTTYPE_LEVEL 0x38
45 #define GPIO_INT_POLARITY 0x3c
46 #define GPIO_INT_STATUS 0x40
47 #define GPIO_INT_RAWSTATUS 0x44
48 #define GPIO_DEBOUNCE 0x48
49 #define GPIO_PORTS_EOI 0x4c
50 #define GPIO_EXT_PORT 0x50
51 #define GPIO_LS_SYNC 0x60
52
53 enum rockchip_pinctrl_type {
54 PX30,
55 RV1108,
56 RK2928,
57 RK3066B,
58 RK3128,
59 RK3188,
60 RK3288,
61 RK3368,
62 RK3399,
63 };
64
65 /*
66 * Encode variants of iomux registers into a type variable
67 */
68 #define IOMUX_GPIO_ONLY BIT(0)
69 #define IOMUX_WIDTH_4BIT BIT(1)
70 #define IOMUX_SOURCE_PMU BIT(2)
71 #define IOMUX_UNROUTED BIT(3)
72 #define IOMUX_WIDTH_3BIT BIT(4)
73
74 /**
75 * struct rockchip_iomux
76 * @type: iomux variant using IOMUX_* constants
77 * @offset: if initialized to -1 it will be autocalculated, by specifying
78 * an initial offset value the relevant source offset can be reset
79 * to a new value for autocalculating the following iomux registers.
80 */
81 struct rockchip_iomux {
82 int type;
83 int offset;
84 };
85
86 /*
87 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
88 */
89 enum rockchip_pin_drv_type {
90 DRV_TYPE_IO_DEFAULT = 0,
91 DRV_TYPE_IO_1V8_OR_3V0,
92 DRV_TYPE_IO_1V8_ONLY,
93 DRV_TYPE_IO_1V8_3V0_AUTO,
94 DRV_TYPE_IO_3V3_ONLY,
95 DRV_TYPE_MAX
96 };
97
98 /*
99 * enum type index corresponding to rockchip_pull_list arrays index.
100 */
101 enum rockchip_pin_pull_type {
102 PULL_TYPE_IO_DEFAULT = 0,
103 PULL_TYPE_IO_1V8_ONLY,
104 PULL_TYPE_MAX
105 };
106
107 /**
108 * struct rockchip_drv
109 * @drv_type: drive strength variant using rockchip_perpin_drv_type
110 * @offset: if initialized to -1 it will be autocalculated, by specifying
111 * an initial offset value the relevant source offset can be reset
112 * to a new value for autocalculating the following drive strength
113 * registers. if used chips own cal_drv func instead to calculate
114 * registers offset, the variant could be ignored.
115 */
116 struct rockchip_drv {
117 enum rockchip_pin_drv_type drv_type;
118 int offset;
119 };
120
121 /**
122 * struct rockchip_pin_bank
123 * @reg_base: register base of the gpio bank
124 * @regmap_pull: optional separate register for additional pull settings
125 * @clk: clock of the gpio bank
126 * @irq: interrupt of the gpio bank
127 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
128 * @pin_base: first pin number
129 * @nr_pins: number of pins in this bank
130 * @name: name of the bank
131 * @bank_num: number of the bank, to account for holes
132 * @iomux: array describing the 4 iomux sources of the bank
133 * @drv: array describing the 4 drive strength sources of the bank
134 * @pull_type: array describing the 4 pull type sources of the bank
135 * @valid: is all necessary information present
136 * @of_node: dt node of this bank
137 * @drvdata: common pinctrl basedata
138 * @domain: irqdomain of the gpio bank
139 * @gpio_chip: gpiolib chip
140 * @grange: gpio range
141 * @slock: spinlock for the gpio bank
142 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
143 * @recalced_mask: bit mask to indicate a need to recalulate the mask
144 * @route_mask: bits describing the routing pins of per bank
145 */
146 struct rockchip_pin_bank {
147 void __iomem *reg_base;
148 struct regmap *regmap_pull;
149 struct clk *clk;
150 int irq;
151 u32 saved_masks;
152 u32 pin_base;
153 u8 nr_pins;
154 char *name;
155 u8 bank_num;
156 struct rockchip_iomux iomux[4];
157 struct rockchip_drv drv[4];
158 enum rockchip_pin_pull_type pull_type[4];
159 bool valid;
160 struct device_node *of_node;
161 struct rockchip_pinctrl *drvdata;
162 struct irq_domain *domain;
163 struct gpio_chip gpio_chip;
164 struct pinctrl_gpio_range grange;
165 raw_spinlock_t slock;
166 u32 toggle_edge_mode;
167 u32 recalced_mask;
168 u32 route_mask;
169 };
170
171 #define PIN_BANK(id, pins, label) \
172 { \
173 .bank_num = id, \
174 .nr_pins = pins, \
175 .name = label, \
176 .iomux = { \
177 { .offset = -1 }, \
178 { .offset = -1 }, \
179 { .offset = -1 }, \
180 { .offset = -1 }, \
181 }, \
182 }
183
184 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
185 { \
186 .bank_num = id, \
187 .nr_pins = pins, \
188 .name = label, \
189 .iomux = { \
190 { .type = iom0, .offset = -1 }, \
191 { .type = iom1, .offset = -1 }, \
192 { .type = iom2, .offset = -1 }, \
193 { .type = iom3, .offset = -1 }, \
194 }, \
195 }
196
197 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
198 { \
199 .bank_num = id, \
200 .nr_pins = pins, \
201 .name = label, \
202 .iomux = { \
203 { .offset = -1 }, \
204 { .offset = -1 }, \
205 { .offset = -1 }, \
206 { .offset = -1 }, \
207 }, \
208 .drv = { \
209 { .drv_type = type0, .offset = -1 }, \
210 { .drv_type = type1, .offset = -1 }, \
211 { .drv_type = type2, .offset = -1 }, \
212 { .drv_type = type3, .offset = -1 }, \
213 }, \
214 }
215
216 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
217 drv2, drv3, pull0, pull1, \
218 pull2, pull3) \
219 { \
220 .bank_num = id, \
221 .nr_pins = pins, \
222 .name = label, \
223 .iomux = { \
224 { .offset = -1 }, \
225 { .offset = -1 }, \
226 { .offset = -1 }, \
227 { .offset = -1 }, \
228 }, \
229 .drv = { \
230 { .drv_type = drv0, .offset = -1 }, \
231 { .drv_type = drv1, .offset = -1 }, \
232 { .drv_type = drv2, .offset = -1 }, \
233 { .drv_type = drv3, .offset = -1 }, \
234 }, \
235 .pull_type[0] = pull0, \
236 .pull_type[1] = pull1, \
237 .pull_type[2] = pull2, \
238 .pull_type[3] = pull3, \
239 }
240
241 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
242 iom2, iom3, drv0, drv1, drv2, \
243 drv3, offset0, offset1, \
244 offset2, offset3) \
245 { \
246 .bank_num = id, \
247 .nr_pins = pins, \
248 .name = label, \
249 .iomux = { \
250 { .type = iom0, .offset = -1 }, \
251 { .type = iom1, .offset = -1 }, \
252 { .type = iom2, .offset = -1 }, \
253 { .type = iom3, .offset = -1 }, \
254 }, \
255 .drv = { \
256 { .drv_type = drv0, .offset = offset0 }, \
257 { .drv_type = drv1, .offset = offset1 }, \
258 { .drv_type = drv2, .offset = offset2 }, \
259 { .drv_type = drv3, .offset = offset3 }, \
260 }, \
261 }
262
263 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
264 label, iom0, iom1, iom2, \
265 iom3, drv0, drv1, drv2, \
266 drv3, offset0, offset1, \
267 offset2, offset3, pull0, \
268 pull1, pull2, pull3) \
269 { \
270 .bank_num = id, \
271 .nr_pins = pins, \
272 .name = label, \
273 .iomux = { \
274 { .type = iom0, .offset = -1 }, \
275 { .type = iom1, .offset = -1 }, \
276 { .type = iom2, .offset = -1 }, \
277 { .type = iom3, .offset = -1 }, \
278 }, \
279 .drv = { \
280 { .drv_type = drv0, .offset = offset0 }, \
281 { .drv_type = drv1, .offset = offset1 }, \
282 { .drv_type = drv2, .offset = offset2 }, \
283 { .drv_type = drv3, .offset = offset3 }, \
284 }, \
285 .pull_type[0] = pull0, \
286 .pull_type[1] = pull1, \
287 .pull_type[2] = pull2, \
288 .pull_type[3] = pull3, \
289 }
290
291 /**
292 * struct rockchip_mux_recalced_data: represent a pin iomux data.
293 * @num: bank number.
294 * @pin: pin number.
295 * @bit: index at register.
296 * @reg: register offset.
297 * @mask: mask bit
298 */
299 struct rockchip_mux_recalced_data {
300 u8 num;
301 u8 pin;
302 u32 reg;
303 u8 bit;
304 u8 mask;
305 };
306
307 enum rockchip_mux_route_location {
308 ROCKCHIP_ROUTE_SAME = 0,
309 ROCKCHIP_ROUTE_PMU,
310 ROCKCHIP_ROUTE_GRF,
311 };
312
313 /**
314 * struct rockchip_mux_recalced_data: represent a pin iomux data.
315 * @bank_num: bank number.
316 * @pin: index at register or used to calc index.
317 * @func: the min pin.
318 * @route_location: the mux route location (same, pmu, grf).
319 * @route_offset: the max pin.
320 * @route_val: the register offset.
321 */
322 struct rockchip_mux_route_data {
323 u8 bank_num;
324 u8 pin;
325 u8 func;
326 enum rockchip_mux_route_location route_location;
327 u32 route_offset;
328 u32 route_val;
329 };
330
331 struct rockchip_pin_ctrl {
332 struct rockchip_pin_bank *pin_banks;
333 u32 nr_banks;
334 u32 nr_pins;
335 char *label;
336 enum rockchip_pinctrl_type type;
337 int grf_mux_offset;
338 int pmu_mux_offset;
339 int grf_drv_offset;
340 int pmu_drv_offset;
341 struct rockchip_mux_recalced_data *iomux_recalced;
342 u32 niomux_recalced;
343 struct rockchip_mux_route_data *iomux_routes;
344 u32 niomux_routes;
345
346 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
347 int pin_num, struct regmap **regmap,
348 int *reg, u8 *bit);
349 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
350 int pin_num, struct regmap **regmap,
351 int *reg, u8 *bit);
352 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
353 int pin_num, struct regmap **regmap,
354 int *reg, u8 *bit);
355 };
356
357 struct rockchip_pin_config {
358 unsigned int func;
359 unsigned long *configs;
360 unsigned int nconfigs;
361 };
362
363 /**
364 * struct rockchip_pin_group: represent group of pins of a pinmux function.
365 * @name: name of the pin group, used to lookup the group.
366 * @pins: the pins included in this group.
367 * @npins: number of pins included in this group.
368 * @data: local pin configuration
369 */
370 struct rockchip_pin_group {
371 const char *name;
372 unsigned int npins;
373 unsigned int *pins;
374 struct rockchip_pin_config *data;
375 };
376
377 /**
378 * struct rockchip_pmx_func: represent a pin function.
379 * @name: name of the pin function, used to lookup the function.
380 * @groups: one or more names of pin groups that provide this function.
381 * @ngroups: number of groups included in @groups.
382 */
383 struct rockchip_pmx_func {
384 const char *name;
385 const char **groups;
386 u8 ngroups;
387 };
388
389 struct rockchip_pinctrl {
390 struct regmap *regmap_base;
391 int reg_size;
392 struct regmap *regmap_pull;
393 struct regmap *regmap_pmu;
394 struct device *dev;
395 struct rockchip_pin_ctrl *ctrl;
396 struct pinctrl_desc pctl;
397 struct pinctrl_dev *pctl_dev;
398 struct rockchip_pin_group *groups;
399 unsigned int ngroups;
400 struct rockchip_pmx_func *functions;
401 unsigned int nfunctions;
402 };
403
404 static struct regmap_config rockchip_regmap_config = {
405 .reg_bits = 32,
406 .val_bits = 32,
407 .reg_stride = 4,
408 };
409
pinctrl_name_to_group(const struct rockchip_pinctrl * info,const char * name)410 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
411 const struct rockchip_pinctrl *info,
412 const char *name)
413 {
414 int i;
415
416 for (i = 0; i < info->ngroups; i++) {
417 if (!strcmp(info->groups[i].name, name))
418 return &info->groups[i];
419 }
420
421 return NULL;
422 }
423
424 /*
425 * given a pin number that is local to a pin controller, find out the pin bank
426 * and the register base of the pin bank.
427 */
pin_to_bank(struct rockchip_pinctrl * info,unsigned pin)428 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
429 unsigned pin)
430 {
431 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
432
433 while (pin >= (b->pin_base + b->nr_pins))
434 b++;
435
436 return b;
437 }
438
bank_num_to_bank(struct rockchip_pinctrl * info,unsigned num)439 static struct rockchip_pin_bank *bank_num_to_bank(
440 struct rockchip_pinctrl *info,
441 unsigned num)
442 {
443 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
444 int i;
445
446 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
447 if (b->bank_num == num)
448 return b;
449 }
450
451 return ERR_PTR(-EINVAL);
452 }
453
454 /*
455 * Pinctrl_ops handling
456 */
457
rockchip_get_groups_count(struct pinctrl_dev * pctldev)458 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
459 {
460 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
461
462 return info->ngroups;
463 }
464
rockchip_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)465 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
466 unsigned selector)
467 {
468 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
469
470 return info->groups[selector].name;
471 }
472
rockchip_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)473 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
474 unsigned selector, const unsigned **pins,
475 unsigned *npins)
476 {
477 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
478
479 if (selector >= info->ngroups)
480 return -EINVAL;
481
482 *pins = info->groups[selector].pins;
483 *npins = info->groups[selector].npins;
484
485 return 0;
486 }
487
rockchip_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)488 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
489 struct device_node *np,
490 struct pinctrl_map **map, unsigned *num_maps)
491 {
492 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
493 const struct rockchip_pin_group *grp;
494 struct pinctrl_map *new_map;
495 struct device_node *parent;
496 int map_num = 1;
497 int i;
498
499 /*
500 * first find the group of this node and check if we need to create
501 * config maps for pins
502 */
503 grp = pinctrl_name_to_group(info, np->name);
504 if (!grp) {
505 dev_err(info->dev, "unable to find group for node %pOFn\n",
506 np);
507 return -EINVAL;
508 }
509
510 map_num += grp->npins;
511
512 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
513 if (!new_map)
514 return -ENOMEM;
515
516 *map = new_map;
517 *num_maps = map_num;
518
519 /* create mux map */
520 parent = of_get_parent(np);
521 if (!parent) {
522 kfree(new_map);
523 return -EINVAL;
524 }
525 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
526 new_map[0].data.mux.function = parent->name;
527 new_map[0].data.mux.group = np->name;
528 of_node_put(parent);
529
530 /* create config map */
531 new_map++;
532 for (i = 0; i < grp->npins; i++) {
533 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
534 new_map[i].data.configs.group_or_pin =
535 pin_get_name(pctldev, grp->pins[i]);
536 new_map[i].data.configs.configs = grp->data[i].configs;
537 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
538 }
539
540 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
541 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
542
543 return 0;
544 }
545
rockchip_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)546 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
547 struct pinctrl_map *map, unsigned num_maps)
548 {
549 kfree(map);
550 }
551
552 static const struct pinctrl_ops rockchip_pctrl_ops = {
553 .get_groups_count = rockchip_get_groups_count,
554 .get_group_name = rockchip_get_group_name,
555 .get_group_pins = rockchip_get_group_pins,
556 .dt_node_to_map = rockchip_dt_node_to_map,
557 .dt_free_map = rockchip_dt_free_map,
558 };
559
560 /*
561 * Hardware access
562 */
563
564 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
565 {
566 .num = 1,
567 .pin = 0,
568 .reg = 0x418,
569 .bit = 0,
570 .mask = 0x3
571 }, {
572 .num = 1,
573 .pin = 1,
574 .reg = 0x418,
575 .bit = 2,
576 .mask = 0x3
577 }, {
578 .num = 1,
579 .pin = 2,
580 .reg = 0x418,
581 .bit = 4,
582 .mask = 0x3
583 }, {
584 .num = 1,
585 .pin = 3,
586 .reg = 0x418,
587 .bit = 6,
588 .mask = 0x3
589 }, {
590 .num = 1,
591 .pin = 4,
592 .reg = 0x418,
593 .bit = 8,
594 .mask = 0x3
595 }, {
596 .num = 1,
597 .pin = 5,
598 .reg = 0x418,
599 .bit = 10,
600 .mask = 0x3
601 }, {
602 .num = 1,
603 .pin = 6,
604 .reg = 0x418,
605 .bit = 12,
606 .mask = 0x3
607 }, {
608 .num = 1,
609 .pin = 7,
610 .reg = 0x418,
611 .bit = 14,
612 .mask = 0x3
613 }, {
614 .num = 1,
615 .pin = 8,
616 .reg = 0x41c,
617 .bit = 0,
618 .mask = 0x3
619 }, {
620 .num = 1,
621 .pin = 9,
622 .reg = 0x41c,
623 .bit = 2,
624 .mask = 0x3
625 },
626 };
627
628 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
629 {
630 .num = 2,
631 .pin = 20,
632 .reg = 0xe8,
633 .bit = 0,
634 .mask = 0x7
635 }, {
636 .num = 2,
637 .pin = 21,
638 .reg = 0xe8,
639 .bit = 4,
640 .mask = 0x7
641 }, {
642 .num = 2,
643 .pin = 22,
644 .reg = 0xe8,
645 .bit = 8,
646 .mask = 0x7
647 }, {
648 .num = 2,
649 .pin = 23,
650 .reg = 0xe8,
651 .bit = 12,
652 .mask = 0x7
653 }, {
654 .num = 2,
655 .pin = 24,
656 .reg = 0xd4,
657 .bit = 12,
658 .mask = 0x7
659 },
660 };
661
662 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
663 {
664 .num = 2,
665 .pin = 12,
666 .reg = 0x24,
667 .bit = 8,
668 .mask = 0x3
669 }, {
670 .num = 2,
671 .pin = 15,
672 .reg = 0x28,
673 .bit = 0,
674 .mask = 0x7
675 }, {
676 .num = 2,
677 .pin = 23,
678 .reg = 0x30,
679 .bit = 14,
680 .mask = 0x3
681 },
682 };
683
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)684 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
685 int *reg, u8 *bit, int *mask)
686 {
687 struct rockchip_pinctrl *info = bank->drvdata;
688 struct rockchip_pin_ctrl *ctrl = info->ctrl;
689 struct rockchip_mux_recalced_data *data;
690 int i;
691
692 for (i = 0; i < ctrl->niomux_recalced; i++) {
693 data = &ctrl->iomux_recalced[i];
694 if (data->num == bank->bank_num &&
695 data->pin == pin)
696 break;
697 }
698
699 if (i >= ctrl->niomux_recalced)
700 return;
701
702 *reg = data->reg;
703 *mask = data->mask;
704 *bit = data->bit;
705 }
706
707 static struct rockchip_mux_route_data px30_mux_route_data[] = {
708 {
709 /* cif-d2m0 */
710 .bank_num = 2,
711 .pin = 0,
712 .func = 1,
713 .route_offset = 0x184,
714 .route_val = BIT(16 + 7),
715 }, {
716 /* cif-d2m1 */
717 .bank_num = 3,
718 .pin = 3,
719 .func = 3,
720 .route_offset = 0x184,
721 .route_val = BIT(16 + 7) | BIT(7),
722 }, {
723 /* pdm-m0 */
724 .bank_num = 3,
725 .pin = 22,
726 .func = 2,
727 .route_offset = 0x184,
728 .route_val = BIT(16 + 8),
729 }, {
730 /* pdm-m1 */
731 .bank_num = 2,
732 .pin = 22,
733 .func = 1,
734 .route_offset = 0x184,
735 .route_val = BIT(16 + 8) | BIT(8),
736 }, {
737 /* uart2-rxm0 */
738 .bank_num = 1,
739 .pin = 27,
740 .func = 2,
741 .route_offset = 0x184,
742 .route_val = BIT(16 + 10),
743 }, {
744 /* uart2-rxm1 */
745 .bank_num = 2,
746 .pin = 14,
747 .func = 2,
748 .route_offset = 0x184,
749 .route_val = BIT(16 + 10) | BIT(10),
750 }, {
751 /* uart3-rxm0 */
752 .bank_num = 0,
753 .pin = 17,
754 .func = 2,
755 .route_offset = 0x184,
756 .route_val = BIT(16 + 9),
757 }, {
758 /* uart3-rxm1 */
759 .bank_num = 1,
760 .pin = 15,
761 .func = 2,
762 .route_offset = 0x184,
763 .route_val = BIT(16 + 9) | BIT(9),
764 },
765 };
766
767 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
768 {
769 /* spi-0 */
770 .bank_num = 1,
771 .pin = 10,
772 .func = 1,
773 .route_offset = 0x144,
774 .route_val = BIT(16 + 3) | BIT(16 + 4),
775 }, {
776 /* spi-1 */
777 .bank_num = 1,
778 .pin = 27,
779 .func = 3,
780 .route_offset = 0x144,
781 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
782 }, {
783 /* spi-2 */
784 .bank_num = 0,
785 .pin = 13,
786 .func = 2,
787 .route_offset = 0x144,
788 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
789 }, {
790 /* i2s-0 */
791 .bank_num = 1,
792 .pin = 5,
793 .func = 1,
794 .route_offset = 0x144,
795 .route_val = BIT(16 + 5),
796 }, {
797 /* i2s-1 */
798 .bank_num = 0,
799 .pin = 14,
800 .func = 1,
801 .route_offset = 0x144,
802 .route_val = BIT(16 + 5) | BIT(5),
803 }, {
804 /* emmc-0 */
805 .bank_num = 1,
806 .pin = 22,
807 .func = 2,
808 .route_offset = 0x144,
809 .route_val = BIT(16 + 6),
810 }, {
811 /* emmc-1 */
812 .bank_num = 2,
813 .pin = 4,
814 .func = 2,
815 .route_offset = 0x144,
816 .route_val = BIT(16 + 6) | BIT(6),
817 },
818 };
819
820 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
821 {
822 /* non-iomuxed emmc/flash pins on flash-dqs */
823 .bank_num = 0,
824 .pin = 24,
825 .func = 1,
826 .route_location = ROCKCHIP_ROUTE_GRF,
827 .route_offset = 0xa0,
828 .route_val = BIT(16 + 11),
829 }, {
830 /* non-iomuxed emmc/flash pins on emmc-clk */
831 .bank_num = 0,
832 .pin = 24,
833 .func = 2,
834 .route_location = ROCKCHIP_ROUTE_GRF,
835 .route_offset = 0xa0,
836 .route_val = BIT(16 + 11) | BIT(11),
837 },
838 };
839
840 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
841 {
842 /* pwm0-0 */
843 .bank_num = 0,
844 .pin = 26,
845 .func = 1,
846 .route_offset = 0x50,
847 .route_val = BIT(16),
848 }, {
849 /* pwm0-1 */
850 .bank_num = 3,
851 .pin = 21,
852 .func = 1,
853 .route_offset = 0x50,
854 .route_val = BIT(16) | BIT(0),
855 }, {
856 /* pwm1-0 */
857 .bank_num = 0,
858 .pin = 27,
859 .func = 1,
860 .route_offset = 0x50,
861 .route_val = BIT(16 + 1),
862 }, {
863 /* pwm1-1 */
864 .bank_num = 0,
865 .pin = 30,
866 .func = 2,
867 .route_offset = 0x50,
868 .route_val = BIT(16 + 1) | BIT(1),
869 }, {
870 /* pwm2-0 */
871 .bank_num = 0,
872 .pin = 28,
873 .func = 1,
874 .route_offset = 0x50,
875 .route_val = BIT(16 + 2),
876 }, {
877 /* pwm2-1 */
878 .bank_num = 1,
879 .pin = 12,
880 .func = 2,
881 .route_offset = 0x50,
882 .route_val = BIT(16 + 2) | BIT(2),
883 }, {
884 /* pwm3-0 */
885 .bank_num = 3,
886 .pin = 26,
887 .func = 1,
888 .route_offset = 0x50,
889 .route_val = BIT(16 + 3),
890 }, {
891 /* pwm3-1 */
892 .bank_num = 1,
893 .pin = 11,
894 .func = 2,
895 .route_offset = 0x50,
896 .route_val = BIT(16 + 3) | BIT(3),
897 }, {
898 /* sdio-0_d0 */
899 .bank_num = 1,
900 .pin = 1,
901 .func = 1,
902 .route_offset = 0x50,
903 .route_val = BIT(16 + 4),
904 }, {
905 /* sdio-1_d0 */
906 .bank_num = 3,
907 .pin = 2,
908 .func = 1,
909 .route_offset = 0x50,
910 .route_val = BIT(16 + 4) | BIT(4),
911 }, {
912 /* spi-0_rx */
913 .bank_num = 0,
914 .pin = 13,
915 .func = 2,
916 .route_offset = 0x50,
917 .route_val = BIT(16 + 5),
918 }, {
919 /* spi-1_rx */
920 .bank_num = 2,
921 .pin = 0,
922 .func = 2,
923 .route_offset = 0x50,
924 .route_val = BIT(16 + 5) | BIT(5),
925 }, {
926 /* emmc-0_cmd */
927 .bank_num = 1,
928 .pin = 22,
929 .func = 2,
930 .route_offset = 0x50,
931 .route_val = BIT(16 + 7),
932 }, {
933 /* emmc-1_cmd */
934 .bank_num = 2,
935 .pin = 4,
936 .func = 2,
937 .route_offset = 0x50,
938 .route_val = BIT(16 + 7) | BIT(7),
939 }, {
940 /* uart2-0_rx */
941 .bank_num = 1,
942 .pin = 19,
943 .func = 2,
944 .route_offset = 0x50,
945 .route_val = BIT(16 + 8),
946 }, {
947 /* uart2-1_rx */
948 .bank_num = 1,
949 .pin = 10,
950 .func = 2,
951 .route_offset = 0x50,
952 .route_val = BIT(16 + 8) | BIT(8),
953 }, {
954 /* uart1-0_rx */
955 .bank_num = 1,
956 .pin = 10,
957 .func = 1,
958 .route_offset = 0x50,
959 .route_val = BIT(16 + 11),
960 }, {
961 /* uart1-1_rx */
962 .bank_num = 3,
963 .pin = 13,
964 .func = 1,
965 .route_offset = 0x50,
966 .route_val = BIT(16 + 11) | BIT(11),
967 },
968 };
969
970 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
971 {
972 /* edphdmi_cecinoutt1 */
973 .bank_num = 7,
974 .pin = 16,
975 .func = 2,
976 .route_offset = 0x264,
977 .route_val = BIT(16 + 12) | BIT(12),
978 }, {
979 /* edphdmi_cecinout */
980 .bank_num = 7,
981 .pin = 23,
982 .func = 4,
983 .route_offset = 0x264,
984 .route_val = BIT(16 + 12),
985 },
986 };
987
988 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
989 {
990 /* uart2dbg_rxm0 */
991 .bank_num = 1,
992 .pin = 1,
993 .func = 2,
994 .route_offset = 0x50,
995 .route_val = BIT(16) | BIT(16 + 1),
996 }, {
997 /* uart2dbg_rxm1 */
998 .bank_num = 2,
999 .pin = 1,
1000 .func = 1,
1001 .route_offset = 0x50,
1002 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1003 }, {
1004 /* gmac-m1_rxd0 */
1005 .bank_num = 1,
1006 .pin = 11,
1007 .func = 2,
1008 .route_offset = 0x50,
1009 .route_val = BIT(16 + 2) | BIT(2),
1010 }, {
1011 /* gmac-m1-optimized_rxd3 */
1012 .bank_num = 1,
1013 .pin = 14,
1014 .func = 2,
1015 .route_offset = 0x50,
1016 .route_val = BIT(16 + 10) | BIT(10),
1017 }, {
1018 /* pdm_sdi0m0 */
1019 .bank_num = 2,
1020 .pin = 19,
1021 .func = 2,
1022 .route_offset = 0x50,
1023 .route_val = BIT(16 + 3),
1024 }, {
1025 /* pdm_sdi0m1 */
1026 .bank_num = 1,
1027 .pin = 23,
1028 .func = 3,
1029 .route_offset = 0x50,
1030 .route_val = BIT(16 + 3) | BIT(3),
1031 }, {
1032 /* spi_rxdm2 */
1033 .bank_num = 3,
1034 .pin = 2,
1035 .func = 4,
1036 .route_offset = 0x50,
1037 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1038 }, {
1039 /* i2s2_sdim0 */
1040 .bank_num = 1,
1041 .pin = 24,
1042 .func = 1,
1043 .route_offset = 0x50,
1044 .route_val = BIT(16 + 6),
1045 }, {
1046 /* i2s2_sdim1 */
1047 .bank_num = 3,
1048 .pin = 2,
1049 .func = 6,
1050 .route_offset = 0x50,
1051 .route_val = BIT(16 + 6) | BIT(6),
1052 }, {
1053 /* card_iom1 */
1054 .bank_num = 2,
1055 .pin = 22,
1056 .func = 3,
1057 .route_offset = 0x50,
1058 .route_val = BIT(16 + 7) | BIT(7),
1059 }, {
1060 /* tsp_d5m1 */
1061 .bank_num = 2,
1062 .pin = 16,
1063 .func = 3,
1064 .route_offset = 0x50,
1065 .route_val = BIT(16 + 8) | BIT(8),
1066 }, {
1067 /* cif_data5m1 */
1068 .bank_num = 2,
1069 .pin = 16,
1070 .func = 4,
1071 .route_offset = 0x50,
1072 .route_val = BIT(16 + 9) | BIT(9),
1073 },
1074 };
1075
1076 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1077 {
1078 /* uart2dbga_rx */
1079 .bank_num = 4,
1080 .pin = 8,
1081 .func = 2,
1082 .route_offset = 0xe21c,
1083 .route_val = BIT(16 + 10) | BIT(16 + 11),
1084 }, {
1085 /* uart2dbgb_rx */
1086 .bank_num = 4,
1087 .pin = 16,
1088 .func = 2,
1089 .route_offset = 0xe21c,
1090 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1091 }, {
1092 /* uart2dbgc_rx */
1093 .bank_num = 4,
1094 .pin = 19,
1095 .func = 1,
1096 .route_offset = 0xe21c,
1097 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1098 }, {
1099 /* pcie_clkreqn */
1100 .bank_num = 2,
1101 .pin = 26,
1102 .func = 2,
1103 .route_offset = 0xe21c,
1104 .route_val = BIT(16 + 14),
1105 }, {
1106 /* pcie_clkreqnb */
1107 .bank_num = 4,
1108 .pin = 24,
1109 .func = 1,
1110 .route_offset = 0xe21c,
1111 .route_val = BIT(16 + 14) | BIT(14),
1112 },
1113 };
1114
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * loc,u32 * reg,u32 * value)1115 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1116 int mux, u32 *loc, u32 *reg, u32 *value)
1117 {
1118 struct rockchip_pinctrl *info = bank->drvdata;
1119 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1120 struct rockchip_mux_route_data *data;
1121 int i;
1122
1123 for (i = 0; i < ctrl->niomux_routes; i++) {
1124 data = &ctrl->iomux_routes[i];
1125 if ((data->bank_num == bank->bank_num) &&
1126 (data->pin == pin) && (data->func == mux))
1127 break;
1128 }
1129
1130 if (i >= ctrl->niomux_routes)
1131 return false;
1132
1133 *loc = data->route_location;
1134 *reg = data->route_offset;
1135 *value = data->route_val;
1136
1137 return true;
1138 }
1139
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)1140 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1141 {
1142 struct rockchip_pinctrl *info = bank->drvdata;
1143 int iomux_num = (pin / 8);
1144 struct regmap *regmap;
1145 unsigned int val;
1146 int reg, ret, mask, mux_type;
1147 u8 bit;
1148
1149 if (iomux_num > 3)
1150 return -EINVAL;
1151
1152 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1153 dev_err(info->dev, "pin %d is unrouted\n", pin);
1154 return -EINVAL;
1155 }
1156
1157 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1158 return RK_FUNC_GPIO;
1159
1160 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1161 ? info->regmap_pmu : info->regmap_base;
1162
1163 /* get basic quadrupel of mux registers and the correct reg inside */
1164 mux_type = bank->iomux[iomux_num].type;
1165 reg = bank->iomux[iomux_num].offset;
1166 if (mux_type & IOMUX_WIDTH_4BIT) {
1167 if ((pin % 8) >= 4)
1168 reg += 0x4;
1169 bit = (pin % 4) * 4;
1170 mask = 0xf;
1171 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1172 if ((pin % 8) >= 5)
1173 reg += 0x4;
1174 bit = (pin % 8 % 5) * 3;
1175 mask = 0x7;
1176 } else {
1177 bit = (pin % 8) * 2;
1178 mask = 0x3;
1179 }
1180
1181 if (bank->recalced_mask & BIT(pin))
1182 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1183
1184 ret = regmap_read(regmap, reg, &val);
1185 if (ret)
1186 return ret;
1187
1188 return ((val >> bit) & mask);
1189 }
1190
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)1191 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1192 int pin, int mux)
1193 {
1194 struct rockchip_pinctrl *info = bank->drvdata;
1195 int iomux_num = (pin / 8);
1196
1197 if (iomux_num > 3)
1198 return -EINVAL;
1199
1200 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1201 dev_err(info->dev, "pin %d is unrouted\n", pin);
1202 return -EINVAL;
1203 }
1204
1205 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1206 if (mux != RK_FUNC_GPIO) {
1207 dev_err(info->dev,
1208 "pin %d only supports a gpio mux\n", pin);
1209 return -ENOTSUPP;
1210 }
1211 }
1212
1213 return 0;
1214 }
1215
1216 /*
1217 * Set a new mux function for a pin.
1218 *
1219 * The register is divided into the upper and lower 16 bit. When changing
1220 * a value, the previous register value is not read and changed. Instead
1221 * it seems the changed bits are marked in the upper 16 bit, while the
1222 * changed value gets set in the same offset in the lower 16 bit.
1223 * All pin settings seem to be 2 bit wide in both the upper and lower
1224 * parts.
1225 * @bank: pin bank to change
1226 * @pin: pin to change
1227 * @mux: new mux function to set
1228 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)1229 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1230 {
1231 struct rockchip_pinctrl *info = bank->drvdata;
1232 int iomux_num = (pin / 8);
1233 struct regmap *regmap;
1234 int reg, ret, mask, mux_type;
1235 u8 bit;
1236 u32 data, rmask, route_location, route_reg, route_val;
1237
1238 ret = rockchip_verify_mux(bank, pin, mux);
1239 if (ret < 0)
1240 return ret;
1241
1242 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1243 return 0;
1244
1245 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1246 bank->bank_num, pin, mux);
1247
1248 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1249 ? info->regmap_pmu : info->regmap_base;
1250
1251 /* get basic quadrupel of mux registers and the correct reg inside */
1252 mux_type = bank->iomux[iomux_num].type;
1253 reg = bank->iomux[iomux_num].offset;
1254 if (mux_type & IOMUX_WIDTH_4BIT) {
1255 if ((pin % 8) >= 4)
1256 reg += 0x4;
1257 bit = (pin % 4) * 4;
1258 mask = 0xf;
1259 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1260 if ((pin % 8) >= 5)
1261 reg += 0x4;
1262 bit = (pin % 8 % 5) * 3;
1263 mask = 0x7;
1264 } else {
1265 bit = (pin % 8) * 2;
1266 mask = 0x3;
1267 }
1268
1269 if (bank->recalced_mask & BIT(pin))
1270 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1271
1272 if (bank->route_mask & BIT(pin)) {
1273 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1274 &route_reg, &route_val)) {
1275 struct regmap *route_regmap = regmap;
1276
1277 /* handle special locations */
1278 switch (route_location) {
1279 case ROCKCHIP_ROUTE_PMU:
1280 route_regmap = info->regmap_pmu;
1281 break;
1282 case ROCKCHIP_ROUTE_GRF:
1283 route_regmap = info->regmap_base;
1284 break;
1285 }
1286
1287 ret = regmap_write(route_regmap, route_reg, route_val);
1288 if (ret)
1289 return ret;
1290 }
1291 }
1292
1293 data = (mask << (bit + 16));
1294 rmask = data | (data >> 16);
1295 data |= (mux & mask) << bit;
1296 ret = regmap_update_bits(regmap, reg, rmask, data);
1297
1298 return ret;
1299 }
1300
1301 #define PX30_PULL_PMU_OFFSET 0x10
1302 #define PX30_PULL_GRF_OFFSET 0x60
1303 #define PX30_PULL_BITS_PER_PIN 2
1304 #define PX30_PULL_PINS_PER_REG 8
1305 #define PX30_PULL_BANK_STRIDE 16
1306
px30_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1307 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1308 int pin_num, struct regmap **regmap,
1309 int *reg, u8 *bit)
1310 {
1311 struct rockchip_pinctrl *info = bank->drvdata;
1312
1313 /* The first 32 pins of the first bank are located in PMU */
1314 if (bank->bank_num == 0) {
1315 *regmap = info->regmap_pmu;
1316 *reg = PX30_PULL_PMU_OFFSET;
1317 } else {
1318 *regmap = info->regmap_base;
1319 *reg = PX30_PULL_GRF_OFFSET;
1320
1321 /* correct the offset, as we're starting with the 2nd bank */
1322 *reg -= 0x10;
1323 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1324 }
1325
1326 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1327 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1328 *bit *= PX30_PULL_BITS_PER_PIN;
1329 }
1330
1331 #define PX30_DRV_PMU_OFFSET 0x20
1332 #define PX30_DRV_GRF_OFFSET 0xf0
1333 #define PX30_DRV_BITS_PER_PIN 2
1334 #define PX30_DRV_PINS_PER_REG 8
1335 #define PX30_DRV_BANK_STRIDE 16
1336
px30_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1337 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1338 int pin_num, struct regmap **regmap,
1339 int *reg, u8 *bit)
1340 {
1341 struct rockchip_pinctrl *info = bank->drvdata;
1342
1343 /* The first 32 pins of the first bank are located in PMU */
1344 if (bank->bank_num == 0) {
1345 *regmap = info->regmap_pmu;
1346 *reg = PX30_DRV_PMU_OFFSET;
1347 } else {
1348 *regmap = info->regmap_base;
1349 *reg = PX30_DRV_GRF_OFFSET;
1350
1351 /* correct the offset, as we're starting with the 2nd bank */
1352 *reg -= 0x10;
1353 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1354 }
1355
1356 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1357 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1358 *bit *= PX30_DRV_BITS_PER_PIN;
1359 }
1360
1361 #define PX30_SCHMITT_PMU_OFFSET 0x38
1362 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1363 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1364 #define PX30_SCHMITT_BANK_STRIDE 16
1365 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1366
px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1367 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1368 int pin_num,
1369 struct regmap **regmap,
1370 int *reg, u8 *bit)
1371 {
1372 struct rockchip_pinctrl *info = bank->drvdata;
1373 int pins_per_reg;
1374
1375 if (bank->bank_num == 0) {
1376 *regmap = info->regmap_pmu;
1377 *reg = PX30_SCHMITT_PMU_OFFSET;
1378 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1379 } else {
1380 *regmap = info->regmap_base;
1381 *reg = PX30_SCHMITT_GRF_OFFSET;
1382 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1383 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1384 }
1385
1386 *reg += ((pin_num / pins_per_reg) * 4);
1387 *bit = pin_num % pins_per_reg;
1388
1389 return 0;
1390 }
1391
1392 #define RV1108_PULL_PMU_OFFSET 0x10
1393 #define RV1108_PULL_OFFSET 0x110
1394 #define RV1108_PULL_PINS_PER_REG 8
1395 #define RV1108_PULL_BITS_PER_PIN 2
1396 #define RV1108_PULL_BANK_STRIDE 16
1397
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1398 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1399 int pin_num, struct regmap **regmap,
1400 int *reg, u8 *bit)
1401 {
1402 struct rockchip_pinctrl *info = bank->drvdata;
1403
1404 /* The first 24 pins of the first bank are located in PMU */
1405 if (bank->bank_num == 0) {
1406 *regmap = info->regmap_pmu;
1407 *reg = RV1108_PULL_PMU_OFFSET;
1408 } else {
1409 *reg = RV1108_PULL_OFFSET;
1410 *regmap = info->regmap_base;
1411 /* correct the offset, as we're starting with the 2nd bank */
1412 *reg -= 0x10;
1413 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1414 }
1415
1416 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1417 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1418 *bit *= RV1108_PULL_BITS_PER_PIN;
1419 }
1420
1421 #define RV1108_DRV_PMU_OFFSET 0x20
1422 #define RV1108_DRV_GRF_OFFSET 0x210
1423 #define RV1108_DRV_BITS_PER_PIN 2
1424 #define RV1108_DRV_PINS_PER_REG 8
1425 #define RV1108_DRV_BANK_STRIDE 16
1426
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1427 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1428 int pin_num, struct regmap **regmap,
1429 int *reg, u8 *bit)
1430 {
1431 struct rockchip_pinctrl *info = bank->drvdata;
1432
1433 /* The first 24 pins of the first bank are located in PMU */
1434 if (bank->bank_num == 0) {
1435 *regmap = info->regmap_pmu;
1436 *reg = RV1108_DRV_PMU_OFFSET;
1437 } else {
1438 *regmap = info->regmap_base;
1439 *reg = RV1108_DRV_GRF_OFFSET;
1440
1441 /* correct the offset, as we're starting with the 2nd bank */
1442 *reg -= 0x10;
1443 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1444 }
1445
1446 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1447 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1448 *bit *= RV1108_DRV_BITS_PER_PIN;
1449 }
1450
1451 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1452 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1453 #define RV1108_SCHMITT_BANK_STRIDE 8
1454 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1455 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1456
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1457 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1458 int pin_num,
1459 struct regmap **regmap,
1460 int *reg, u8 *bit)
1461 {
1462 struct rockchip_pinctrl *info = bank->drvdata;
1463 int pins_per_reg;
1464
1465 if (bank->bank_num == 0) {
1466 *regmap = info->regmap_pmu;
1467 *reg = RV1108_SCHMITT_PMU_OFFSET;
1468 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1469 } else {
1470 *regmap = info->regmap_base;
1471 *reg = RV1108_SCHMITT_GRF_OFFSET;
1472 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1473 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1474 }
1475 *reg += ((pin_num / pins_per_reg) * 4);
1476 *bit = pin_num % pins_per_reg;
1477
1478 return 0;
1479 }
1480
1481 #define RK2928_PULL_OFFSET 0x118
1482 #define RK2928_PULL_PINS_PER_REG 16
1483 #define RK2928_PULL_BANK_STRIDE 8
1484
rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1485 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1486 int pin_num, struct regmap **regmap,
1487 int *reg, u8 *bit)
1488 {
1489 struct rockchip_pinctrl *info = bank->drvdata;
1490
1491 *regmap = info->regmap_base;
1492 *reg = RK2928_PULL_OFFSET;
1493 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1494 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1495
1496 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1497 };
1498
1499 #define RK3128_PULL_OFFSET 0x118
1500
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1501 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1502 int pin_num, struct regmap **regmap,
1503 int *reg, u8 *bit)
1504 {
1505 struct rockchip_pinctrl *info = bank->drvdata;
1506
1507 *regmap = info->regmap_base;
1508 *reg = RK3128_PULL_OFFSET;
1509 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1510 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1511
1512 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1513 }
1514
1515 #define RK3188_PULL_OFFSET 0x164
1516 #define RK3188_PULL_BITS_PER_PIN 2
1517 #define RK3188_PULL_PINS_PER_REG 8
1518 #define RK3188_PULL_BANK_STRIDE 16
1519 #define RK3188_PULL_PMU_OFFSET 0x64
1520
rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1521 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1522 int pin_num, struct regmap **regmap,
1523 int *reg, u8 *bit)
1524 {
1525 struct rockchip_pinctrl *info = bank->drvdata;
1526
1527 /* The first 12 pins of the first bank are located elsewhere */
1528 if (bank->bank_num == 0 && pin_num < 12) {
1529 *regmap = info->regmap_pmu ? info->regmap_pmu
1530 : bank->regmap_pull;
1531 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1532 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1533 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1534 *bit *= RK3188_PULL_BITS_PER_PIN;
1535 } else {
1536 *regmap = info->regmap_pull ? info->regmap_pull
1537 : info->regmap_base;
1538 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1539
1540 /* correct the offset, as it is the 2nd pull register */
1541 *reg -= 4;
1542 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1543 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1544
1545 /*
1546 * The bits in these registers have an inverse ordering
1547 * with the lowest pin being in bits 15:14 and the highest
1548 * pin in bits 1:0
1549 */
1550 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1551 *bit *= RK3188_PULL_BITS_PER_PIN;
1552 }
1553 }
1554
1555 #define RK3288_PULL_OFFSET 0x140
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1556 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1557 int pin_num, struct regmap **regmap,
1558 int *reg, u8 *bit)
1559 {
1560 struct rockchip_pinctrl *info = bank->drvdata;
1561
1562 /* The first 24 pins of the first bank are located in PMU */
1563 if (bank->bank_num == 0) {
1564 *regmap = info->regmap_pmu;
1565 *reg = RK3188_PULL_PMU_OFFSET;
1566
1567 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1568 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1569 *bit *= RK3188_PULL_BITS_PER_PIN;
1570 } else {
1571 *regmap = info->regmap_base;
1572 *reg = RK3288_PULL_OFFSET;
1573
1574 /* correct the offset, as we're starting with the 2nd bank */
1575 *reg -= 0x10;
1576 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1577 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1578
1579 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1580 *bit *= RK3188_PULL_BITS_PER_PIN;
1581 }
1582 }
1583
1584 #define RK3288_DRV_PMU_OFFSET 0x70
1585 #define RK3288_DRV_GRF_OFFSET 0x1c0
1586 #define RK3288_DRV_BITS_PER_PIN 2
1587 #define RK3288_DRV_PINS_PER_REG 8
1588 #define RK3288_DRV_BANK_STRIDE 16
1589
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1590 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1591 int pin_num, struct regmap **regmap,
1592 int *reg, u8 *bit)
1593 {
1594 struct rockchip_pinctrl *info = bank->drvdata;
1595
1596 /* The first 24 pins of the first bank are located in PMU */
1597 if (bank->bank_num == 0) {
1598 *regmap = info->regmap_pmu;
1599 *reg = RK3288_DRV_PMU_OFFSET;
1600
1601 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1602 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1603 *bit *= RK3288_DRV_BITS_PER_PIN;
1604 } else {
1605 *regmap = info->regmap_base;
1606 *reg = RK3288_DRV_GRF_OFFSET;
1607
1608 /* correct the offset, as we're starting with the 2nd bank */
1609 *reg -= 0x10;
1610 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1611 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1612
1613 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1614 *bit *= RK3288_DRV_BITS_PER_PIN;
1615 }
1616 }
1617
1618 #define RK3228_PULL_OFFSET 0x100
1619
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1620 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1621 int pin_num, struct regmap **regmap,
1622 int *reg, u8 *bit)
1623 {
1624 struct rockchip_pinctrl *info = bank->drvdata;
1625
1626 *regmap = info->regmap_base;
1627 *reg = RK3228_PULL_OFFSET;
1628 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1629 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1630
1631 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1632 *bit *= RK3188_PULL_BITS_PER_PIN;
1633 }
1634
1635 #define RK3228_DRV_GRF_OFFSET 0x200
1636
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1637 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1638 int pin_num, struct regmap **regmap,
1639 int *reg, u8 *bit)
1640 {
1641 struct rockchip_pinctrl *info = bank->drvdata;
1642
1643 *regmap = info->regmap_base;
1644 *reg = RK3228_DRV_GRF_OFFSET;
1645 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1646 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1647
1648 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1649 *bit *= RK3288_DRV_BITS_PER_PIN;
1650 }
1651
1652 #define RK3368_PULL_GRF_OFFSET 0x100
1653 #define RK3368_PULL_PMU_OFFSET 0x10
1654
rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1655 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1656 int pin_num, struct regmap **regmap,
1657 int *reg, u8 *bit)
1658 {
1659 struct rockchip_pinctrl *info = bank->drvdata;
1660
1661 /* The first 32 pins of the first bank are located in PMU */
1662 if (bank->bank_num == 0) {
1663 *regmap = info->regmap_pmu;
1664 *reg = RK3368_PULL_PMU_OFFSET;
1665
1666 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1667 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1668 *bit *= RK3188_PULL_BITS_PER_PIN;
1669 } else {
1670 *regmap = info->regmap_base;
1671 *reg = RK3368_PULL_GRF_OFFSET;
1672
1673 /* correct the offset, as we're starting with the 2nd bank */
1674 *reg -= 0x10;
1675 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1676 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1677
1678 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1679 *bit *= RK3188_PULL_BITS_PER_PIN;
1680 }
1681 }
1682
1683 #define RK3368_DRV_PMU_OFFSET 0x20
1684 #define RK3368_DRV_GRF_OFFSET 0x200
1685
rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1686 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1687 int pin_num, struct regmap **regmap,
1688 int *reg, u8 *bit)
1689 {
1690 struct rockchip_pinctrl *info = bank->drvdata;
1691
1692 /* The first 32 pins of the first bank are located in PMU */
1693 if (bank->bank_num == 0) {
1694 *regmap = info->regmap_pmu;
1695 *reg = RK3368_DRV_PMU_OFFSET;
1696
1697 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1698 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1699 *bit *= RK3288_DRV_BITS_PER_PIN;
1700 } else {
1701 *regmap = info->regmap_base;
1702 *reg = RK3368_DRV_GRF_OFFSET;
1703
1704 /* correct the offset, as we're starting with the 2nd bank */
1705 *reg -= 0x10;
1706 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1707 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1708
1709 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1710 *bit *= RK3288_DRV_BITS_PER_PIN;
1711 }
1712 }
1713
1714 #define RK3399_PULL_GRF_OFFSET 0xe040
1715 #define RK3399_PULL_PMU_OFFSET 0x40
1716 #define RK3399_DRV_3BITS_PER_PIN 3
1717
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1718 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1719 int pin_num, struct regmap **regmap,
1720 int *reg, u8 *bit)
1721 {
1722 struct rockchip_pinctrl *info = bank->drvdata;
1723
1724 /* The bank0:16 and bank1:32 pins are located in PMU */
1725 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1726 *regmap = info->regmap_pmu;
1727 *reg = RK3399_PULL_PMU_OFFSET;
1728
1729 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1730
1731 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1732 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1733 *bit *= RK3188_PULL_BITS_PER_PIN;
1734 } else {
1735 *regmap = info->regmap_base;
1736 *reg = RK3399_PULL_GRF_OFFSET;
1737
1738 /* correct the offset, as we're starting with the 3rd bank */
1739 *reg -= 0x20;
1740 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1741 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1742
1743 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1744 *bit *= RK3188_PULL_BITS_PER_PIN;
1745 }
1746 }
1747
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1748 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1749 int pin_num, struct regmap **regmap,
1750 int *reg, u8 *bit)
1751 {
1752 struct rockchip_pinctrl *info = bank->drvdata;
1753 int drv_num = (pin_num / 8);
1754
1755 /* The bank0:16 and bank1:32 pins are located in PMU */
1756 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1757 *regmap = info->regmap_pmu;
1758 else
1759 *regmap = info->regmap_base;
1760
1761 *reg = bank->drv[drv_num].offset;
1762 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1763 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1764 *bit = (pin_num % 8) * 3;
1765 else
1766 *bit = (pin_num % 8) * 2;
1767 }
1768
1769 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1770 { 2, 4, 8, 12, -1, -1, -1, -1 },
1771 { 3, 6, 9, 12, -1, -1, -1, -1 },
1772 { 5, 10, 15, 20, -1, -1, -1, -1 },
1773 { 4, 6, 8, 10, 12, 14, 16, 18 },
1774 { 4, 7, 10, 13, 16, 19, 22, 26 }
1775 };
1776
rockchip_get_drive_perpin(struct rockchip_pin_bank * bank,int pin_num)1777 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1778 int pin_num)
1779 {
1780 struct rockchip_pinctrl *info = bank->drvdata;
1781 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1782 struct regmap *regmap;
1783 int reg, ret;
1784 u32 data, temp, rmask_bits;
1785 u8 bit;
1786 int drv_type = bank->drv[pin_num / 8].drv_type;
1787
1788 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1789
1790 switch (drv_type) {
1791 case DRV_TYPE_IO_1V8_3V0_AUTO:
1792 case DRV_TYPE_IO_3V3_ONLY:
1793 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1794 switch (bit) {
1795 case 0 ... 12:
1796 /* regular case, nothing to do */
1797 break;
1798 case 15:
1799 /*
1800 * drive-strength offset is special, as it is
1801 * spread over 2 registers
1802 */
1803 ret = regmap_read(regmap, reg, &data);
1804 if (ret)
1805 return ret;
1806
1807 ret = regmap_read(regmap, reg + 0x4, &temp);
1808 if (ret)
1809 return ret;
1810
1811 /*
1812 * the bit data[15] contains bit 0 of the value
1813 * while temp[1:0] contains bits 2 and 1
1814 */
1815 data >>= 15;
1816 temp &= 0x3;
1817 temp <<= 1;
1818 data |= temp;
1819
1820 return rockchip_perpin_drv_list[drv_type][data];
1821 case 18 ... 21:
1822 /* setting fully enclosed in the second register */
1823 reg += 4;
1824 bit -= 16;
1825 break;
1826 default:
1827 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1828 bit, drv_type);
1829 return -EINVAL;
1830 }
1831
1832 break;
1833 case DRV_TYPE_IO_DEFAULT:
1834 case DRV_TYPE_IO_1V8_OR_3V0:
1835 case DRV_TYPE_IO_1V8_ONLY:
1836 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1837 break;
1838 default:
1839 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1840 drv_type);
1841 return -EINVAL;
1842 }
1843
1844 ret = regmap_read(regmap, reg, &data);
1845 if (ret)
1846 return ret;
1847
1848 data >>= bit;
1849 data &= (1 << rmask_bits) - 1;
1850
1851 return rockchip_perpin_drv_list[drv_type][data];
1852 }
1853
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)1854 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1855 int pin_num, int strength)
1856 {
1857 struct rockchip_pinctrl *info = bank->drvdata;
1858 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1859 struct regmap *regmap;
1860 int reg, ret, i;
1861 u32 data, rmask, rmask_bits, temp;
1862 u8 bit;
1863 int drv_type = bank->drv[pin_num / 8].drv_type;
1864
1865 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1866 bank->bank_num, pin_num, strength);
1867
1868 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1869
1870 ret = -EINVAL;
1871 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1872 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1873 ret = i;
1874 break;
1875 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1876 ret = rockchip_perpin_drv_list[drv_type][i];
1877 break;
1878 }
1879 }
1880
1881 if (ret < 0) {
1882 dev_err(info->dev, "unsupported driver strength %d\n",
1883 strength);
1884 return ret;
1885 }
1886
1887 switch (drv_type) {
1888 case DRV_TYPE_IO_1V8_3V0_AUTO:
1889 case DRV_TYPE_IO_3V3_ONLY:
1890 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1891 switch (bit) {
1892 case 0 ... 12:
1893 /* regular case, nothing to do */
1894 break;
1895 case 15:
1896 /*
1897 * drive-strength offset is special, as it is spread
1898 * over 2 registers, the bit data[15] contains bit 0
1899 * of the value while temp[1:0] contains bits 2 and 1
1900 */
1901 data = (ret & 0x1) << 15;
1902 temp = (ret >> 0x1) & 0x3;
1903
1904 rmask = BIT(15) | BIT(31);
1905 data |= BIT(31);
1906 ret = regmap_update_bits(regmap, reg, rmask, data);
1907 if (ret)
1908 return ret;
1909
1910 rmask = 0x3 | (0x3 << 16);
1911 temp |= (0x3 << 16);
1912 reg += 0x4;
1913 ret = regmap_update_bits(regmap, reg, rmask, temp);
1914
1915 return ret;
1916 case 18 ... 21:
1917 /* setting fully enclosed in the second register */
1918 reg += 4;
1919 bit -= 16;
1920 break;
1921 default:
1922 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1923 bit, drv_type);
1924 return -EINVAL;
1925 }
1926 break;
1927 case DRV_TYPE_IO_DEFAULT:
1928 case DRV_TYPE_IO_1V8_OR_3V0:
1929 case DRV_TYPE_IO_1V8_ONLY:
1930 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1931 break;
1932 default:
1933 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1934 drv_type);
1935 return -EINVAL;
1936 }
1937
1938 /* enable the write to the equivalent lower bits */
1939 data = ((1 << rmask_bits) - 1) << (bit + 16);
1940 rmask = data | (data >> 16);
1941 data |= (ret << bit);
1942
1943 ret = regmap_update_bits(regmap, reg, rmask, data);
1944
1945 return ret;
1946 }
1947
1948 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1949 {
1950 PIN_CONFIG_BIAS_DISABLE,
1951 PIN_CONFIG_BIAS_PULL_UP,
1952 PIN_CONFIG_BIAS_PULL_DOWN,
1953 PIN_CONFIG_BIAS_BUS_HOLD
1954 },
1955 {
1956 PIN_CONFIG_BIAS_DISABLE,
1957 PIN_CONFIG_BIAS_PULL_DOWN,
1958 PIN_CONFIG_BIAS_DISABLE,
1959 PIN_CONFIG_BIAS_PULL_UP
1960 },
1961 };
1962
rockchip_get_pull(struct rockchip_pin_bank * bank,int pin_num)1963 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1964 {
1965 struct rockchip_pinctrl *info = bank->drvdata;
1966 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1967 struct regmap *regmap;
1968 int reg, ret, pull_type;
1969 u8 bit;
1970 u32 data;
1971
1972 /* rk3066b does support any pulls */
1973 if (ctrl->type == RK3066B)
1974 return PIN_CONFIG_BIAS_DISABLE;
1975
1976 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1977
1978 ret = regmap_read(regmap, reg, &data);
1979 if (ret)
1980 return ret;
1981
1982 switch (ctrl->type) {
1983 case RK2928:
1984 case RK3128:
1985 return !(data & BIT(bit))
1986 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1987 : PIN_CONFIG_BIAS_DISABLE;
1988 case PX30:
1989 case RV1108:
1990 case RK3188:
1991 case RK3288:
1992 case RK3368:
1993 case RK3399:
1994 pull_type = bank->pull_type[pin_num / 8];
1995 data >>= bit;
1996 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1997
1998 return rockchip_pull_list[pull_type][data];
1999 default:
2000 dev_err(info->dev, "unsupported pinctrl type\n");
2001 return -EINVAL;
2002 };
2003 }
2004
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)2005 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2006 int pin_num, int pull)
2007 {
2008 struct rockchip_pinctrl *info = bank->drvdata;
2009 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2010 struct regmap *regmap;
2011 int reg, ret, i, pull_type;
2012 u8 bit;
2013 u32 data, rmask;
2014
2015 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2016 bank->bank_num, pin_num, pull);
2017
2018 /* rk3066b does support any pulls */
2019 if (ctrl->type == RK3066B)
2020 return pull ? -EINVAL : 0;
2021
2022 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2023
2024 switch (ctrl->type) {
2025 case RK2928:
2026 case RK3128:
2027 data = BIT(bit + 16);
2028 if (pull == PIN_CONFIG_BIAS_DISABLE)
2029 data |= BIT(bit);
2030 ret = regmap_write(regmap, reg, data);
2031 break;
2032 case PX30:
2033 case RV1108:
2034 case RK3188:
2035 case RK3288:
2036 case RK3368:
2037 case RK3399:
2038 pull_type = bank->pull_type[pin_num / 8];
2039 ret = -EINVAL;
2040 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2041 i++) {
2042 if (rockchip_pull_list[pull_type][i] == pull) {
2043 ret = i;
2044 break;
2045 }
2046 }
2047
2048 if (ret < 0) {
2049 dev_err(info->dev, "unsupported pull setting %d\n",
2050 pull);
2051 return ret;
2052 }
2053
2054 /* enable the write to the equivalent lower bits */
2055 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2056 rmask = data | (data >> 16);
2057 data |= (ret << bit);
2058
2059 ret = regmap_update_bits(regmap, reg, rmask, data);
2060 break;
2061 default:
2062 dev_err(info->dev, "unsupported pinctrl type\n");
2063 return -EINVAL;
2064 }
2065
2066 return ret;
2067 }
2068
2069 #define RK3328_SCHMITT_BITS_PER_PIN 1
2070 #define RK3328_SCHMITT_PINS_PER_REG 16
2071 #define RK3328_SCHMITT_BANK_STRIDE 8
2072 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2073
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2074 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2075 int pin_num,
2076 struct regmap **regmap,
2077 int *reg, u8 *bit)
2078 {
2079 struct rockchip_pinctrl *info = bank->drvdata;
2080
2081 *regmap = info->regmap_base;
2082 *reg = RK3328_SCHMITT_GRF_OFFSET;
2083
2084 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2085 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2086 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2087
2088 return 0;
2089 }
2090
rockchip_get_schmitt(struct rockchip_pin_bank * bank,int pin_num)2091 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2092 {
2093 struct rockchip_pinctrl *info = bank->drvdata;
2094 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2095 struct regmap *regmap;
2096 int reg, ret;
2097 u8 bit;
2098 u32 data;
2099
2100 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2101 if (ret)
2102 return ret;
2103
2104 ret = regmap_read(regmap, reg, &data);
2105 if (ret)
2106 return ret;
2107
2108 data >>= bit;
2109 return data & 0x1;
2110 }
2111
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)2112 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2113 int pin_num, int enable)
2114 {
2115 struct rockchip_pinctrl *info = bank->drvdata;
2116 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2117 struct regmap *regmap;
2118 int reg, ret;
2119 u8 bit;
2120 u32 data, rmask;
2121
2122 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2123 bank->bank_num, pin_num, enable);
2124
2125 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2126 if (ret)
2127 return ret;
2128
2129 /* enable the write to the equivalent lower bits */
2130 data = BIT(bit + 16) | (enable << bit);
2131 rmask = BIT(bit + 16) | BIT(bit);
2132
2133 return regmap_update_bits(regmap, reg, rmask, data);
2134 }
2135
2136 /*
2137 * Pinmux_ops handling
2138 */
2139
rockchip_pmx_get_funcs_count(struct pinctrl_dev * pctldev)2140 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2141 {
2142 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2143
2144 return info->nfunctions;
2145 }
2146
rockchip_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)2147 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2148 unsigned selector)
2149 {
2150 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2151
2152 return info->functions[selector].name;
2153 }
2154
rockchip_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)2155 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2156 unsigned selector, const char * const **groups,
2157 unsigned * const num_groups)
2158 {
2159 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2160
2161 *groups = info->functions[selector].groups;
2162 *num_groups = info->functions[selector].ngroups;
2163
2164 return 0;
2165 }
2166
rockchip_pmx_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)2167 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2168 unsigned group)
2169 {
2170 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2171 const unsigned int *pins = info->groups[group].pins;
2172 const struct rockchip_pin_config *data = info->groups[group].data;
2173 struct rockchip_pin_bank *bank;
2174 int cnt, ret = 0;
2175
2176 dev_dbg(info->dev, "enable function %s group %s\n",
2177 info->functions[selector].name, info->groups[group].name);
2178
2179 /*
2180 * for each pin in the pin group selected, program the corresponding
2181 * pin function number in the config register.
2182 */
2183 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2184 bank = pin_to_bank(info, pins[cnt]);
2185 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2186 data[cnt].func);
2187 if (ret)
2188 break;
2189 }
2190
2191 if (ret) {
2192 /* revert the already done pin settings */
2193 for (cnt--; cnt >= 0; cnt--)
2194 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2195
2196 return ret;
2197 }
2198
2199 return 0;
2200 }
2201
rockchip_gpio_get_direction(struct gpio_chip * chip,unsigned offset)2202 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2203 {
2204 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2205 u32 data;
2206 int ret;
2207
2208 ret = clk_enable(bank->clk);
2209 if (ret < 0) {
2210 dev_err(bank->drvdata->dev,
2211 "failed to enable clock for bank %s\n", bank->name);
2212 return ret;
2213 }
2214 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2215 clk_disable(bank->clk);
2216
2217 return !(data & BIT(offset));
2218 }
2219
2220 /*
2221 * The calls to gpio_direction_output() and gpio_direction_input()
2222 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2223 * function called from the gpiolib interface).
2224 */
_rockchip_pmx_gpio_set_direction(struct gpio_chip * chip,int pin,bool input)2225 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2226 int pin, bool input)
2227 {
2228 struct rockchip_pin_bank *bank;
2229 int ret;
2230 unsigned long flags;
2231 u32 data;
2232
2233 bank = gpiochip_get_data(chip);
2234
2235 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2236 if (ret < 0)
2237 return ret;
2238
2239 clk_enable(bank->clk);
2240 raw_spin_lock_irqsave(&bank->slock, flags);
2241
2242 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2243 /* set bit to 1 for output, 0 for input */
2244 if (!input)
2245 data |= BIT(pin);
2246 else
2247 data &= ~BIT(pin);
2248 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2249
2250 raw_spin_unlock_irqrestore(&bank->slock, flags);
2251 clk_disable(bank->clk);
2252
2253 return 0;
2254 }
2255
rockchip_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset,bool input)2256 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2257 struct pinctrl_gpio_range *range,
2258 unsigned offset, bool input)
2259 {
2260 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2261 struct gpio_chip *chip;
2262 int pin;
2263
2264 chip = range->gc;
2265 pin = offset - chip->base;
2266 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2267 offset, range->name, pin, input ? "input" : "output");
2268
2269 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2270 input);
2271 }
2272
2273 static const struct pinmux_ops rockchip_pmx_ops = {
2274 .get_functions_count = rockchip_pmx_get_funcs_count,
2275 .get_function_name = rockchip_pmx_get_func_name,
2276 .get_function_groups = rockchip_pmx_get_groups,
2277 .set_mux = rockchip_pmx_set,
2278 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2279 };
2280
2281 /*
2282 * Pinconf_ops handling
2283 */
2284
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,enum pin_config_param pull)2285 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2286 enum pin_config_param pull)
2287 {
2288 switch (ctrl->type) {
2289 case RK2928:
2290 case RK3128:
2291 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2292 pull == PIN_CONFIG_BIAS_DISABLE);
2293 case RK3066B:
2294 return pull ? false : true;
2295 case PX30:
2296 case RV1108:
2297 case RK3188:
2298 case RK3288:
2299 case RK3368:
2300 case RK3399:
2301 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2302 }
2303
2304 return false;
2305 }
2306
2307 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2308 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2309
2310 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned num_configs)2311 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2312 unsigned long *configs, unsigned num_configs)
2313 {
2314 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2315 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2316 enum pin_config_param param;
2317 u32 arg;
2318 int i;
2319 int rc;
2320
2321 for (i = 0; i < num_configs; i++) {
2322 param = pinconf_to_config_param(configs[i]);
2323 arg = pinconf_to_config_argument(configs[i]);
2324
2325 switch (param) {
2326 case PIN_CONFIG_BIAS_DISABLE:
2327 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2328 param);
2329 if (rc)
2330 return rc;
2331 break;
2332 case PIN_CONFIG_BIAS_PULL_UP:
2333 case PIN_CONFIG_BIAS_PULL_DOWN:
2334 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2335 case PIN_CONFIG_BIAS_BUS_HOLD:
2336 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2337 return -ENOTSUPP;
2338
2339 if (!arg)
2340 return -EINVAL;
2341
2342 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2343 param);
2344 if (rc)
2345 return rc;
2346 break;
2347 case PIN_CONFIG_OUTPUT:
2348 rockchip_gpio_set(&bank->gpio_chip,
2349 pin - bank->pin_base, arg);
2350 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2351 pin - bank->pin_base, false);
2352 if (rc)
2353 return rc;
2354 break;
2355 case PIN_CONFIG_DRIVE_STRENGTH:
2356 /* rk3288 is the first with per-pin drive-strength */
2357 if (!info->ctrl->drv_calc_reg)
2358 return -ENOTSUPP;
2359
2360 rc = rockchip_set_drive_perpin(bank,
2361 pin - bank->pin_base, arg);
2362 if (rc < 0)
2363 return rc;
2364 break;
2365 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2366 if (!info->ctrl->schmitt_calc_reg)
2367 return -ENOTSUPP;
2368
2369 rc = rockchip_set_schmitt(bank,
2370 pin - bank->pin_base, arg);
2371 if (rc < 0)
2372 return rc;
2373 break;
2374 default:
2375 return -ENOTSUPP;
2376 break;
2377 }
2378 } /* for each config */
2379
2380 return 0;
2381 }
2382
2383 /* get the pin config settings for a specified pin */
rockchip_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)2384 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2385 unsigned long *config)
2386 {
2387 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2388 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2389 enum pin_config_param param = pinconf_to_config_param(*config);
2390 u16 arg;
2391 int rc;
2392
2393 switch (param) {
2394 case PIN_CONFIG_BIAS_DISABLE:
2395 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2396 return -EINVAL;
2397
2398 arg = 0;
2399 break;
2400 case PIN_CONFIG_BIAS_PULL_UP:
2401 case PIN_CONFIG_BIAS_PULL_DOWN:
2402 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2403 case PIN_CONFIG_BIAS_BUS_HOLD:
2404 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2405 return -ENOTSUPP;
2406
2407 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2408 return -EINVAL;
2409
2410 arg = 1;
2411 break;
2412 case PIN_CONFIG_OUTPUT:
2413 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2414 if (rc != RK_FUNC_GPIO)
2415 return -EINVAL;
2416
2417 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2418 if (rc < 0)
2419 return rc;
2420
2421 arg = rc ? 1 : 0;
2422 break;
2423 case PIN_CONFIG_DRIVE_STRENGTH:
2424 /* rk3288 is the first with per-pin drive-strength */
2425 if (!info->ctrl->drv_calc_reg)
2426 return -ENOTSUPP;
2427
2428 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2429 if (rc < 0)
2430 return rc;
2431
2432 arg = rc;
2433 break;
2434 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2435 if (!info->ctrl->schmitt_calc_reg)
2436 return -ENOTSUPP;
2437
2438 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2439 if (rc < 0)
2440 return rc;
2441
2442 arg = rc;
2443 break;
2444 default:
2445 return -ENOTSUPP;
2446 break;
2447 }
2448
2449 *config = pinconf_to_config_packed(param, arg);
2450
2451 return 0;
2452 }
2453
2454 static const struct pinconf_ops rockchip_pinconf_ops = {
2455 .pin_config_get = rockchip_pinconf_get,
2456 .pin_config_set = rockchip_pinconf_set,
2457 .is_generic = true,
2458 };
2459
2460 static const struct of_device_id rockchip_bank_match[] = {
2461 { .compatible = "rockchip,gpio-bank" },
2462 { .compatible = "rockchip,rk3188-gpio-bank0" },
2463 {},
2464 };
2465
rockchip_pinctrl_child_count(struct rockchip_pinctrl * info,struct device_node * np)2466 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2467 struct device_node *np)
2468 {
2469 struct device_node *child;
2470
2471 for_each_child_of_node(np, child) {
2472 if (of_match_node(rockchip_bank_match, child))
2473 continue;
2474
2475 info->nfunctions++;
2476 info->ngroups += of_get_child_count(child);
2477 }
2478 }
2479
rockchip_pinctrl_parse_groups(struct device_node * np,struct rockchip_pin_group * grp,struct rockchip_pinctrl * info,u32 index)2480 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2481 struct rockchip_pin_group *grp,
2482 struct rockchip_pinctrl *info,
2483 u32 index)
2484 {
2485 struct rockchip_pin_bank *bank;
2486 int size;
2487 const __be32 *list;
2488 int num;
2489 int i, j;
2490 int ret;
2491
2492 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2493
2494 /* Initialise group */
2495 grp->name = np->name;
2496
2497 /*
2498 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2499 * do sanity check and calculate pins number
2500 */
2501 list = of_get_property(np, "rockchip,pins", &size);
2502 /* we do not check return since it's safe node passed down */
2503 size /= sizeof(*list);
2504 if (!size || size % 4) {
2505 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2506 return -EINVAL;
2507 }
2508
2509 grp->npins = size / 4;
2510
2511 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2512 GFP_KERNEL);
2513 grp->data = devm_kcalloc(info->dev,
2514 grp->npins,
2515 sizeof(struct rockchip_pin_config),
2516 GFP_KERNEL);
2517 if (!grp->pins || !grp->data)
2518 return -ENOMEM;
2519
2520 for (i = 0, j = 0; i < size; i += 4, j++) {
2521 const __be32 *phandle;
2522 struct device_node *np_config;
2523
2524 num = be32_to_cpu(*list++);
2525 bank = bank_num_to_bank(info, num);
2526 if (IS_ERR(bank))
2527 return PTR_ERR(bank);
2528
2529 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2530 grp->data[j].func = be32_to_cpu(*list++);
2531
2532 phandle = list++;
2533 if (!phandle)
2534 return -EINVAL;
2535
2536 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2537 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2538 &grp->data[j].configs, &grp->data[j].nconfigs);
2539 of_node_put(np_config);
2540 if (ret)
2541 return ret;
2542 }
2543
2544 return 0;
2545 }
2546
rockchip_pinctrl_parse_functions(struct device_node * np,struct rockchip_pinctrl * info,u32 index)2547 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2548 struct rockchip_pinctrl *info,
2549 u32 index)
2550 {
2551 struct device_node *child;
2552 struct rockchip_pmx_func *func;
2553 struct rockchip_pin_group *grp;
2554 int ret;
2555 static u32 grp_index;
2556 u32 i = 0;
2557
2558 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2559
2560 func = &info->functions[index];
2561
2562 /* Initialise function */
2563 func->name = np->name;
2564 func->ngroups = of_get_child_count(np);
2565 if (func->ngroups <= 0)
2566 return 0;
2567
2568 func->groups = devm_kcalloc(info->dev,
2569 func->ngroups, sizeof(char *), GFP_KERNEL);
2570 if (!func->groups)
2571 return -ENOMEM;
2572
2573 for_each_child_of_node(np, child) {
2574 func->groups[i] = child->name;
2575 grp = &info->groups[grp_index++];
2576 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2577 if (ret) {
2578 of_node_put(child);
2579 return ret;
2580 }
2581 }
2582
2583 return 0;
2584 }
2585
rockchip_pinctrl_parse_dt(struct platform_device * pdev,struct rockchip_pinctrl * info)2586 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2587 struct rockchip_pinctrl *info)
2588 {
2589 struct device *dev = &pdev->dev;
2590 struct device_node *np = dev->of_node;
2591 struct device_node *child;
2592 int ret;
2593 int i;
2594
2595 rockchip_pinctrl_child_count(info, np);
2596
2597 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2598 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2599
2600 info->functions = devm_kcalloc(dev,
2601 info->nfunctions,
2602 sizeof(struct rockchip_pmx_func),
2603 GFP_KERNEL);
2604 if (!info->functions)
2605 return -EINVAL;
2606
2607 info->groups = devm_kcalloc(dev,
2608 info->ngroups,
2609 sizeof(struct rockchip_pin_group),
2610 GFP_KERNEL);
2611 if (!info->groups)
2612 return -EINVAL;
2613
2614 i = 0;
2615
2616 for_each_child_of_node(np, child) {
2617 if (of_match_node(rockchip_bank_match, child))
2618 continue;
2619
2620 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2621 if (ret) {
2622 dev_err(&pdev->dev, "failed to parse function\n");
2623 of_node_put(child);
2624 return ret;
2625 }
2626 }
2627
2628 return 0;
2629 }
2630
rockchip_pinctrl_register(struct platform_device * pdev,struct rockchip_pinctrl * info)2631 static int rockchip_pinctrl_register(struct platform_device *pdev,
2632 struct rockchip_pinctrl *info)
2633 {
2634 struct pinctrl_desc *ctrldesc = &info->pctl;
2635 struct pinctrl_pin_desc *pindesc, *pdesc;
2636 struct rockchip_pin_bank *pin_bank;
2637 int pin, bank, ret;
2638 int k;
2639
2640 ctrldesc->name = "rockchip-pinctrl";
2641 ctrldesc->owner = THIS_MODULE;
2642 ctrldesc->pctlops = &rockchip_pctrl_ops;
2643 ctrldesc->pmxops = &rockchip_pmx_ops;
2644 ctrldesc->confops = &rockchip_pinconf_ops;
2645
2646 pindesc = devm_kcalloc(&pdev->dev,
2647 info->ctrl->nr_pins, sizeof(*pindesc),
2648 GFP_KERNEL);
2649 if (!pindesc)
2650 return -ENOMEM;
2651
2652 ctrldesc->pins = pindesc;
2653 ctrldesc->npins = info->ctrl->nr_pins;
2654
2655 pdesc = pindesc;
2656 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2657 pin_bank = &info->ctrl->pin_banks[bank];
2658 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2659 pdesc->number = k;
2660 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2661 pin_bank->name, pin);
2662 pdesc++;
2663 }
2664 }
2665
2666 ret = rockchip_pinctrl_parse_dt(pdev, info);
2667 if (ret)
2668 return ret;
2669
2670 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
2671 if (IS_ERR(info->pctl_dev)) {
2672 dev_err(&pdev->dev, "could not register pinctrl driver\n");
2673 return PTR_ERR(info->pctl_dev);
2674 }
2675
2676 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2677 pin_bank = &info->ctrl->pin_banks[bank];
2678 pin_bank->grange.name = pin_bank->name;
2679 pin_bank->grange.id = bank;
2680 pin_bank->grange.pin_base = pin_bank->pin_base;
2681 pin_bank->grange.base = pin_bank->gpio_chip.base;
2682 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2683 pin_bank->grange.gc = &pin_bank->gpio_chip;
2684 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2685 }
2686
2687 return 0;
2688 }
2689
2690 /*
2691 * GPIO handling
2692 */
2693
rockchip_gpio_set(struct gpio_chip * gc,unsigned offset,int value)2694 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2695 {
2696 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2697 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2698 unsigned long flags;
2699 u32 data;
2700
2701 clk_enable(bank->clk);
2702 raw_spin_lock_irqsave(&bank->slock, flags);
2703
2704 data = readl(reg);
2705 data &= ~BIT(offset);
2706 if (value)
2707 data |= BIT(offset);
2708 writel(data, reg);
2709
2710 raw_spin_unlock_irqrestore(&bank->slock, flags);
2711 clk_disable(bank->clk);
2712 }
2713
2714 /*
2715 * Returns the level of the pin for input direction and setting of the DR
2716 * register for output gpios.
2717 */
rockchip_gpio_get(struct gpio_chip * gc,unsigned offset)2718 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2719 {
2720 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2721 u32 data;
2722
2723 clk_enable(bank->clk);
2724 data = readl(bank->reg_base + GPIO_EXT_PORT);
2725 clk_disable(bank->clk);
2726 data >>= offset;
2727 data &= 1;
2728 return data;
2729 }
2730
2731 /*
2732 * gpiolib gpio_direction_input callback function. The setting of the pin
2733 * mux function as 'gpio input' will be handled by the pinctrl subsystem
2734 * interface.
2735 */
rockchip_gpio_direction_input(struct gpio_chip * gc,unsigned offset)2736 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2737 {
2738 return pinctrl_gpio_direction_input(gc->base + offset);
2739 }
2740
2741 /*
2742 * gpiolib gpio_direction_output callback function. The setting of the pin
2743 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2744 * interface.
2745 */
rockchip_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)2746 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2747 unsigned offset, int value)
2748 {
2749 rockchip_gpio_set(gc, offset, value);
2750 return pinctrl_gpio_direction_output(gc->base + offset);
2751 }
2752
rockchip_gpio_set_debounce(struct gpio_chip * gc,unsigned int offset,bool enable)2753 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
2754 unsigned int offset, bool enable)
2755 {
2756 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2757 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
2758 unsigned long flags;
2759 u32 data;
2760
2761 clk_enable(bank->clk);
2762 raw_spin_lock_irqsave(&bank->slock, flags);
2763
2764 data = readl(reg);
2765 if (enable)
2766 data |= BIT(offset);
2767 else
2768 data &= ~BIT(offset);
2769 writel(data, reg);
2770
2771 raw_spin_unlock_irqrestore(&bank->slock, flags);
2772 clk_disable(bank->clk);
2773 }
2774
2775 /*
2776 * gpiolib set_config callback function. The setting of the pin
2777 * mux function as 'gpio output' will be handled by the pinctrl subsystem
2778 * interface.
2779 */
rockchip_gpio_set_config(struct gpio_chip * gc,unsigned int offset,unsigned long config)2780 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
2781 unsigned long config)
2782 {
2783 enum pin_config_param param = pinconf_to_config_param(config);
2784
2785 switch (param) {
2786 case PIN_CONFIG_INPUT_DEBOUNCE:
2787 rockchip_gpio_set_debounce(gc, offset, true);
2788 /*
2789 * Rockchip's gpio could only support up to one period
2790 * of the debounce clock(pclk), which is far away from
2791 * satisftying the requirement, as pclk is usually near
2792 * 100MHz shared by all peripherals. So the fact is it
2793 * has crippled debounce capability could only be useful
2794 * to prevent any spurious glitches from waking up the system
2795 * if the gpio is conguired as wakeup interrupt source. Let's
2796 * still return -ENOTSUPP as before, to make sure the caller
2797 * of gpiod_set_debounce won't change its behaviour.
2798 */
2799 return -ENOTSUPP;
2800 default:
2801 return -ENOTSUPP;
2802 }
2803 }
2804
2805 /*
2806 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2807 * and a virtual IRQ, if not already present.
2808 */
rockchip_gpio_to_irq(struct gpio_chip * gc,unsigned offset)2809 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2810 {
2811 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2812 unsigned int virq;
2813
2814 if (!bank->domain)
2815 return -ENXIO;
2816
2817 clk_enable(bank->clk);
2818 virq = irq_create_mapping(bank->domain, offset);
2819 clk_disable(bank->clk);
2820
2821 return (virq) ? : -ENXIO;
2822 }
2823
2824 static const struct gpio_chip rockchip_gpiolib_chip = {
2825 .request = gpiochip_generic_request,
2826 .free = gpiochip_generic_free,
2827 .set = rockchip_gpio_set,
2828 .get = rockchip_gpio_get,
2829 .get_direction = rockchip_gpio_get_direction,
2830 .direction_input = rockchip_gpio_direction_input,
2831 .direction_output = rockchip_gpio_direction_output,
2832 .set_config = rockchip_gpio_set_config,
2833 .to_irq = rockchip_gpio_to_irq,
2834 .owner = THIS_MODULE,
2835 };
2836
2837 /*
2838 * Interrupt handling
2839 */
2840
rockchip_irq_demux(struct irq_desc * desc)2841 static void rockchip_irq_demux(struct irq_desc *desc)
2842 {
2843 struct irq_chip *chip = irq_desc_get_chip(desc);
2844 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2845 u32 pend;
2846
2847 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2848
2849 chained_irq_enter(chip, desc);
2850
2851 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2852
2853 while (pend) {
2854 unsigned int irq, virq;
2855
2856 irq = __ffs(pend);
2857 pend &= ~BIT(irq);
2858 virq = irq_linear_revmap(bank->domain, irq);
2859
2860 if (!virq) {
2861 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2862 continue;
2863 }
2864
2865 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2866
2867 /*
2868 * Triggering IRQ on both rising and falling edge
2869 * needs manual intervention.
2870 */
2871 if (bank->toggle_edge_mode & BIT(irq)) {
2872 u32 data, data_old, polarity;
2873 unsigned long flags;
2874
2875 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2876 do {
2877 raw_spin_lock_irqsave(&bank->slock, flags);
2878
2879 polarity = readl_relaxed(bank->reg_base +
2880 GPIO_INT_POLARITY);
2881 if (data & BIT(irq))
2882 polarity &= ~BIT(irq);
2883 else
2884 polarity |= BIT(irq);
2885 writel(polarity,
2886 bank->reg_base + GPIO_INT_POLARITY);
2887
2888 raw_spin_unlock_irqrestore(&bank->slock, flags);
2889
2890 data_old = data;
2891 data = readl_relaxed(bank->reg_base +
2892 GPIO_EXT_PORT);
2893 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2894 }
2895
2896 generic_handle_irq(virq);
2897 }
2898
2899 chained_irq_exit(chip, desc);
2900 }
2901
rockchip_irq_set_type(struct irq_data * d,unsigned int type)2902 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2903 {
2904 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2905 struct rockchip_pin_bank *bank = gc->private;
2906 u32 mask = BIT(d->hwirq);
2907 u32 polarity;
2908 u32 level;
2909 u32 data;
2910 unsigned long flags;
2911 int ret;
2912
2913 /* make sure the pin is configured as gpio input */
2914 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2915 if (ret < 0)
2916 return ret;
2917
2918 clk_enable(bank->clk);
2919 raw_spin_lock_irqsave(&bank->slock, flags);
2920
2921 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2922 data &= ~mask;
2923 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2924
2925 raw_spin_unlock_irqrestore(&bank->slock, flags);
2926
2927 if (type & IRQ_TYPE_EDGE_BOTH)
2928 irq_set_handler_locked(d, handle_edge_irq);
2929 else
2930 irq_set_handler_locked(d, handle_level_irq);
2931
2932 raw_spin_lock_irqsave(&bank->slock, flags);
2933 irq_gc_lock(gc);
2934
2935 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2936 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2937
2938 switch (type) {
2939 case IRQ_TYPE_EDGE_BOTH:
2940 bank->toggle_edge_mode |= mask;
2941 level |= mask;
2942
2943 /*
2944 * Determine gpio state. If 1 next interrupt should be falling
2945 * otherwise rising.
2946 */
2947 data = readl(bank->reg_base + GPIO_EXT_PORT);
2948 if (data & mask)
2949 polarity &= ~mask;
2950 else
2951 polarity |= mask;
2952 break;
2953 case IRQ_TYPE_EDGE_RISING:
2954 bank->toggle_edge_mode &= ~mask;
2955 level |= mask;
2956 polarity |= mask;
2957 break;
2958 case IRQ_TYPE_EDGE_FALLING:
2959 bank->toggle_edge_mode &= ~mask;
2960 level |= mask;
2961 polarity &= ~mask;
2962 break;
2963 case IRQ_TYPE_LEVEL_HIGH:
2964 bank->toggle_edge_mode &= ~mask;
2965 level &= ~mask;
2966 polarity |= mask;
2967 break;
2968 case IRQ_TYPE_LEVEL_LOW:
2969 bank->toggle_edge_mode &= ~mask;
2970 level &= ~mask;
2971 polarity &= ~mask;
2972 break;
2973 default:
2974 irq_gc_unlock(gc);
2975 raw_spin_unlock_irqrestore(&bank->slock, flags);
2976 clk_disable(bank->clk);
2977 return -EINVAL;
2978 }
2979
2980 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2981 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2982
2983 irq_gc_unlock(gc);
2984 raw_spin_unlock_irqrestore(&bank->slock, flags);
2985 clk_disable(bank->clk);
2986
2987 return 0;
2988 }
2989
rockchip_irq_suspend(struct irq_data * d)2990 static void rockchip_irq_suspend(struct irq_data *d)
2991 {
2992 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2993 struct rockchip_pin_bank *bank = gc->private;
2994
2995 clk_enable(bank->clk);
2996 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2997 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2998 clk_disable(bank->clk);
2999 }
3000
rockchip_irq_resume(struct irq_data * d)3001 static void rockchip_irq_resume(struct irq_data *d)
3002 {
3003 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3004 struct rockchip_pin_bank *bank = gc->private;
3005
3006 clk_enable(bank->clk);
3007 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3008 clk_disable(bank->clk);
3009 }
3010
rockchip_irq_enable(struct irq_data * d)3011 static void rockchip_irq_enable(struct irq_data *d)
3012 {
3013 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3014 struct rockchip_pin_bank *bank = gc->private;
3015
3016 clk_enable(bank->clk);
3017 irq_gc_mask_clr_bit(d);
3018 }
3019
rockchip_irq_disable(struct irq_data * d)3020 static void rockchip_irq_disable(struct irq_data *d)
3021 {
3022 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3023 struct rockchip_pin_bank *bank = gc->private;
3024
3025 irq_gc_mask_set_bit(d);
3026 clk_disable(bank->clk);
3027 }
3028
rockchip_interrupts_register(struct platform_device * pdev,struct rockchip_pinctrl * info)3029 static int rockchip_interrupts_register(struct platform_device *pdev,
3030 struct rockchip_pinctrl *info)
3031 {
3032 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3033 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3034 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3035 struct irq_chip_generic *gc;
3036 int ret;
3037 int i, j;
3038
3039 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3040 if (!bank->valid) {
3041 dev_warn(&pdev->dev, "bank %s is not valid\n",
3042 bank->name);
3043 continue;
3044 }
3045
3046 ret = clk_enable(bank->clk);
3047 if (ret) {
3048 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3049 bank->name);
3050 continue;
3051 }
3052
3053 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3054 &irq_generic_chip_ops, NULL);
3055 if (!bank->domain) {
3056 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3057 bank->name);
3058 clk_disable(bank->clk);
3059 continue;
3060 }
3061
3062 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3063 "rockchip_gpio_irq", handle_level_irq,
3064 clr, 0, IRQ_GC_INIT_MASK_CACHE);
3065 if (ret) {
3066 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3067 bank->name);
3068 irq_domain_remove(bank->domain);
3069 clk_disable(bank->clk);
3070 continue;
3071 }
3072
3073 /*
3074 * Linux assumes that all interrupts start out disabled/masked.
3075 * Our driver only uses the concept of masked and always keeps
3076 * things enabled, so for us that's all masked and all enabled.
3077 */
3078 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3079 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3080
3081 gc = irq_get_domain_generic_chip(bank->domain, 0);
3082 gc->reg_base = bank->reg_base;
3083 gc->private = bank;
3084 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3085 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3086 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3087 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3088 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3089 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3090 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3091 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3092 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3093 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3094 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3095 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3096
3097 irq_set_chained_handler_and_data(bank->irq,
3098 rockchip_irq_demux, bank);
3099
3100 /* map the gpio irqs here, when the clock is still running */
3101 for (j = 0 ; j < 32 ; j++)
3102 irq_create_mapping(bank->domain, j);
3103
3104 clk_disable(bank->clk);
3105 }
3106
3107 return 0;
3108 }
3109
rockchip_gpiolib_register(struct platform_device * pdev,struct rockchip_pinctrl * info)3110 static int rockchip_gpiolib_register(struct platform_device *pdev,
3111 struct rockchip_pinctrl *info)
3112 {
3113 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3114 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3115 struct gpio_chip *gc;
3116 int ret;
3117 int i;
3118
3119 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3120 if (!bank->valid) {
3121 dev_warn(&pdev->dev, "bank %s is not valid\n",
3122 bank->name);
3123 continue;
3124 }
3125
3126 bank->gpio_chip = rockchip_gpiolib_chip;
3127
3128 gc = &bank->gpio_chip;
3129 gc->base = bank->pin_base;
3130 gc->ngpio = bank->nr_pins;
3131 gc->parent = &pdev->dev;
3132 gc->of_node = bank->of_node;
3133 gc->label = bank->name;
3134
3135 ret = gpiochip_add_data(gc, bank);
3136 if (ret) {
3137 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3138 gc->label, ret);
3139 goto fail;
3140 }
3141 }
3142
3143 rockchip_interrupts_register(pdev, info);
3144
3145 return 0;
3146
3147 fail:
3148 for (--i, --bank; i >= 0; --i, --bank) {
3149 if (!bank->valid)
3150 continue;
3151 gpiochip_remove(&bank->gpio_chip);
3152 }
3153 return ret;
3154 }
3155
rockchip_gpiolib_unregister(struct platform_device * pdev,struct rockchip_pinctrl * info)3156 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3157 struct rockchip_pinctrl *info)
3158 {
3159 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3160 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3161 int i;
3162
3163 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3164 if (!bank->valid)
3165 continue;
3166 gpiochip_remove(&bank->gpio_chip);
3167 }
3168
3169 return 0;
3170 }
3171
rockchip_get_bank_data(struct rockchip_pin_bank * bank,struct rockchip_pinctrl * info)3172 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3173 struct rockchip_pinctrl *info)
3174 {
3175 struct resource res;
3176 void __iomem *base;
3177
3178 if (of_address_to_resource(bank->of_node, 0, &res)) {
3179 dev_err(info->dev, "cannot find IO resource for bank\n");
3180 return -ENOENT;
3181 }
3182
3183 bank->reg_base = devm_ioremap_resource(info->dev, &res);
3184 if (IS_ERR(bank->reg_base))
3185 return PTR_ERR(bank->reg_base);
3186
3187 /*
3188 * special case, where parts of the pull setting-registers are
3189 * part of the PMU register space
3190 */
3191 if (of_device_is_compatible(bank->of_node,
3192 "rockchip,rk3188-gpio-bank0")) {
3193 struct device_node *node;
3194
3195 node = of_parse_phandle(bank->of_node->parent,
3196 "rockchip,pmu", 0);
3197 if (!node) {
3198 if (of_address_to_resource(bank->of_node, 1, &res)) {
3199 dev_err(info->dev, "cannot find IO resource for bank\n");
3200 return -ENOENT;
3201 }
3202
3203 base = devm_ioremap_resource(info->dev, &res);
3204 if (IS_ERR(base))
3205 return PTR_ERR(base);
3206 rockchip_regmap_config.max_register =
3207 resource_size(&res) - 4;
3208 rockchip_regmap_config.name =
3209 "rockchip,rk3188-gpio-bank0-pull";
3210 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3211 base,
3212 &rockchip_regmap_config);
3213 }
3214 of_node_put(node);
3215 }
3216
3217 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3218
3219 bank->clk = of_clk_get(bank->of_node, 0);
3220 if (IS_ERR(bank->clk))
3221 return PTR_ERR(bank->clk);
3222
3223 return clk_prepare(bank->clk);
3224 }
3225
3226 static const struct of_device_id rockchip_pinctrl_dt_match[];
3227
3228 /* retrieve the soc specific data */
rockchip_pinctrl_get_soc_data(struct rockchip_pinctrl * d,struct platform_device * pdev)3229 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3230 struct rockchip_pinctrl *d,
3231 struct platform_device *pdev)
3232 {
3233 const struct of_device_id *match;
3234 struct device_node *node = pdev->dev.of_node;
3235 struct device_node *np;
3236 struct rockchip_pin_ctrl *ctrl;
3237 struct rockchip_pin_bank *bank;
3238 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3239
3240 match = of_match_node(rockchip_pinctrl_dt_match, node);
3241 ctrl = (struct rockchip_pin_ctrl *)match->data;
3242
3243 for_each_child_of_node(node, np) {
3244 if (!of_find_property(np, "gpio-controller", NULL))
3245 continue;
3246
3247 bank = ctrl->pin_banks;
3248 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3249 if (!strcmp(bank->name, np->name)) {
3250 bank->of_node = np;
3251
3252 if (!rockchip_get_bank_data(bank, d))
3253 bank->valid = true;
3254
3255 break;
3256 }
3257 }
3258 }
3259
3260 grf_offs = ctrl->grf_mux_offset;
3261 pmu_offs = ctrl->pmu_mux_offset;
3262 drv_pmu_offs = ctrl->pmu_drv_offset;
3263 drv_grf_offs = ctrl->grf_drv_offset;
3264 bank = ctrl->pin_banks;
3265 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3266 int bank_pins = 0;
3267
3268 raw_spin_lock_init(&bank->slock);
3269 bank->drvdata = d;
3270 bank->pin_base = ctrl->nr_pins;
3271 ctrl->nr_pins += bank->nr_pins;
3272
3273 /* calculate iomux and drv offsets */
3274 for (j = 0; j < 4; j++) {
3275 struct rockchip_iomux *iom = &bank->iomux[j];
3276 struct rockchip_drv *drv = &bank->drv[j];
3277 int inc;
3278
3279 if (bank_pins >= bank->nr_pins)
3280 break;
3281
3282 /* preset iomux offset value, set new start value */
3283 if (iom->offset >= 0) {
3284 if (iom->type & IOMUX_SOURCE_PMU)
3285 pmu_offs = iom->offset;
3286 else
3287 grf_offs = iom->offset;
3288 } else { /* set current iomux offset */
3289 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3290 pmu_offs : grf_offs;
3291 }
3292
3293 /* preset drv offset value, set new start value */
3294 if (drv->offset >= 0) {
3295 if (iom->type & IOMUX_SOURCE_PMU)
3296 drv_pmu_offs = drv->offset;
3297 else
3298 drv_grf_offs = drv->offset;
3299 } else { /* set current drv offset */
3300 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3301 drv_pmu_offs : drv_grf_offs;
3302 }
3303
3304 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3305 i, j, iom->offset, drv->offset);
3306
3307 /*
3308 * Increase offset according to iomux width.
3309 * 4bit iomux'es are spread over two registers.
3310 */
3311 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3312 IOMUX_WIDTH_3BIT)) ? 8 : 4;
3313 if (iom->type & IOMUX_SOURCE_PMU)
3314 pmu_offs += inc;
3315 else
3316 grf_offs += inc;
3317
3318 /*
3319 * Increase offset according to drv width.
3320 * 3bit drive-strenth'es are spread over two registers.
3321 */
3322 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3323 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3324 inc = 8;
3325 else
3326 inc = 4;
3327
3328 if (iom->type & IOMUX_SOURCE_PMU)
3329 drv_pmu_offs += inc;
3330 else
3331 drv_grf_offs += inc;
3332
3333 bank_pins += 8;
3334 }
3335
3336 /* calculate the per-bank recalced_mask */
3337 for (j = 0; j < ctrl->niomux_recalced; j++) {
3338 int pin = 0;
3339
3340 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3341 pin = ctrl->iomux_recalced[j].pin;
3342 bank->recalced_mask |= BIT(pin);
3343 }
3344 }
3345
3346 /* calculate the per-bank route_mask */
3347 for (j = 0; j < ctrl->niomux_routes; j++) {
3348 int pin = 0;
3349
3350 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3351 pin = ctrl->iomux_routes[j].pin;
3352 bank->route_mask |= BIT(pin);
3353 }
3354 }
3355 }
3356
3357 return ctrl;
3358 }
3359
3360 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3361 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3362
3363 static u32 rk3288_grf_gpio6c_iomux;
3364
rockchip_pinctrl_suspend(struct device * dev)3365 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3366 {
3367 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3368 int ret = pinctrl_force_sleep(info->pctl_dev);
3369
3370 if (ret)
3371 return ret;
3372
3373 /*
3374 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3375 * the setting here, and restore it at resume.
3376 */
3377 if (info->ctrl->type == RK3288) {
3378 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3379 &rk3288_grf_gpio6c_iomux);
3380 if (ret) {
3381 pinctrl_force_default(info->pctl_dev);
3382 return ret;
3383 }
3384 }
3385
3386 return 0;
3387 }
3388
rockchip_pinctrl_resume(struct device * dev)3389 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3390 {
3391 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3392 int ret;
3393
3394 if (info->ctrl->type == RK3288) {
3395 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3396 rk3288_grf_gpio6c_iomux |
3397 GPIO6C6_SEL_WRITE_ENABLE);
3398 if (ret)
3399 return ret;
3400 }
3401
3402 return pinctrl_force_default(info->pctl_dev);
3403 }
3404
3405 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3406 rockchip_pinctrl_resume);
3407
rockchip_pinctrl_probe(struct platform_device * pdev)3408 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3409 {
3410 struct rockchip_pinctrl *info;
3411 struct device *dev = &pdev->dev;
3412 struct rockchip_pin_ctrl *ctrl;
3413 struct device_node *np = pdev->dev.of_node, *node;
3414 struct resource *res;
3415 void __iomem *base;
3416 int ret;
3417
3418 if (!dev->of_node) {
3419 dev_err(dev, "device tree node not found\n");
3420 return -ENODEV;
3421 }
3422
3423 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3424 if (!info)
3425 return -ENOMEM;
3426
3427 info->dev = dev;
3428
3429 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3430 if (!ctrl) {
3431 dev_err(dev, "driver data not available\n");
3432 return -EINVAL;
3433 }
3434 info->ctrl = ctrl;
3435
3436 node = of_parse_phandle(np, "rockchip,grf", 0);
3437 if (node) {
3438 info->regmap_base = syscon_node_to_regmap(node);
3439 of_node_put(node);
3440 if (IS_ERR(info->regmap_base))
3441 return PTR_ERR(info->regmap_base);
3442 } else {
3443 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3444 base = devm_ioremap_resource(&pdev->dev, res);
3445 if (IS_ERR(base))
3446 return PTR_ERR(base);
3447
3448 rockchip_regmap_config.max_register = resource_size(res) - 4;
3449 rockchip_regmap_config.name = "rockchip,pinctrl";
3450 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3451 &rockchip_regmap_config);
3452
3453 /* to check for the old dt-bindings */
3454 info->reg_size = resource_size(res);
3455
3456 /* Honor the old binding, with pull registers as 2nd resource */
3457 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3458 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3459 base = devm_ioremap_resource(&pdev->dev, res);
3460 if (IS_ERR(base))
3461 return PTR_ERR(base);
3462
3463 rockchip_regmap_config.max_register =
3464 resource_size(res) - 4;
3465 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3466 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3467 base,
3468 &rockchip_regmap_config);
3469 }
3470 }
3471
3472 /* try to find the optional reference to the pmu syscon */
3473 node = of_parse_phandle(np, "rockchip,pmu", 0);
3474 if (node) {
3475 info->regmap_pmu = syscon_node_to_regmap(node);
3476 of_node_put(node);
3477 if (IS_ERR(info->regmap_pmu))
3478 return PTR_ERR(info->regmap_pmu);
3479 }
3480
3481 ret = rockchip_gpiolib_register(pdev, info);
3482 if (ret)
3483 return ret;
3484
3485 ret = rockchip_pinctrl_register(pdev, info);
3486 if (ret) {
3487 rockchip_gpiolib_unregister(pdev, info);
3488 return ret;
3489 }
3490
3491 platform_set_drvdata(pdev, info);
3492
3493 return 0;
3494 }
3495
3496 static struct rockchip_pin_bank px30_pin_banks[] = {
3497 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3498 IOMUX_SOURCE_PMU,
3499 IOMUX_SOURCE_PMU,
3500 IOMUX_SOURCE_PMU
3501 ),
3502 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3503 IOMUX_WIDTH_4BIT,
3504 IOMUX_WIDTH_4BIT,
3505 IOMUX_WIDTH_4BIT
3506 ),
3507 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3508 IOMUX_WIDTH_4BIT,
3509 IOMUX_WIDTH_4BIT,
3510 IOMUX_WIDTH_4BIT
3511 ),
3512 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3513 IOMUX_WIDTH_4BIT,
3514 IOMUX_WIDTH_4BIT,
3515 IOMUX_WIDTH_4BIT
3516 ),
3517 };
3518
3519 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3520 .pin_banks = px30_pin_banks,
3521 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3522 .label = "PX30-GPIO",
3523 .type = PX30,
3524 .grf_mux_offset = 0x0,
3525 .pmu_mux_offset = 0x0,
3526 .iomux_routes = px30_mux_route_data,
3527 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3528 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3529 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3530 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3531 };
3532
3533 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3534 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3535 IOMUX_SOURCE_PMU,
3536 IOMUX_SOURCE_PMU,
3537 IOMUX_SOURCE_PMU),
3538 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3539 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3540 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3541 };
3542
3543 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3544 .pin_banks = rv1108_pin_banks,
3545 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3546 .label = "RV1108-GPIO",
3547 .type = RV1108,
3548 .grf_mux_offset = 0x10,
3549 .pmu_mux_offset = 0x0,
3550 .iomux_recalced = rv1108_mux_recalced_data,
3551 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3552 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3553 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3554 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3555 };
3556
3557 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3558 PIN_BANK(0, 32, "gpio0"),
3559 PIN_BANK(1, 32, "gpio1"),
3560 PIN_BANK(2, 32, "gpio2"),
3561 PIN_BANK(3, 32, "gpio3"),
3562 };
3563
3564 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3565 .pin_banks = rk2928_pin_banks,
3566 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3567 .label = "RK2928-GPIO",
3568 .type = RK2928,
3569 .grf_mux_offset = 0xa8,
3570 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3571 };
3572
3573 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3574 PIN_BANK(0, 32, "gpio0"),
3575 PIN_BANK(1, 32, "gpio1"),
3576 PIN_BANK(2, 32, "gpio2"),
3577 };
3578
3579 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3580 .pin_banks = rk3036_pin_banks,
3581 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3582 .label = "RK3036-GPIO",
3583 .type = RK2928,
3584 .grf_mux_offset = 0xa8,
3585 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3586 };
3587
3588 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3589 PIN_BANK(0, 32, "gpio0"),
3590 PIN_BANK(1, 32, "gpio1"),
3591 PIN_BANK(2, 32, "gpio2"),
3592 PIN_BANK(3, 32, "gpio3"),
3593 PIN_BANK(4, 32, "gpio4"),
3594 PIN_BANK(6, 16, "gpio6"),
3595 };
3596
3597 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3598 .pin_banks = rk3066a_pin_banks,
3599 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3600 .label = "RK3066a-GPIO",
3601 .type = RK2928,
3602 .grf_mux_offset = 0xa8,
3603 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3604 };
3605
3606 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3607 PIN_BANK(0, 32, "gpio0"),
3608 PIN_BANK(1, 32, "gpio1"),
3609 PIN_BANK(2, 32, "gpio2"),
3610 PIN_BANK(3, 32, "gpio3"),
3611 };
3612
3613 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3614 .pin_banks = rk3066b_pin_banks,
3615 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3616 .label = "RK3066b-GPIO",
3617 .type = RK3066B,
3618 .grf_mux_offset = 0x60,
3619 };
3620
3621 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3622 PIN_BANK(0, 32, "gpio0"),
3623 PIN_BANK(1, 32, "gpio1"),
3624 PIN_BANK(2, 32, "gpio2"),
3625 PIN_BANK(3, 32, "gpio3"),
3626 };
3627
3628 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3629 .pin_banks = rk3128_pin_banks,
3630 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3631 .label = "RK3128-GPIO",
3632 .type = RK3128,
3633 .grf_mux_offset = 0xa8,
3634 .iomux_recalced = rk3128_mux_recalced_data,
3635 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3636 .iomux_routes = rk3128_mux_route_data,
3637 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3638 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3639 };
3640
3641 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3642 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3643 PIN_BANK(1, 32, "gpio1"),
3644 PIN_BANK(2, 32, "gpio2"),
3645 PIN_BANK(3, 32, "gpio3"),
3646 };
3647
3648 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3649 .pin_banks = rk3188_pin_banks,
3650 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3651 .label = "RK3188-GPIO",
3652 .type = RK3188,
3653 .grf_mux_offset = 0x60,
3654 .iomux_routes = rk3188_mux_route_data,
3655 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
3656 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3657 };
3658
3659 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3660 PIN_BANK(0, 32, "gpio0"),
3661 PIN_BANK(1, 32, "gpio1"),
3662 PIN_BANK(2, 32, "gpio2"),
3663 PIN_BANK(3, 32, "gpio3"),
3664 };
3665
3666 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3667 .pin_banks = rk3228_pin_banks,
3668 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3669 .label = "RK3228-GPIO",
3670 .type = RK3288,
3671 .grf_mux_offset = 0x0,
3672 .iomux_routes = rk3228_mux_route_data,
3673 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3674 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3675 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3676 };
3677
3678 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3679 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3680 IOMUX_SOURCE_PMU,
3681 IOMUX_SOURCE_PMU,
3682 IOMUX_UNROUTED
3683 ),
3684 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3685 IOMUX_UNROUTED,
3686 IOMUX_UNROUTED,
3687 0
3688 ),
3689 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3690 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3691 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3692 IOMUX_WIDTH_4BIT,
3693 0,
3694 0
3695 ),
3696 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3697 0,
3698 0,
3699 IOMUX_UNROUTED
3700 ),
3701 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3702 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3703 0,
3704 IOMUX_WIDTH_4BIT,
3705 IOMUX_UNROUTED
3706 ),
3707 PIN_BANK(8, 16, "gpio8"),
3708 };
3709
3710 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3711 .pin_banks = rk3288_pin_banks,
3712 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3713 .label = "RK3288-GPIO",
3714 .type = RK3288,
3715 .grf_mux_offset = 0x0,
3716 .pmu_mux_offset = 0x84,
3717 .iomux_routes = rk3288_mux_route_data,
3718 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3719 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3720 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3721 };
3722
3723 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3724 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3725 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3726 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3727 IOMUX_WIDTH_3BIT,
3728 IOMUX_WIDTH_3BIT,
3729 0),
3730 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3731 IOMUX_WIDTH_3BIT,
3732 IOMUX_WIDTH_3BIT,
3733 0,
3734 0),
3735 };
3736
3737 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3738 .pin_banks = rk3328_pin_banks,
3739 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3740 .label = "RK3328-GPIO",
3741 .type = RK3288,
3742 .grf_mux_offset = 0x0,
3743 .iomux_recalced = rk3328_mux_recalced_data,
3744 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3745 .iomux_routes = rk3328_mux_route_data,
3746 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3747 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3748 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3749 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3750 };
3751
3752 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3753 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3754 IOMUX_SOURCE_PMU,
3755 IOMUX_SOURCE_PMU,
3756 IOMUX_SOURCE_PMU
3757 ),
3758 PIN_BANK(1, 32, "gpio1"),
3759 PIN_BANK(2, 32, "gpio2"),
3760 PIN_BANK(3, 32, "gpio3"),
3761 };
3762
3763 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3764 .pin_banks = rk3368_pin_banks,
3765 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3766 .label = "RK3368-GPIO",
3767 .type = RK3368,
3768 .grf_mux_offset = 0x0,
3769 .pmu_mux_offset = 0x0,
3770 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3771 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3772 };
3773
3774 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3775 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3776 IOMUX_SOURCE_PMU,
3777 IOMUX_SOURCE_PMU,
3778 IOMUX_SOURCE_PMU,
3779 IOMUX_SOURCE_PMU,
3780 DRV_TYPE_IO_1V8_ONLY,
3781 DRV_TYPE_IO_1V8_ONLY,
3782 DRV_TYPE_IO_DEFAULT,
3783 DRV_TYPE_IO_DEFAULT,
3784 0x80,
3785 0x88,
3786 -1,
3787 -1,
3788 PULL_TYPE_IO_1V8_ONLY,
3789 PULL_TYPE_IO_1V8_ONLY,
3790 PULL_TYPE_IO_DEFAULT,
3791 PULL_TYPE_IO_DEFAULT
3792 ),
3793 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3794 IOMUX_SOURCE_PMU,
3795 IOMUX_SOURCE_PMU,
3796 IOMUX_SOURCE_PMU,
3797 DRV_TYPE_IO_1V8_OR_3V0,
3798 DRV_TYPE_IO_1V8_OR_3V0,
3799 DRV_TYPE_IO_1V8_OR_3V0,
3800 DRV_TYPE_IO_1V8_OR_3V0,
3801 0xa0,
3802 0xa8,
3803 0xb0,
3804 0xb8
3805 ),
3806 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3807 DRV_TYPE_IO_1V8_OR_3V0,
3808 DRV_TYPE_IO_1V8_ONLY,
3809 DRV_TYPE_IO_1V8_ONLY,
3810 PULL_TYPE_IO_DEFAULT,
3811 PULL_TYPE_IO_DEFAULT,
3812 PULL_TYPE_IO_1V8_ONLY,
3813 PULL_TYPE_IO_1V8_ONLY
3814 ),
3815 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3816 DRV_TYPE_IO_3V3_ONLY,
3817 DRV_TYPE_IO_3V3_ONLY,
3818 DRV_TYPE_IO_1V8_OR_3V0
3819 ),
3820 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3821 DRV_TYPE_IO_1V8_3V0_AUTO,
3822 DRV_TYPE_IO_1V8_OR_3V0,
3823 DRV_TYPE_IO_1V8_OR_3V0
3824 ),
3825 };
3826
3827 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3828 .pin_banks = rk3399_pin_banks,
3829 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3830 .label = "RK3399-GPIO",
3831 .type = RK3399,
3832 .grf_mux_offset = 0xe000,
3833 .pmu_mux_offset = 0x0,
3834 .grf_drv_offset = 0xe100,
3835 .pmu_drv_offset = 0x80,
3836 .iomux_routes = rk3399_mux_route_data,
3837 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3838 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3839 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3840 };
3841
3842 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3843 { .compatible = "rockchip,px30-pinctrl",
3844 .data = &px30_pin_ctrl },
3845 { .compatible = "rockchip,rv1108-pinctrl",
3846 .data = &rv1108_pin_ctrl },
3847 { .compatible = "rockchip,rk2928-pinctrl",
3848 .data = &rk2928_pin_ctrl },
3849 { .compatible = "rockchip,rk3036-pinctrl",
3850 .data = &rk3036_pin_ctrl },
3851 { .compatible = "rockchip,rk3066a-pinctrl",
3852 .data = &rk3066a_pin_ctrl },
3853 { .compatible = "rockchip,rk3066b-pinctrl",
3854 .data = &rk3066b_pin_ctrl },
3855 { .compatible = "rockchip,rk3128-pinctrl",
3856 .data = (void *)&rk3128_pin_ctrl },
3857 { .compatible = "rockchip,rk3188-pinctrl",
3858 .data = &rk3188_pin_ctrl },
3859 { .compatible = "rockchip,rk3228-pinctrl",
3860 .data = &rk3228_pin_ctrl },
3861 { .compatible = "rockchip,rk3288-pinctrl",
3862 .data = &rk3288_pin_ctrl },
3863 { .compatible = "rockchip,rk3328-pinctrl",
3864 .data = &rk3328_pin_ctrl },
3865 { .compatible = "rockchip,rk3368-pinctrl",
3866 .data = &rk3368_pin_ctrl },
3867 { .compatible = "rockchip,rk3399-pinctrl",
3868 .data = &rk3399_pin_ctrl },
3869 {},
3870 };
3871
3872 static struct platform_driver rockchip_pinctrl_driver = {
3873 .probe = rockchip_pinctrl_probe,
3874 .driver = {
3875 .name = "rockchip-pinctrl",
3876 .pm = &rockchip_pinctrl_dev_pm_ops,
3877 .of_match_table = rockchip_pinctrl_dt_match,
3878 },
3879 };
3880
rockchip_pinctrl_drv_register(void)3881 static int __init rockchip_pinctrl_drv_register(void)
3882 {
3883 return platform_driver_register(&rockchip_pinctrl_driver);
3884 }
3885 postcore_initcall(rockchip_pinctrl_drv_register);
3886