1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 */ 5 #ifndef __PINCTRL_MSM_H__ 6 #define __PINCTRL_MSM_H__ 7 8 #include <linux/gpio/driver.h> 9 10 struct pinctrl_pin_desc; 11 12 /** 13 * struct msm_function - a pinmux function 14 * @name: Name of the pinmux function. 15 * @groups: List of pingroups for this function. 16 * @ngroups: Number of entries in @groups. 17 */ 18 struct msm_function { 19 const char *name; 20 const char * const *groups; 21 unsigned ngroups; 22 }; 23 24 /** 25 * struct msm_pingroup - Qualcomm pingroup definition 26 * @name: Name of the pingroup. 27 * @pins: A list of pins assigned to this pingroup. 28 * @npins: Number of entries in @pins. 29 * @funcs: A list of pinmux functions that can be selected for 30 * this group. The index of the selected function is used 31 * for programming the function selector. 32 * Entries should be indices into the groups list of the 33 * struct msm_pinctrl_soc_data. 34 * @ctl_reg: Offset of the register holding control bits for this group. 35 * @io_reg: Offset of the register holding input/output bits for this group. 36 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. 37 * @intr_status_reg: Offset of the register holding the status bits for this group. 38 * @intr_target_reg: Offset of the register specifying routing of the interrupts 39 * from this group. 40 * @mux_bit: Offset in @ctl_reg for the pinmux function selection. 41 * @pull_bit: Offset in @ctl_reg for the bias configuration. 42 * @drv_bit: Offset in @ctl_reg for the drive strength configuration. 43 * @oe_bit: Offset in @ctl_reg for controlling output enable. 44 * @in_bit: Offset in @io_reg for the input bit value. 45 * @out_bit: Offset in @io_reg for the output bit value. 46 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. 47 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 48 * status. 49 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 50 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from 51 * this gpio should get routed to the KPSS processor. 52 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 53 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 54 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 55 * @intr_detection_width: Number of bits used for specifying interrupt type, 56 * Should be 2 for SoCs that can detect both edges in hardware, 57 * otherwise 1. 58 */ 59 struct msm_pingroup { 60 const char *name; 61 const unsigned *pins; 62 unsigned npins; 63 64 unsigned *funcs; 65 unsigned nfuncs; 66 67 u32 ctl_reg; 68 u32 io_reg; 69 u32 intr_cfg_reg; 70 u32 intr_status_reg; 71 u32 intr_target_reg; 72 73 unsigned int tile:2; 74 75 unsigned mux_bit:5; 76 77 unsigned pull_bit:5; 78 unsigned drv_bit:5; 79 80 unsigned oe_bit:5; 81 unsigned in_bit:5; 82 unsigned out_bit:5; 83 84 unsigned intr_enable_bit:5; 85 unsigned intr_status_bit:5; 86 unsigned intr_ack_high:1; 87 88 unsigned intr_target_bit:5; 89 unsigned intr_target_kpss_val:5; 90 unsigned intr_raw_status_bit:5; 91 unsigned intr_polarity_bit:5; 92 unsigned intr_detection_bit:5; 93 unsigned intr_detection_width:5; 94 }; 95 96 /** 97 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins 98 * @gpio: The GPIOs that are wakeup capable 99 * @wakeirq: The interrupt at the always-on interrupt controller 100 */ 101 struct msm_gpio_wakeirq_map { 102 unsigned int gpio; 103 unsigned int wakeirq; 104 }; 105 106 /** 107 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration 108 * @pins: An array describing all pins the pin controller affects. 109 * @npins: The number of entries in @pins. 110 * @functions: An array describing all mux functions the SoC supports. 111 * @nfunctions: The number of entries in @functions. 112 * @groups: An array describing all pin groups the pin SoC supports. 113 * @ngroups: The numbmer of entries in @groups. 114 * @ngpio: The number of pingroups the driver should expose as GPIOs. 115 * @pull_no_keeper: The SoC does not support keeper bias. 116 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM 117 * @nwakeirq_map: The number of entries in @hierarchy_map 118 */ 119 struct msm_pinctrl_soc_data { 120 const struct pinctrl_pin_desc *pins; 121 unsigned npins; 122 const struct msm_function *functions; 123 unsigned nfunctions; 124 const struct msm_pingroup *groups; 125 unsigned ngroups; 126 unsigned ngpios; 127 bool pull_no_keeper; 128 const char *const *tiles; 129 unsigned int ntiles; 130 const int *reserved_gpios; 131 const struct msm_gpio_wakeirq_map *wakeirq_map; 132 unsigned int nwakeirq_map; 133 }; 134 135 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; 136 137 int msm_pinctrl_probe(struct platform_device *pdev, 138 const struct msm_pinctrl_soc_data *soc_data); 139 int msm_pinctrl_remove(struct platform_device *pdev); 140 141 #endif 142