1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
5 *
6 * Limitations:
7 * - The .apply callback doesn't complete the currently running period before
8 * reconfiguring the hardware.
9 * - Each period starts with the inactive part.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/gpio.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pwm.h>
20
21 #include <asm/mach-jz4740/timer.h>
22
23 #define NUM_PWM 8
24
25 struct jz4740_pwm_chip {
26 struct pwm_chip chip;
27 struct clk *clk;
28 };
29
to_jz4740(struct pwm_chip * chip)30 static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
31 {
32 return container_of(chip, struct jz4740_pwm_chip, chip);
33 }
34
jz4740_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)35 static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
36 {
37 /*
38 * Timers 0 and 1 are used for system tasks, so they are unavailable
39 * for use as PWMs.
40 */
41 if (pwm->hwpwm < 2)
42 return -EBUSY;
43
44 jz4740_timer_start(pwm->hwpwm);
45
46 return 0;
47 }
48
jz4740_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)49 static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
50 {
51 jz4740_timer_set_ctrl(pwm->hwpwm, 0);
52
53 jz4740_timer_stop(pwm->hwpwm);
54 }
55
jz4740_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)56 static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
57 {
58 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm);
59
60 ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
61 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
62 jz4740_timer_enable(pwm->hwpwm);
63
64 return 0;
65 }
66
jz4740_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)67 static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
68 {
69 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm);
70
71 /*
72 * Set duty > period. This trick allows the TCU channels in TCU2 mode to
73 * properly return to their init level.
74 */
75 jz4740_timer_set_duty(pwm->hwpwm, 0xffff);
76 jz4740_timer_set_period(pwm->hwpwm, 0x0);
77
78 /*
79 * Disable PWM output.
80 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
81 * counter is stopped, while in TCU1 mode the order does not matter.
82 */
83 ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
84 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
85
86 /* Stop counter */
87 jz4740_timer_disable(pwm->hwpwm);
88 }
89
jz4740_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)90 static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
91 const struct pwm_state *state)
92 {
93 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
94 unsigned long long tmp;
95 unsigned long rate, period, duty;
96 unsigned int prescaler = 0;
97 uint16_t ctrl;
98
99 rate = clk_get_rate(jz4740->clk);
100 tmp = rate * state->period;
101 do_div(tmp, 1000000000);
102 period = tmp;
103
104 while (period > 0xffff && prescaler < 6) {
105 period >>= 2;
106 ++prescaler;
107 }
108
109 if (prescaler == 6)
110 return -EINVAL;
111
112 tmp = (unsigned long long)rate * state->duty_cycle;
113 do_div(tmp, NSEC_PER_SEC);
114 duty = period - tmp;
115
116 if (duty >= period)
117 duty = period - 1;
118
119 jz4740_pwm_disable(chip, pwm);
120
121 jz4740_timer_set_count(pwm->hwpwm, 0);
122 jz4740_timer_set_duty(pwm->hwpwm, duty);
123 jz4740_timer_set_period(pwm->hwpwm, period);
124
125 ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
126 JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
127
128 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
129
130 switch (state->polarity) {
131 case PWM_POLARITY_NORMAL:
132 ctrl &= ~JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
133 break;
134 case PWM_POLARITY_INVERSED:
135 ctrl |= JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
136 break;
137 }
138
139 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
140
141 if (state->enabled)
142 jz4740_pwm_enable(chip, pwm);
143
144 return 0;
145 }
146
147 static const struct pwm_ops jz4740_pwm_ops = {
148 .request = jz4740_pwm_request,
149 .free = jz4740_pwm_free,
150 .apply = jz4740_pwm_apply,
151 .owner = THIS_MODULE,
152 };
153
jz4740_pwm_probe(struct platform_device * pdev)154 static int jz4740_pwm_probe(struct platform_device *pdev)
155 {
156 struct jz4740_pwm_chip *jz4740;
157
158 jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL);
159 if (!jz4740)
160 return -ENOMEM;
161
162 jz4740->clk = devm_clk_get(&pdev->dev, "ext");
163 if (IS_ERR(jz4740->clk))
164 return PTR_ERR(jz4740->clk);
165
166 jz4740->chip.dev = &pdev->dev;
167 jz4740->chip.ops = &jz4740_pwm_ops;
168 jz4740->chip.npwm = NUM_PWM;
169 jz4740->chip.base = -1;
170 jz4740->chip.of_xlate = of_pwm_xlate_with_flags;
171 jz4740->chip.of_pwm_n_cells = 3;
172
173 platform_set_drvdata(pdev, jz4740);
174
175 return pwmchip_add(&jz4740->chip);
176 }
177
jz4740_pwm_remove(struct platform_device * pdev)178 static int jz4740_pwm_remove(struct platform_device *pdev)
179 {
180 struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev);
181
182 return pwmchip_remove(&jz4740->chip);
183 }
184
185 #ifdef CONFIG_OF
186 static const struct of_device_id jz4740_pwm_dt_ids[] = {
187 { .compatible = "ingenic,jz4740-pwm", },
188 {},
189 };
190 MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
191 #endif
192
193 static struct platform_driver jz4740_pwm_driver = {
194 .driver = {
195 .name = "jz4740-pwm",
196 .of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
197 },
198 .probe = jz4740_pwm_probe,
199 .remove = jz4740_pwm_remove,
200 };
201 module_platform_driver(jz4740_pwm_driver);
202
203 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
204 MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
205 MODULE_ALIAS("platform:jz4740-pwm");
206 MODULE_LICENSE("GPL");
207