1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
6 *
7 * Limitations:
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
13 */
14 #include <linux/clk.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/slab.h>
20 #include <linux/bitfield.h>
21
22 /* Register offsets */
23 #define PWM_SIFIVE_PWMCFG 0x0
24 #define PWM_SIFIVE_PWMCOUNT 0x8
25 #define PWM_SIFIVE_PWMS 0x10
26 #define PWM_SIFIVE_PWMCMP0 0x20
27
28 /* PWMCFG fields */
29 #define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
30 #define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
31 #define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
32 #define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
33 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
34 #define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
35 #define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
36 #define PWM_SIFIVE_PWMCFG_GANG BIT(24)
37 #define PWM_SIFIVE_PWMCFG_IP BIT(28)
38
39 /* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
40 #define PWM_SIFIVE_SIZE_PWMCMP 4
41 #define PWM_SIFIVE_CMPWIDTH 16
42 #define PWM_SIFIVE_DEFAULT_PERIOD 10000000
43
44 struct pwm_sifive_ddata {
45 struct pwm_chip chip;
46 struct mutex lock; /* lock to protect user_count and approx_period */
47 struct notifier_block notifier;
48 struct clk *clk;
49 void __iomem *regs;
50 unsigned int real_period;
51 unsigned int approx_period;
52 int user_count;
53 };
54
55 static inline
pwm_sifive_chip_to_ddata(struct pwm_chip * c)56 struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
57 {
58 return container_of(c, struct pwm_sifive_ddata, chip);
59 }
60
pwm_sifive_request(struct pwm_chip * chip,struct pwm_device * pwm)61 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
62 {
63 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
64
65 mutex_lock(&ddata->lock);
66 ddata->user_count++;
67 mutex_unlock(&ddata->lock);
68
69 return 0;
70 }
71
pwm_sifive_free(struct pwm_chip * chip,struct pwm_device * pwm)72 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
73 {
74 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
75
76 mutex_lock(&ddata->lock);
77 ddata->user_count--;
78 mutex_unlock(&ddata->lock);
79 }
80
81 /* Called holding ddata->lock */
pwm_sifive_update_clock(struct pwm_sifive_ddata * ddata,unsigned long rate)82 static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
83 unsigned long rate)
84 {
85 unsigned long long num;
86 unsigned long scale_pow;
87 int scale;
88 u32 val;
89 /*
90 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
91 * period length is using pwmscale which provides the number of bits the
92 * counter is shifted before being feed to the comparators. A period
93 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
94 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
95 */
96 scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
97 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
98
99 val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
100 FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
101 writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
102
103 /* As scale <= 15 the shift operation cannot overflow. */
104 num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
105 ddata->real_period = div64_ul(num, rate);
106 dev_dbg(ddata->chip.dev,
107 "New real_period = %u ns\n", ddata->real_period);
108 }
109
pwm_sifive_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)110 static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
111 struct pwm_state *state)
112 {
113 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
114 u32 duty, val;
115
116 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP0 +
117 pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP);
118
119 state->enabled = duty > 0;
120
121 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
122 if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
123 state->enabled = false;
124
125 state->period = ddata->real_period;
126 state->duty_cycle =
127 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
128 state->polarity = PWM_POLARITY_INVERSED;
129 }
130
pwm_sifive_enable(struct pwm_chip * chip,bool enable)131 static int pwm_sifive_enable(struct pwm_chip *chip, bool enable)
132 {
133 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
134 int ret;
135
136 if (enable) {
137 ret = clk_enable(ddata->clk);
138 if (ret) {
139 dev_err(ddata->chip.dev, "Enable clk failed\n");
140 return ret;
141 }
142 }
143
144 if (!enable)
145 clk_disable(ddata->clk);
146
147 return 0;
148 }
149
pwm_sifive_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)150 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
151 const struct pwm_state *state)
152 {
153 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
154 struct pwm_state cur_state;
155 unsigned int duty_cycle;
156 unsigned long long num;
157 bool enabled;
158 int ret = 0;
159 u32 frac;
160
161 if (state->polarity != PWM_POLARITY_INVERSED)
162 return -EINVAL;
163
164 ret = clk_enable(ddata->clk);
165 if (ret) {
166 dev_err(ddata->chip.dev, "Enable clk failed\n");
167 return ret;
168 }
169
170 cur_state = pwm->state;
171 enabled = cur_state.enabled;
172
173 duty_cycle = state->duty_cycle;
174 if (!state->enabled)
175 duty_cycle = 0;
176
177 /*
178 * The problem of output producing mixed setting as mentioned at top,
179 * occurs here. To minimize the window for this problem, we are
180 * calculating the register values first and then writing them
181 * consecutively
182 */
183 num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
184 frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
185 /* The hardware cannot generate a 100% duty cycle */
186 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
187
188 mutex_lock(&ddata->lock);
189 if (state->period != ddata->approx_period) {
190 /*
191 * Don't let a 2nd user change the period underneath the 1st user.
192 * However if ddate->approx_period == 0 this is the first time we set
193 * any period, so let whoever gets here first set the period so other
194 * users who agree on the period won't fail.
195 */
196 if (ddata->user_count != 1 && ddata->approx_period) {
197 mutex_unlock(&ddata->lock);
198 ret = -EBUSY;
199 goto exit;
200 }
201 ddata->approx_period = state->period;
202 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
203 }
204 mutex_unlock(&ddata->lock);
205
206 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP0 +
207 pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP);
208
209 if (state->enabled != enabled)
210 pwm_sifive_enable(chip, state->enabled);
211
212 exit:
213 clk_disable(ddata->clk);
214 return ret;
215 }
216
217 static const struct pwm_ops pwm_sifive_ops = {
218 .request = pwm_sifive_request,
219 .free = pwm_sifive_free,
220 .get_state = pwm_sifive_get_state,
221 .apply = pwm_sifive_apply,
222 .owner = THIS_MODULE,
223 };
224
pwm_sifive_clock_notifier(struct notifier_block * nb,unsigned long event,void * data)225 static int pwm_sifive_clock_notifier(struct notifier_block *nb,
226 unsigned long event, void *data)
227 {
228 struct clk_notifier_data *ndata = data;
229 struct pwm_sifive_ddata *ddata =
230 container_of(nb, struct pwm_sifive_ddata, notifier);
231
232 if (event == POST_RATE_CHANGE) {
233 mutex_lock(&ddata->lock);
234 pwm_sifive_update_clock(ddata, ndata->new_rate);
235 mutex_unlock(&ddata->lock);
236 }
237
238 return NOTIFY_OK;
239 }
240
pwm_sifive_probe(struct platform_device * pdev)241 static int pwm_sifive_probe(struct platform_device *pdev)
242 {
243 struct device *dev = &pdev->dev;
244 struct pwm_sifive_ddata *ddata;
245 struct pwm_chip *chip;
246 struct resource *res;
247 int ret;
248
249 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
250 if (!ddata)
251 return -ENOMEM;
252
253 mutex_init(&ddata->lock);
254 chip = &ddata->chip;
255 chip->dev = dev;
256 chip->ops = &pwm_sifive_ops;
257 chip->of_xlate = of_pwm_xlate_with_flags;
258 chip->of_pwm_n_cells = 3;
259 chip->base = -1;
260 chip->npwm = 4;
261
262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
263 ddata->regs = devm_ioremap_resource(dev, res);
264 if (IS_ERR(ddata->regs))
265 return PTR_ERR(ddata->regs);
266
267 ddata->clk = devm_clk_get(dev, NULL);
268 if (IS_ERR(ddata->clk)) {
269 if (PTR_ERR(ddata->clk) != -EPROBE_DEFER)
270 dev_err(dev, "Unable to find controller clock\n");
271 return PTR_ERR(ddata->clk);
272 }
273
274 ret = clk_prepare_enable(ddata->clk);
275 if (ret) {
276 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
277 return ret;
278 }
279
280 /* Watch for changes to underlying clock frequency */
281 ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
282 ret = clk_notifier_register(ddata->clk, &ddata->notifier);
283 if (ret) {
284 dev_err(dev, "failed to register clock notifier: %d\n", ret);
285 goto disable_clk;
286 }
287
288 ret = pwmchip_add(chip);
289 if (ret < 0) {
290 dev_err(dev, "cannot register PWM: %d\n", ret);
291 goto unregister_clk;
292 }
293
294 platform_set_drvdata(pdev, ddata);
295 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
296
297 return 0;
298
299 unregister_clk:
300 clk_notifier_unregister(ddata->clk, &ddata->notifier);
301 disable_clk:
302 clk_disable_unprepare(ddata->clk);
303
304 return ret;
305 }
306
pwm_sifive_remove(struct platform_device * dev)307 static int pwm_sifive_remove(struct platform_device *dev)
308 {
309 struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
310 bool is_enabled = false;
311 struct pwm_device *pwm;
312 int ret, ch;
313
314 for (ch = 0; ch < ddata->chip.npwm; ch++) {
315 pwm = &ddata->chip.pwms[ch];
316 if (pwm->state.enabled) {
317 is_enabled = true;
318 break;
319 }
320 }
321 if (is_enabled)
322 clk_disable(ddata->clk);
323
324 clk_disable_unprepare(ddata->clk);
325 ret = pwmchip_remove(&ddata->chip);
326 clk_notifier_unregister(ddata->clk, &ddata->notifier);
327
328 return ret;
329 }
330
331 static const struct of_device_id pwm_sifive_of_match[] = {
332 { .compatible = "sifive,pwm0" },
333 {},
334 };
335 MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
336
337 static struct platform_driver pwm_sifive_driver = {
338 .probe = pwm_sifive_probe,
339 .remove = pwm_sifive_remove,
340 .driver = {
341 .name = "pwm-sifive",
342 .of_match_table = pwm_sifive_of_match,
343 },
344 };
345 module_platform_driver(pwm_sifive_driver);
346
347 MODULE_DESCRIPTION("SiFive PWM driver");
348 MODULE_LICENSE("GPL v2");
349