1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4 #include <linux/of.h>
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/rtc.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm.h>
10 #include <linux/regmap.h>
11 #include <linux/slab.h>
12 #include <linux/spinlock.h>
13
14 /* RTC Register offsets from RTC CTRL REG */
15 #define PM8XXX_ALARM_CTRL_OFFSET 0x01
16 #define PM8XXX_RTC_WRITE_OFFSET 0x02
17 #define PM8XXX_RTC_READ_OFFSET 0x06
18 #define PM8XXX_ALARM_RW_OFFSET 0x0A
19
20 /* RTC_CTRL register bit fields */
21 #define PM8xxx_RTC_ENABLE BIT(7)
22 #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
23
24 #define NUM_8_BIT_RTC_REGS 0x4
25
26 /**
27 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
28 * @ctrl: base address of control register
29 * @write: base address of write register
30 * @read: base address of read register
31 * @alarm_ctrl: base address of alarm control register
32 * @alarm_ctrl2: base address of alarm control2 register
33 * @alarm_rw: base address of alarm read-write register
34 * @alarm_en: alarm enable mask
35 */
36 struct pm8xxx_rtc_regs {
37 unsigned int ctrl;
38 unsigned int write;
39 unsigned int read;
40 unsigned int alarm_ctrl;
41 unsigned int alarm_ctrl2;
42 unsigned int alarm_rw;
43 unsigned int alarm_en;
44 };
45
46 /**
47 * struct pm8xxx_rtc - rtc driver internal structure
48 * @rtc: rtc device for this driver.
49 * @regmap: regmap used to access RTC registers
50 * @allow_set_time: indicates whether writing to the RTC is allowed
51 * @rtc_alarm_irq: rtc alarm irq number.
52 * @ctrl_reg: rtc control register.
53 * @rtc_dev: device structure.
54 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
55 */
56 struct pm8xxx_rtc {
57 struct rtc_device *rtc;
58 struct regmap *regmap;
59 bool allow_set_time;
60 int rtc_alarm_irq;
61 const struct pm8xxx_rtc_regs *regs;
62 struct device *rtc_dev;
63 spinlock_t ctrl_reg_lock;
64 };
65
66 /*
67 * Steps to write the RTC registers.
68 * 1. Disable alarm if enabled.
69 * 2. Disable rtc if enabled.
70 * 3. Write 0x00 to LSB.
71 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
72 * 5. Enable rtc if disabled in step 2.
73 * 6. Enable alarm if disabled in step 1.
74 */
pm8xxx_rtc_set_time(struct device * dev,struct rtc_time * tm)75 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
76 {
77 int rc, i;
78 unsigned long secs, irq_flags;
79 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
80 unsigned int ctrl_reg, rtc_ctrl_reg;
81 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
82 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
83
84 if (!rtc_dd->allow_set_time)
85 return -EACCES;
86
87 rtc_tm_to_time(tm, &secs);
88
89 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
90
91 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
92 value[i] = secs & 0xFF;
93 secs >>= 8;
94 }
95
96 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
97
98 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
99 if (rc)
100 goto rtc_rw_fail;
101
102 if (ctrl_reg & regs->alarm_en) {
103 alarm_enabled = 1;
104 ctrl_reg &= ~regs->alarm_en;
105 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
106 if (rc) {
107 dev_err(dev, "Write to RTC Alarm control register failed\n");
108 goto rtc_rw_fail;
109 }
110 }
111
112 /* Disable RTC H/w before writing on RTC register */
113 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
114 if (rc)
115 goto rtc_rw_fail;
116
117 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
118 rtc_disabled = 1;
119 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
120 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
121 if (rc) {
122 dev_err(dev, "Write to RTC control register failed\n");
123 goto rtc_rw_fail;
124 }
125 }
126
127 /* Write 0 to Byte[0] */
128 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
129 if (rc) {
130 dev_err(dev, "Write to RTC write data register failed\n");
131 goto rtc_rw_fail;
132 }
133
134 /* Write Byte[1], Byte[2], Byte[3] */
135 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
136 &value[1], sizeof(value) - 1);
137 if (rc) {
138 dev_err(dev, "Write to RTC write data register failed\n");
139 goto rtc_rw_fail;
140 }
141
142 /* Write Byte[0] */
143 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
144 if (rc) {
145 dev_err(dev, "Write to RTC write data register failed\n");
146 goto rtc_rw_fail;
147 }
148
149 /* Enable RTC H/w after writing on RTC register */
150 if (rtc_disabled) {
151 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
152 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
153 if (rc) {
154 dev_err(dev, "Write to RTC control register failed\n");
155 goto rtc_rw_fail;
156 }
157 }
158
159 if (alarm_enabled) {
160 ctrl_reg |= regs->alarm_en;
161 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
162 if (rc) {
163 dev_err(dev, "Write to RTC Alarm control register failed\n");
164 goto rtc_rw_fail;
165 }
166 }
167
168 rtc_rw_fail:
169 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
170
171 return rc;
172 }
173
pm8xxx_rtc_read_time(struct device * dev,struct rtc_time * tm)174 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
175 {
176 int rc;
177 u8 value[NUM_8_BIT_RTC_REGS];
178 unsigned long secs;
179 unsigned int reg;
180 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
181 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
182
183 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
184 if (rc) {
185 dev_err(dev, "RTC read data register failed\n");
186 return rc;
187 }
188
189 /*
190 * Read the LSB again and check if there has been a carry over.
191 * If there is, redo the read operation.
192 */
193 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
194 if (rc < 0) {
195 dev_err(dev, "RTC read data register failed\n");
196 return rc;
197 }
198
199 if (unlikely(reg < value[0])) {
200 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
201 value, sizeof(value));
202 if (rc) {
203 dev_err(dev, "RTC read data register failed\n");
204 return rc;
205 }
206 }
207
208 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
209 ((unsigned long)value[3] << 24);
210
211 rtc_time_to_tm(secs, tm);
212
213 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
214
215 return 0;
216 }
217
pm8xxx_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)218 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
219 {
220 int rc, i;
221 u8 value[NUM_8_BIT_RTC_REGS];
222 unsigned long secs, irq_flags;
223 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
224 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
225
226 rtc_tm_to_time(&alarm->time, &secs);
227
228 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
229 value[i] = secs & 0xFF;
230 secs >>= 8;
231 }
232
233 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
234 regs->alarm_en, 0);
235 if (rc)
236 return rc;
237
238 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
239
240 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
241 sizeof(value));
242 if (rc) {
243 dev_err(dev, "Write to RTC ALARM register failed\n");
244 goto rtc_rw_fail;
245 }
246
247 if (alarm->enabled) {
248 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
249 regs->alarm_en, regs->alarm_en);
250 if (rc)
251 goto rtc_rw_fail;
252 }
253
254 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
255 &alarm->time, &alarm->time);
256 rtc_rw_fail:
257 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
258 return rc;
259 }
260
pm8xxx_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)261 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
262 {
263 int rc;
264 u8 value[NUM_8_BIT_RTC_REGS];
265 unsigned long secs;
266 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
267 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
268
269 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
270 sizeof(value));
271 if (rc) {
272 dev_err(dev, "RTC alarm time read failed\n");
273 return rc;
274 }
275
276 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
277 ((unsigned long)value[3] << 24);
278
279 rtc_time_to_tm(secs, &alarm->time);
280
281 rc = rtc_valid_tm(&alarm->time);
282 if (rc < 0) {
283 dev_err(dev, "Invalid alarm time read from RTC\n");
284 return rc;
285 }
286
287 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
288 &alarm->time, &alarm->time);
289
290 return 0;
291 }
292
pm8xxx_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)293 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
294 {
295 int rc;
296 unsigned long irq_flags;
297 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
298 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
299 unsigned int ctrl_reg;
300
301 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
302
303 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
304 if (rc)
305 goto rtc_rw_fail;
306
307 if (enable)
308 ctrl_reg |= regs->alarm_en;
309 else
310 ctrl_reg &= ~regs->alarm_en;
311
312 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
313 if (rc) {
314 dev_err(dev, "Write to RTC control register failed\n");
315 goto rtc_rw_fail;
316 }
317
318 rtc_rw_fail:
319 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
320 return rc;
321 }
322
323 static const struct rtc_class_ops pm8xxx_rtc_ops = {
324 .read_time = pm8xxx_rtc_read_time,
325 .set_time = pm8xxx_rtc_set_time,
326 .set_alarm = pm8xxx_rtc_set_alarm,
327 .read_alarm = pm8xxx_rtc_read_alarm,
328 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
329 };
330
pm8xxx_alarm_trigger(int irq,void * dev_id)331 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
332 {
333 struct pm8xxx_rtc *rtc_dd = dev_id;
334 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
335 unsigned int ctrl_reg;
336 int rc;
337 unsigned long irq_flags;
338
339 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
340
341 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
342
343 /* Clear the alarm enable bit */
344 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
345 if (rc) {
346 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
347 goto rtc_alarm_handled;
348 }
349
350 ctrl_reg &= ~regs->alarm_en;
351
352 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
353 if (rc) {
354 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
355 dev_err(rtc_dd->rtc_dev,
356 "Write to alarm control register failed\n");
357 goto rtc_alarm_handled;
358 }
359
360 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
361
362 /* Clear RTC alarm register */
363 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
364 if (rc) {
365 dev_err(rtc_dd->rtc_dev,
366 "RTC Alarm control2 register read failed\n");
367 goto rtc_alarm_handled;
368 }
369
370 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
371 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
372 if (rc)
373 dev_err(rtc_dd->rtc_dev,
374 "Write to RTC Alarm control2 register failed\n");
375
376 rtc_alarm_handled:
377 return IRQ_HANDLED;
378 }
379
pm8xxx_rtc_enable(struct pm8xxx_rtc * rtc_dd)380 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
381 {
382 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
383 unsigned int ctrl_reg;
384 int rc;
385
386 /* Check if the RTC is on, else turn it on */
387 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
388 if (rc)
389 return rc;
390
391 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
392 ctrl_reg |= PM8xxx_RTC_ENABLE;
393 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
394 if (rc)
395 return rc;
396 }
397
398 return 0;
399 }
400
401 static const struct pm8xxx_rtc_regs pm8921_regs = {
402 .ctrl = 0x11d,
403 .write = 0x11f,
404 .read = 0x123,
405 .alarm_rw = 0x127,
406 .alarm_ctrl = 0x11d,
407 .alarm_ctrl2 = 0x11e,
408 .alarm_en = BIT(1),
409 };
410
411 static const struct pm8xxx_rtc_regs pm8058_regs = {
412 .ctrl = 0x1e8,
413 .write = 0x1ea,
414 .read = 0x1ee,
415 .alarm_rw = 0x1f2,
416 .alarm_ctrl = 0x1e8,
417 .alarm_ctrl2 = 0x1e9,
418 .alarm_en = BIT(1),
419 };
420
421 static const struct pm8xxx_rtc_regs pm8941_regs = {
422 .ctrl = 0x6046,
423 .write = 0x6040,
424 .read = 0x6048,
425 .alarm_rw = 0x6140,
426 .alarm_ctrl = 0x6146,
427 .alarm_ctrl2 = 0x6148,
428 .alarm_en = BIT(7),
429 };
430
431 /*
432 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
433 */
434 static const struct of_device_id pm8xxx_id_table[] = {
435 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
436 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
437 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
438 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
439 { },
440 };
441 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
442
pm8xxx_rtc_probe(struct platform_device * pdev)443 static int pm8xxx_rtc_probe(struct platform_device *pdev)
444 {
445 int rc;
446 struct pm8xxx_rtc *rtc_dd;
447 const struct of_device_id *match;
448
449 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
450 if (!match)
451 return -ENXIO;
452
453 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
454 if (rtc_dd == NULL)
455 return -ENOMEM;
456
457 /* Initialise spinlock to protect RTC control register */
458 spin_lock_init(&rtc_dd->ctrl_reg_lock);
459
460 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
461 if (!rtc_dd->regmap) {
462 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
463 return -ENXIO;
464 }
465
466 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
467 if (rtc_dd->rtc_alarm_irq < 0)
468 return -ENXIO;
469
470 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
471 "allow-set-time");
472
473 rtc_dd->regs = match->data;
474 rtc_dd->rtc_dev = &pdev->dev;
475
476 rc = pm8xxx_rtc_enable(rtc_dd);
477 if (rc)
478 return rc;
479
480 platform_set_drvdata(pdev, rtc_dd);
481
482 device_init_wakeup(&pdev->dev, 1);
483
484 /* Register the RTC device */
485 rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
486 &pm8xxx_rtc_ops, THIS_MODULE);
487 if (IS_ERR(rtc_dd->rtc)) {
488 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
489 __func__, PTR_ERR(rtc_dd->rtc));
490 return PTR_ERR(rtc_dd->rtc);
491 }
492
493 /* Request the alarm IRQ */
494 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
495 pm8xxx_alarm_trigger,
496 IRQF_TRIGGER_RISING,
497 "pm8xxx_rtc_alarm", rtc_dd);
498 if (rc < 0) {
499 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
500 return rc;
501 }
502
503 dev_dbg(&pdev->dev, "Probe success !!\n");
504
505 return 0;
506 }
507
508 #ifdef CONFIG_PM_SLEEP
pm8xxx_rtc_resume(struct device * dev)509 static int pm8xxx_rtc_resume(struct device *dev)
510 {
511 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
512
513 if (device_may_wakeup(dev))
514 disable_irq_wake(rtc_dd->rtc_alarm_irq);
515
516 return 0;
517 }
518
pm8xxx_rtc_suspend(struct device * dev)519 static int pm8xxx_rtc_suspend(struct device *dev)
520 {
521 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
522
523 if (device_may_wakeup(dev))
524 enable_irq_wake(rtc_dd->rtc_alarm_irq);
525
526 return 0;
527 }
528 #endif
529
530 static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
531 pm8xxx_rtc_suspend,
532 pm8xxx_rtc_resume);
533
534 static struct platform_driver pm8xxx_rtc_driver = {
535 .probe = pm8xxx_rtc_probe,
536 .driver = {
537 .name = "rtc-pm8xxx",
538 .pm = &pm8xxx_rtc_pm_ops,
539 .of_match_table = pm8xxx_id_table,
540 },
541 };
542
543 module_platform_driver(pm8xxx_rtc_driver);
544
545 MODULE_ALIAS("platform:rtc-pm8xxx");
546 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
547 MODULE_LICENSE("GPL v2");
548 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
549