1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * An RTC driver for Allwinner A31/A23
4 *
5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
6 *
7 * based on rtc-sunxi.c
8 *
9 * An RTC driver for Allwinner A10/A20
10 *
11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/fs.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/rtc.h>
29 #include <linux/slab.h>
30 #include <linux/types.h>
31
32 /* Control register */
33 #define SUN6I_LOSC_CTRL 0x0000
34 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4)
40 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
41 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
42
43 #define SUN6I_LOSC_CLK_PRESCAL 0x0008
44
45 /* RTC */
46 #define SUN6I_RTC_YMD 0x0010
47 #define SUN6I_RTC_HMS 0x0014
48
49 /* Alarm 0 (counter) */
50 #define SUN6I_ALRM_COUNTER 0x0020
51 #define SUN6I_ALRM_CUR_VAL 0x0024
52 #define SUN6I_ALRM_EN 0x0028
53 #define SUN6I_ALRM_EN_CNT_EN BIT(0)
54 #define SUN6I_ALRM_IRQ_EN 0x002c
55 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
56 #define SUN6I_ALRM_IRQ_STA 0x0030
57 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
58
59 /* Alarm 1 (wall clock) */
60 #define SUN6I_ALRM1_EN 0x0044
61 #define SUN6I_ALRM1_IRQ_EN 0x0048
62 #define SUN6I_ALRM1_IRQ_STA 0x004c
63 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
64
65 /* Alarm config */
66 #define SUN6I_ALARM_CONFIG 0x0050
67 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
68
69 #define SUN6I_LOSC_OUT_GATING 0x0060
70 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
71
72 /*
73 * Get date values
74 */
75 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
76 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
77 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
78 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
79
80 /*
81 * Get time values
82 */
83 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
84 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
85 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
86
87 /*
88 * Set date values
89 */
90 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
91 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
92 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
93 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
94
95 /*
96 * Set time values
97 */
98 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
99 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
100 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
101
102 /*
103 * The year parameter passed to the driver is usually an offset relative to
104 * the year 1900. This macro is used to convert this offset to another one
105 * relative to the minimum year allowed by the hardware.
106 *
107 * The year range is 1970 - 2033. This range is selected to match Allwinner's
108 * driver, even though it is somewhat limited.
109 */
110 #define SUN6I_YEAR_MIN 1970
111 #define SUN6I_YEAR_MAX 2033
112 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
113
114 /*
115 * There are other differences between models, including:
116 *
117 * - number of GPIO pins that can be configured to hold a certain level
118 * - crypto-key related registers (H5, H6)
119 * - boot process related (super standby, secondary processor entry address)
120 * registers (R40, H6)
121 * - SYS power domain controls (R40)
122 * - DCXO controls (H6)
123 * - RC oscillator calibration (H6)
124 *
125 * These functions are not covered by this driver.
126 */
127 struct sun6i_rtc_clk_data {
128 unsigned long rc_osc_rate;
129 unsigned int fixed_prescaler : 16;
130 unsigned int has_prescaler : 1;
131 unsigned int has_out_clk : 1;
132 unsigned int has_losc_en : 1;
133 unsigned int has_auto_swt : 1;
134 };
135
136 struct sun6i_rtc_dev {
137 struct rtc_device *rtc;
138 struct device *dev;
139 const struct sun6i_rtc_clk_data *data;
140 void __iomem *base;
141 int irq;
142 unsigned long alarm;
143
144 struct clk_hw hw;
145 struct clk_hw *int_osc;
146 struct clk *losc;
147 struct clk *ext_losc;
148
149 spinlock_t lock;
150 };
151
152 static struct sun6i_rtc_dev *sun6i_rtc;
153
sun6i_rtc_osc_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)154 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
155 unsigned long parent_rate)
156 {
157 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
158 u32 val = 0;
159
160 val = readl(rtc->base + SUN6I_LOSC_CTRL);
161 if (val & SUN6I_LOSC_CTRL_EXT_OSC)
162 return parent_rate;
163
164 if (rtc->data->fixed_prescaler)
165 parent_rate /= rtc->data->fixed_prescaler;
166
167 if (rtc->data->has_prescaler) {
168 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
169 val &= GENMASK(4, 0);
170 }
171
172 return parent_rate / (val + 1);
173 }
174
sun6i_rtc_osc_get_parent(struct clk_hw * hw)175 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
176 {
177 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
178
179 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
180 }
181
sun6i_rtc_osc_set_parent(struct clk_hw * hw,u8 index)182 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
183 {
184 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
185 unsigned long flags;
186 u32 val;
187
188 if (index > 1)
189 return -EINVAL;
190
191 spin_lock_irqsave(&rtc->lock, flags);
192 val = readl(rtc->base + SUN6I_LOSC_CTRL);
193 val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
194 val |= SUN6I_LOSC_CTRL_KEY;
195 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
196 if (rtc->data->has_losc_en) {
197 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
198 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
199 }
200 writel(val, rtc->base + SUN6I_LOSC_CTRL);
201 spin_unlock_irqrestore(&rtc->lock, flags);
202
203 return 0;
204 }
205
206 static const struct clk_ops sun6i_rtc_osc_ops = {
207 .recalc_rate = sun6i_rtc_osc_recalc_rate,
208
209 .get_parent = sun6i_rtc_osc_get_parent,
210 .set_parent = sun6i_rtc_osc_set_parent,
211 };
212
sun6i_rtc_clk_init(struct device_node * node,const struct sun6i_rtc_clk_data * data)213 static void __init sun6i_rtc_clk_init(struct device_node *node,
214 const struct sun6i_rtc_clk_data *data)
215 {
216 struct clk_hw_onecell_data *clk_data;
217 struct sun6i_rtc_dev *rtc;
218 struct clk_init_data init = {
219 .ops = &sun6i_rtc_osc_ops,
220 .name = "losc",
221 };
222 const char *iosc_name = "rtc-int-osc";
223 const char *clkout_name = "osc32k-out";
224 const char *parents[2];
225 u32 reg;
226
227 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
228 if (!rtc)
229 return;
230
231 rtc->data = data;
232 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
233 if (!clk_data) {
234 kfree(rtc);
235 return;
236 }
237
238 spin_lock_init(&rtc->lock);
239
240 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
241 if (IS_ERR(rtc->base)) {
242 pr_crit("Can't map RTC registers");
243 goto err;
244 }
245
246 reg = SUN6I_LOSC_CTRL_KEY;
247 if (rtc->data->has_auto_swt) {
248 /* Bypass auto-switch to int osc, on ext losc failure */
249 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
250 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
251 }
252
253 /* Switch to the external, more precise, oscillator, if present */
254 if (of_get_property(node, "clocks", NULL)) {
255 reg |= SUN6I_LOSC_CTRL_EXT_OSC;
256 if (rtc->data->has_losc_en)
257 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
258 }
259 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
260
261 /* Yes, I know, this is ugly. */
262 sun6i_rtc = rtc;
263
264 of_property_read_string_index(node, "clock-output-names", 2,
265 &iosc_name);
266
267 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
268 iosc_name,
269 NULL, 0,
270 rtc->data->rc_osc_rate,
271 300000000);
272 if (IS_ERR(rtc->int_osc)) {
273 pr_crit("Couldn't register the internal oscillator\n");
274 goto err;
275 }
276
277 parents[0] = clk_hw_get_name(rtc->int_osc);
278 /* If there is no external oscillator, this will be NULL and ... */
279 parents[1] = of_clk_get_parent_name(node, 0);
280
281 rtc->hw.init = &init;
282
283 init.parent_names = parents;
284 /* ... number of clock parents will be 1. */
285 init.num_parents = of_clk_get_parent_count(node) + 1;
286 of_property_read_string_index(node, "clock-output-names", 0,
287 &init.name);
288
289 rtc->losc = clk_register(NULL, &rtc->hw);
290 if (IS_ERR(rtc->losc)) {
291 pr_crit("Couldn't register the LOSC clock\n");
292 goto err_register;
293 }
294
295 of_property_read_string_index(node, "clock-output-names", 1,
296 &clkout_name);
297 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
298 0, rtc->base + SUN6I_LOSC_OUT_GATING,
299 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
300 &rtc->lock);
301 if (IS_ERR(rtc->ext_losc)) {
302 pr_crit("Couldn't register the LOSC external gate\n");
303 goto err_register;
304 }
305
306 clk_data->num = 3;
307 clk_data->hws[0] = &rtc->hw;
308 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
309 clk_data->hws[2] = rtc->int_osc;
310 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
311 return;
312
313 err_register:
314 clk_hw_unregister_fixed_rate(rtc->int_osc);
315 err:
316 kfree(clk_data);
317 }
318
319 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
320 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
321 .has_prescaler = 1,
322 };
323
sun6i_a31_rtc_clk_init(struct device_node * node)324 static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
325 {
326 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
327 }
328 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
329 sun6i_a31_rtc_clk_init);
330
331 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
332 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
333 .has_prescaler = 1,
334 .has_out_clk = 1,
335 };
336
sun8i_a23_rtc_clk_init(struct device_node * node)337 static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
338 {
339 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
340 }
341 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
342 sun8i_a23_rtc_clk_init);
343
344 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
345 .rc_osc_rate = 16000000,
346 .fixed_prescaler = 32,
347 .has_prescaler = 1,
348 .has_out_clk = 1,
349 };
350
sun8i_h3_rtc_clk_init(struct device_node * node)351 static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
352 {
353 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
354 }
355 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
356 sun8i_h3_rtc_clk_init);
357 /* As far as we are concerned, clocks for H5 are the same as H3 */
358 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
359 sun8i_h3_rtc_clk_init);
360
361 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
362 .rc_osc_rate = 16000000,
363 .fixed_prescaler = 32,
364 .has_prescaler = 1,
365 .has_out_clk = 1,
366 .has_losc_en = 1,
367 .has_auto_swt = 1,
368 };
369
sun50i_h6_rtc_clk_init(struct device_node * node)370 static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
371 {
372 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
373 }
374 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
375 sun50i_h6_rtc_clk_init);
376
377 /*
378 * The R40 user manual is self-conflicting on whether the prescaler is
379 * fixed or configurable. The clock diagram shows it as fixed, but there
380 * is also a configurable divider in the RTC block.
381 */
382 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
383 .rc_osc_rate = 16000000,
384 .fixed_prescaler = 512,
385 };
sun8i_r40_rtc_clk_init(struct device_node * node)386 static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
387 {
388 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
389 }
390 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
391 sun8i_r40_rtc_clk_init);
392
393 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
394 .rc_osc_rate = 32000,
395 .has_out_clk = 1,
396 };
397
sun8i_v3_rtc_clk_init(struct device_node * node)398 static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
399 {
400 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
401 }
402 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
403 sun8i_v3_rtc_clk_init);
404
sun6i_rtc_alarmirq(int irq,void * id)405 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
406 {
407 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
408 irqreturn_t ret = IRQ_NONE;
409 u32 val;
410
411 spin_lock(&chip->lock);
412 val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
413
414 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
415 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
416 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
417
418 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
419
420 ret = IRQ_HANDLED;
421 }
422 spin_unlock(&chip->lock);
423
424 return ret;
425 }
426
sun6i_rtc_setaie(int to,struct sun6i_rtc_dev * chip)427 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
428 {
429 u32 alrm_val = 0;
430 u32 alrm_irq_val = 0;
431 u32 alrm_wake_val = 0;
432 unsigned long flags;
433
434 if (to) {
435 alrm_val = SUN6I_ALRM_EN_CNT_EN;
436 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
437 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
438 } else {
439 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
440 chip->base + SUN6I_ALRM_IRQ_STA);
441 }
442
443 spin_lock_irqsave(&chip->lock, flags);
444 writel(alrm_val, chip->base + SUN6I_ALRM_EN);
445 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
446 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
447 spin_unlock_irqrestore(&chip->lock, flags);
448 }
449
sun6i_rtc_gettime(struct device * dev,struct rtc_time * rtc_tm)450 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
451 {
452 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
453 u32 date, time;
454
455 /*
456 * read again in case it changes
457 */
458 do {
459 date = readl(chip->base + SUN6I_RTC_YMD);
460 time = readl(chip->base + SUN6I_RTC_HMS);
461 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
462 (time != readl(chip->base + SUN6I_RTC_HMS)));
463
464 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
465 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
466 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
467
468 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
469 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
470 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
471
472 rtc_tm->tm_mon -= 1;
473
474 /*
475 * switch from (data_year->min)-relative offset to
476 * a (1900)-relative one
477 */
478 rtc_tm->tm_year += SUN6I_YEAR_OFF;
479
480 return 0;
481 }
482
sun6i_rtc_getalarm(struct device * dev,struct rtc_wkalrm * wkalrm)483 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
484 {
485 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
486 unsigned long flags;
487 u32 alrm_st;
488 u32 alrm_en;
489
490 spin_lock_irqsave(&chip->lock, flags);
491 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
492 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
493 spin_unlock_irqrestore(&chip->lock, flags);
494
495 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
496 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
497 rtc_time_to_tm(chip->alarm, &wkalrm->time);
498
499 return 0;
500 }
501
sun6i_rtc_setalarm(struct device * dev,struct rtc_wkalrm * wkalrm)502 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
503 {
504 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
505 struct rtc_time *alrm_tm = &wkalrm->time;
506 struct rtc_time tm_now;
507 unsigned long time_now = 0;
508 unsigned long time_set = 0;
509 unsigned long time_gap = 0;
510 int ret = 0;
511
512 ret = sun6i_rtc_gettime(dev, &tm_now);
513 if (ret < 0) {
514 dev_err(dev, "Error in getting time\n");
515 return -EINVAL;
516 }
517
518 rtc_tm_to_time(alrm_tm, &time_set);
519 rtc_tm_to_time(&tm_now, &time_now);
520 if (time_set <= time_now) {
521 dev_err(dev, "Date to set in the past\n");
522 return -EINVAL;
523 }
524
525 time_gap = time_set - time_now;
526
527 if (time_gap > U32_MAX) {
528 dev_err(dev, "Date too far in the future\n");
529 return -EINVAL;
530 }
531
532 sun6i_rtc_setaie(0, chip);
533 writel(0, chip->base + SUN6I_ALRM_COUNTER);
534 usleep_range(100, 300);
535
536 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
537 chip->alarm = time_set;
538
539 sun6i_rtc_setaie(wkalrm->enabled, chip);
540
541 return 0;
542 }
543
sun6i_rtc_wait(struct sun6i_rtc_dev * chip,int offset,unsigned int mask,unsigned int ms_timeout)544 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
545 unsigned int mask, unsigned int ms_timeout)
546 {
547 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
548 u32 reg;
549
550 do {
551 reg = readl(chip->base + offset);
552 reg &= mask;
553
554 if (!reg)
555 return 0;
556
557 } while (time_before(jiffies, timeout));
558
559 return -ETIMEDOUT;
560 }
561
sun6i_rtc_settime(struct device * dev,struct rtc_time * rtc_tm)562 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
563 {
564 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
565 u32 date = 0;
566 u32 time = 0;
567 int year;
568
569 year = rtc_tm->tm_year + 1900;
570 if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
571 dev_err(dev, "rtc only supports year in range %d - %d\n",
572 SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
573 return -EINVAL;
574 }
575
576 rtc_tm->tm_year -= SUN6I_YEAR_OFF;
577 rtc_tm->tm_mon += 1;
578
579 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
580 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
581 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
582
583 if (is_leap_year(year))
584 date |= SUN6I_LEAP_SET_VALUE(1);
585
586 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
587 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
588 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
589
590 /* Check whether registers are writable */
591 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
592 SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
593 dev_err(dev, "rtc is still busy.\n");
594 return -EBUSY;
595 }
596
597 writel(time, chip->base + SUN6I_RTC_HMS);
598
599 /*
600 * After writing the RTC HH-MM-SS register, the
601 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
602 * be cleared until the real writing operation is finished
603 */
604
605 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
606 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
607 dev_err(dev, "Failed to set rtc time.\n");
608 return -ETIMEDOUT;
609 }
610
611 writel(date, chip->base + SUN6I_RTC_YMD);
612
613 /*
614 * After writing the RTC YY-MM-DD register, the
615 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
616 * be cleared until the real writing operation is finished
617 */
618
619 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
620 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
621 dev_err(dev, "Failed to set rtc time.\n");
622 return -ETIMEDOUT;
623 }
624
625 return 0;
626 }
627
sun6i_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)628 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
629 {
630 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
631
632 if (!enabled)
633 sun6i_rtc_setaie(enabled, chip);
634
635 return 0;
636 }
637
638 static const struct rtc_class_ops sun6i_rtc_ops = {
639 .read_time = sun6i_rtc_gettime,
640 .set_time = sun6i_rtc_settime,
641 .read_alarm = sun6i_rtc_getalarm,
642 .set_alarm = sun6i_rtc_setalarm,
643 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
644 };
645
646 #ifdef CONFIG_PM_SLEEP
647 /* Enable IRQ wake on suspend, to wake up from RTC. */
sun6i_rtc_suspend(struct device * dev)648 static int sun6i_rtc_suspend(struct device *dev)
649 {
650 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
651
652 if (device_may_wakeup(dev))
653 enable_irq_wake(chip->irq);
654
655 return 0;
656 }
657
658 /* Disable IRQ wake on resume. */
sun6i_rtc_resume(struct device * dev)659 static int sun6i_rtc_resume(struct device *dev)
660 {
661 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
662
663 if (device_may_wakeup(dev))
664 disable_irq_wake(chip->irq);
665
666 return 0;
667 }
668 #endif
669
670 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
671 sun6i_rtc_suspend, sun6i_rtc_resume);
672
sun6i_rtc_probe(struct platform_device * pdev)673 static int sun6i_rtc_probe(struct platform_device *pdev)
674 {
675 struct sun6i_rtc_dev *chip = sun6i_rtc;
676 int ret;
677
678 if (!chip)
679 return -ENODEV;
680
681 platform_set_drvdata(pdev, chip);
682 chip->dev = &pdev->dev;
683
684 chip->irq = platform_get_irq(pdev, 0);
685 if (chip->irq < 0)
686 return chip->irq;
687
688 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
689 0, dev_name(&pdev->dev), chip);
690 if (ret) {
691 dev_err(&pdev->dev, "Could not request IRQ\n");
692 return ret;
693 }
694
695 /* clear the alarm counter value */
696 writel(0, chip->base + SUN6I_ALRM_COUNTER);
697
698 /* disable counter alarm */
699 writel(0, chip->base + SUN6I_ALRM_EN);
700
701 /* disable counter alarm interrupt */
702 writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
703
704 /* disable week alarm */
705 writel(0, chip->base + SUN6I_ALRM1_EN);
706
707 /* disable week alarm interrupt */
708 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
709
710 /* clear counter alarm pending interrupts */
711 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
712 chip->base + SUN6I_ALRM_IRQ_STA);
713
714 /* clear week alarm pending interrupts */
715 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
716 chip->base + SUN6I_ALRM1_IRQ_STA);
717
718 /* disable alarm wakeup */
719 writel(0, chip->base + SUN6I_ALARM_CONFIG);
720
721 clk_prepare_enable(chip->losc);
722
723 device_init_wakeup(&pdev->dev, 1);
724
725 chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i",
726 &sun6i_rtc_ops, THIS_MODULE);
727 if (IS_ERR(chip->rtc)) {
728 dev_err(&pdev->dev, "unable to register device\n");
729 return PTR_ERR(chip->rtc);
730 }
731
732 dev_info(&pdev->dev, "RTC enabled\n");
733
734 return 0;
735 }
736
737 /*
738 * As far as RTC functionality goes, all models are the same. The
739 * datasheets claim that different models have different number of
740 * registers available for non-volatile storage, but experiments show
741 * that all SoCs have 16 registers available for this purpose.
742 */
743 static const struct of_device_id sun6i_rtc_dt_ids[] = {
744 { .compatible = "allwinner,sun6i-a31-rtc" },
745 { .compatible = "allwinner,sun8i-a23-rtc" },
746 { .compatible = "allwinner,sun8i-h3-rtc" },
747 { .compatible = "allwinner,sun8i-r40-rtc" },
748 { .compatible = "allwinner,sun8i-v3-rtc" },
749 { .compatible = "allwinner,sun50i-h5-rtc" },
750 { .compatible = "allwinner,sun50i-h6-rtc" },
751 { /* sentinel */ },
752 };
753 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
754
755 static struct platform_driver sun6i_rtc_driver = {
756 .probe = sun6i_rtc_probe,
757 .driver = {
758 .name = "sun6i-rtc",
759 .of_match_table = sun6i_rtc_dt_ids,
760 .pm = &sun6i_rtc_pm_ops,
761 },
762 };
763 builtin_platform_driver(sun6i_rtc_driver);
764