1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright IBM Corp. 2000, 2009
4 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
5 * Jan Glauber <jang@linux.vnet.ibm.com>
6 */
7 #ifndef _CIO_QDIO_H
8 #define _CIO_QDIO_H
9
10 #include <asm/page.h>
11 #include <asm/schid.h>
12 #include <asm/debug.h>
13 #include "chsc.h"
14
15 #define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */
16 #define QDIO_BUSY_BIT_RETRY_DELAY 10 /* 10 milliseconds */
17 #define QDIO_BUSY_BIT_RETRIES 1000 /* = 10s retry time */
18 #define QDIO_INPUT_THRESHOLD (500 << 12) /* 500 microseconds */
19
20 enum qdio_irq_states {
21 QDIO_IRQ_STATE_INACTIVE,
22 QDIO_IRQ_STATE_ESTABLISHED,
23 QDIO_IRQ_STATE_ACTIVE,
24 QDIO_IRQ_STATE_STOPPED,
25 QDIO_IRQ_STATE_CLEANUP,
26 QDIO_IRQ_STATE_ERR,
27 NR_QDIO_IRQ_STATES,
28 };
29
30 /* used as intparm in do_IO */
31 #define QDIO_DOING_ESTABLISH 1
32 #define QDIO_DOING_ACTIVATE 2
33 #define QDIO_DOING_CLEANUP 3
34
35 #define SLSB_STATE_NOT_INIT 0x0
36 #define SLSB_STATE_EMPTY 0x1
37 #define SLSB_STATE_PRIMED 0x2
38 #define SLSB_STATE_PENDING 0x3
39 #define SLSB_STATE_HALTED 0xe
40 #define SLSB_STATE_ERROR 0xf
41 #define SLSB_TYPE_INPUT 0x0
42 #define SLSB_TYPE_OUTPUT 0x20
43 #define SLSB_OWNER_PROG 0x80
44 #define SLSB_OWNER_CU 0x40
45
46 #define SLSB_P_INPUT_NOT_INIT \
47 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT) /* 0x80 */
48 #define SLSB_P_INPUT_ACK \
49 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x81 */
50 #define SLSB_CU_INPUT_EMPTY \
51 (SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x41 */
52 #define SLSB_P_INPUT_PRIMED \
53 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED) /* 0x82 */
54 #define SLSB_P_INPUT_HALTED \
55 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED) /* 0x8e */
56 #define SLSB_P_INPUT_ERROR \
57 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR) /* 0x8f */
58 #define SLSB_P_OUTPUT_NOT_INIT \
59 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */
60 #define SLSB_P_OUTPUT_EMPTY \
61 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY) /* 0xa1 */
62 #define SLSB_P_OUTPUT_PENDING \
63 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_PENDING) /* 0xa3 */
64 #define SLSB_CU_OUTPUT_PRIMED \
65 (SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED) /* 0x62 */
66 #define SLSB_P_OUTPUT_HALTED \
67 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED) /* 0xae */
68 #define SLSB_P_OUTPUT_ERROR \
69 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR) /* 0xaf */
70
71 #define SLSB_ERROR_DURING_LOOKUP 0xff
72
73 /* additional CIWs returned by extended Sense-ID */
74 #define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */
75 #define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */
76
77 /* flags for st qdio sch data */
78 #define CHSC_FLAG_QDIO_CAPABILITY 0x80
79 #define CHSC_FLAG_VALIDITY 0x40
80
81 /* SIGA flags */
82 #define QDIO_SIGA_WRITE 0x00
83 #define QDIO_SIGA_READ 0x01
84 #define QDIO_SIGA_SYNC 0x02
85 #define QDIO_SIGA_WRITEQ 0x04
86 #define QDIO_SIGA_QEBSM_FLAG 0x80
87
do_sqbs(u64 token,unsigned char state,int queue,int * start,int * count)88 static inline int do_sqbs(u64 token, unsigned char state, int queue,
89 int *start, int *count)
90 {
91 unsigned long _queuestart = ((unsigned long)queue << 32) | *start;
92 unsigned long _ccq = *count;
93
94 asm volatile(
95 " lgr 1,%[token]\n"
96 " .insn rsy,0xeb000000008a,%[qs],%[ccq],0(%[state])"
97 : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart)
98 : [state] "a" ((unsigned long)state), [token] "d" (token)
99 : "memory", "cc", "1");
100 *count = _ccq & 0xff;
101 *start = _queuestart & 0xff;
102
103 return (_ccq >> 32) & 0xff;
104 }
105
do_eqbs(u64 token,unsigned char * state,int queue,int * start,int * count,int ack)106 static inline int do_eqbs(u64 token, unsigned char *state, int queue,
107 int *start, int *count, int ack)
108 {
109 unsigned long _queuestart = ((unsigned long)queue << 32) | *start;
110 unsigned long _state = (unsigned long)ack << 63;
111 unsigned long _ccq = *count;
112
113 asm volatile(
114 " lgr 1,%[token]\n"
115 " .insn rrf,0xb99c0000,%[qs],%[state],%[ccq],0"
116 : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart),
117 [state] "+&d" (_state)
118 : [token] "d" (token)
119 : "memory", "cc", "1");
120 *count = _ccq & 0xff;
121 *start = _queuestart & 0xff;
122 *state = _state & 0xff;
123
124 return (_ccq >> 32) & 0xff;
125 }
126
127 struct qdio_irq;
128
129 struct siga_flag {
130 u8 input:1;
131 u8 output:1;
132 u8 sync:1;
133 u8 sync_after_ai:1;
134 u8 sync_out_after_pci:1;
135 u8:3;
136 } __attribute__ ((packed));
137
138 struct qdio_dev_perf_stat {
139 unsigned int adapter_int;
140 unsigned int qdio_int;
141 unsigned int pci_request_int;
142
143 unsigned int tasklet_inbound;
144 unsigned int tasklet_inbound_resched;
145 unsigned int tasklet_inbound_resched2;
146 unsigned int tasklet_outbound;
147
148 unsigned int siga_read;
149 unsigned int siga_write;
150 unsigned int siga_sync;
151
152 unsigned int inbound_call;
153 unsigned int inbound_handler;
154 unsigned int stop_polling;
155 unsigned int inbound_queue_full;
156 unsigned int outbound_call;
157 unsigned int outbound_handler;
158 unsigned int outbound_queue_full;
159 unsigned int fast_requeue;
160 unsigned int target_full;
161 unsigned int eqbs;
162 unsigned int eqbs_partial;
163 unsigned int sqbs;
164 unsigned int sqbs_partial;
165 unsigned int int_discarded;
166 } ____cacheline_aligned;
167
168 struct qdio_queue_perf_stat {
169 /*
170 * Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128.
171 * Since max. 127 SBALs are scanned reuse entry for 128 as queue full
172 * aka 127 SBALs found.
173 */
174 unsigned int nr_sbals[8];
175 unsigned int nr_sbal_error;
176 unsigned int nr_sbal_nop;
177 unsigned int nr_sbal_total;
178 };
179
180 enum qdio_queue_irq_states {
181 QDIO_QUEUE_IRQS_DISABLED,
182 };
183
184 struct qdio_input_q {
185 /* input buffer acknowledgement flag */
186 int polling;
187 /* first ACK'ed buffer */
188 int ack_start;
189 /* how much sbals are acknowledged with qebsm */
190 int ack_count;
191 /* last time of noticing incoming data */
192 u64 timestamp;
193 /* upper-layer polling flag */
194 unsigned long queue_irq_state;
195 /* callback to start upper-layer polling */
196 void (*queue_start_poll) (struct ccw_device *, int, unsigned long);
197 };
198
199 struct qdio_output_q {
200 /* PCIs are enabled for the queue */
201 int pci_out_enabled;
202 /* cq: use asynchronous output buffers */
203 int use_cq;
204 /* cq: aobs used for particual SBAL */
205 struct qaob **aobs;
206 /* cq: sbal state related to asynchronous operation */
207 struct qdio_outbuf_state *sbal_state;
208 /* timer to check for more outbound work */
209 struct timer_list timer;
210 };
211
212 /*
213 * Note on cache alignment: grouped slsb and write mostly data at the beginning
214 * sbal[] is read-only and starts on a new cacheline followed by read mostly.
215 */
216 struct qdio_q {
217 struct slsb slsb;
218
219 union {
220 struct qdio_input_q in;
221 struct qdio_output_q out;
222 } u;
223
224 /*
225 * inbound: next buffer the program should check for
226 * outbound: next buffer to check if adapter processed it
227 */
228 int first_to_check;
229
230 /* beginning position for calling the program */
231 int first_to_kick;
232
233 /* number of buffers in use by the adapter */
234 atomic_t nr_buf_used;
235
236 /* error condition during a data transfer */
237 unsigned int qdio_error;
238
239 /* last scan of the queue */
240 u64 timestamp;
241
242 struct tasklet_struct tasklet;
243 struct qdio_queue_perf_stat q_stats;
244
245 struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;
246
247 /* queue number */
248 int nr;
249
250 /* bitmask of queue number */
251 int mask;
252
253 /* input or output queue */
254 int is_input_q;
255
256 /* list of thinint input queues */
257 struct list_head entry;
258
259 /* upper-layer program handler */
260 qdio_handler_t (*handler);
261
262 struct dentry *debugfs_q;
263 struct qdio_irq *irq_ptr;
264 struct sl *sl;
265 /*
266 * A page is allocated under this pointer and used for slib and sl.
267 * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2.
268 */
269 struct slib *slib;
270 } __attribute__ ((aligned(256)));
271
272 struct qdio_irq {
273 struct qib qib;
274 u32 *dsci; /* address of device state change indicator */
275 struct ccw_device *cdev;
276 struct dentry *debugfs_dev;
277 struct dentry *debugfs_perf;
278
279 unsigned long int_parm;
280 struct subchannel_id schid;
281 unsigned long sch_token; /* QEBSM facility */
282
283 enum qdio_irq_states state;
284
285 struct siga_flag siga_flag; /* siga sync information from qdioac */
286
287 int nr_input_qs;
288 int nr_output_qs;
289
290 struct ccw1 ccw;
291 struct ciw equeue;
292 struct ciw aqueue;
293
294 struct qdio_ssqd_desc ssqd_desc;
295 void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *);
296
297 unsigned int scan_threshold; /* used SBALs before tasklet schedule */
298 int perf_stat_enabled;
299
300 struct qdr *qdr;
301 unsigned long chsc_page;
302
303 struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ];
304 struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ];
305
306 debug_info_t *debug_area;
307 struct mutex setup_mutex;
308 struct qdio_dev_perf_stat perf_stat;
309 };
310
311 /* helper functions */
312 #define queue_type(q) q->irq_ptr->qib.qfmt
313 #define SCH_NO(q) (q->irq_ptr->schid.sch_no)
314
315 #define is_thinint_irq(irq) \
316 (irq->qib.qfmt == QDIO_IQDIO_QFMT || \
317 css_general_characteristics.aif_osa)
318
319 #define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr))
320
321 #define qperf_inc(__q, __attr) \
322 ({ \
323 struct qdio_irq *qdev = (__q)->irq_ptr; \
324 if (qdev->perf_stat_enabled) \
325 (qdev->perf_stat.__attr)++; \
326 })
327
account_sbals_error(struct qdio_q * q,int count)328 static inline void account_sbals_error(struct qdio_q *q, int count)
329 {
330 q->q_stats.nr_sbal_error += count;
331 q->q_stats.nr_sbal_total += count;
332 }
333
334 /* the highest iqdio queue is used for multicast */
multicast_outbound(struct qdio_q * q)335 static inline int multicast_outbound(struct qdio_q *q)
336 {
337 return (q->irq_ptr->nr_output_qs > 1) &&
338 (q->nr == q->irq_ptr->nr_output_qs - 1);
339 }
340
341 #define pci_out_supported(irq) ((irq)->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)
342 #define is_qebsm(q) (q->irq_ptr->sch_token != 0)
343
344 #define need_siga_in(q) (q->irq_ptr->siga_flag.input)
345 #define need_siga_out(q) (q->irq_ptr->siga_flag.output)
346 #define need_siga_sync(q) (unlikely(q->irq_ptr->siga_flag.sync))
347 #define need_siga_sync_after_ai(q) \
348 (unlikely(q->irq_ptr->siga_flag.sync_after_ai))
349 #define need_siga_sync_out_after_pci(q) \
350 (unlikely(q->irq_ptr->siga_flag.sync_out_after_pci))
351
352 #define for_each_input_queue(irq_ptr, q, i) \
353 for (i = 0; i < irq_ptr->nr_input_qs && \
354 ({ q = irq_ptr->input_qs[i]; 1; }); i++)
355 #define for_each_output_queue(irq_ptr, q, i) \
356 for (i = 0; i < irq_ptr->nr_output_qs && \
357 ({ q = irq_ptr->output_qs[i]; 1; }); i++)
358
359 #define prev_buf(bufnr) \
360 ((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK)
361 #define next_buf(bufnr) \
362 ((bufnr + 1) & QDIO_MAX_BUFFERS_MASK)
363 #define add_buf(bufnr, inc) \
364 ((bufnr + inc) & QDIO_MAX_BUFFERS_MASK)
365 #define sub_buf(bufnr, dec) \
366 ((bufnr - dec) & QDIO_MAX_BUFFERS_MASK)
367
368 #define queue_irqs_enabled(q) \
369 (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0)
370 #define queue_irqs_disabled(q) \
371 (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0)
372
373 extern u64 last_ai_time;
374
375 /* prototypes for thin interrupt */
376 int qdio_establish_thinint(struct qdio_irq *irq_ptr);
377 void qdio_shutdown_thinint(struct qdio_irq *irq_ptr);
378 void tiqdio_add_input_queues(struct qdio_irq *irq_ptr);
379 void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr);
380 void tiqdio_inbound_processing(unsigned long q);
381 int tiqdio_allocate_memory(void);
382 void tiqdio_free_memory(void);
383 int tiqdio_register_thinints(void);
384 void tiqdio_unregister_thinints(void);
385 void clear_nonshared_ind(struct qdio_irq *);
386 int test_nonshared_ind(struct qdio_irq *);
387
388 /* prototypes for setup */
389 void qdio_inbound_processing(unsigned long data);
390 void qdio_outbound_processing(unsigned long data);
391 void qdio_outbound_timer(struct timer_list *t);
392 void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm,
393 struct irb *irb);
394 int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs,
395 int nr_output_qs);
396 void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr);
397 int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
398 struct subchannel_id *schid,
399 struct qdio_ssqd_desc *data);
400 int qdio_setup_irq(struct qdio_initialize *init_data);
401 void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
402 struct ccw_device *cdev);
403 void qdio_release_memory(struct qdio_irq *irq_ptr);
404 int qdio_setup_create_sysfs(struct ccw_device *cdev);
405 void qdio_setup_destroy_sysfs(struct ccw_device *cdev);
406 int qdio_setup_init(void);
407 void qdio_setup_exit(void);
408 int qdio_enable_async_operation(struct qdio_output_q *q);
409 void qdio_disable_async_operation(struct qdio_output_q *q);
410 struct qaob *qdio_allocate_aob(void);
411
412 int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr,
413 unsigned char *state);
414 #endif /* _CIO_QDIO_H */
415