1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * drivers/usb/gadget/emxx_udc.c
4 * EMXX FCD (Function Controller Driver) for USB.
5 *
6 * Copyright (C) 2010 Renesas Electronics Corporation
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/delay.h>
13 #include <linux/ioport.h>
14 #include <linux/slab.h>
15 #include <linux/errno.h>
16 #include <linux/list.h>
17 #include <linux/interrupt.h>
18 #include <linux/proc_fs.h>
19 #include <linux/clk.h>
20 #include <linux/ctype.h>
21 #include <linux/string.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/workqueue.h>
24 #include <linux/device.h>
25
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
28
29 #include <linux/irq.h>
30 #include <linux/gpio/consumer.h>
31
32 #include "emxx_udc.h"
33
34 #define DRIVER_DESC "EMXX UDC driver"
35 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
36
37 static const char driver_name[] = "emxx_udc";
38 static const char driver_desc[] = DRIVER_DESC;
39
40 /*===========================================================================*/
41 /* Prototype */
42 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
43 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
44 /*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/
45 static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
46 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
47 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
48
49 static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
50 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
51
52 /*===========================================================================*/
53 /* Macro */
54 #define _nbu2ss_zero_len_pkt(udc, epnum) \
55 _nbu2ss_ep_in_end(udc, epnum, 0, 0)
56
57 /*===========================================================================*/
58 /* Global */
59 static struct nbu2ss_udc udc_controller;
60
61 /*-------------------------------------------------------------------------*/
62 /* Read */
_nbu2ss_readl(void __iomem * address)63 static inline u32 _nbu2ss_readl(void __iomem *address)
64 {
65 return __raw_readl(address);
66 }
67
68 /*-------------------------------------------------------------------------*/
69 /* Write */
_nbu2ss_writel(void __iomem * address,u32 udata)70 static inline void _nbu2ss_writel(void __iomem *address, u32 udata)
71 {
72 __raw_writel(udata, address);
73 }
74
75 /*-------------------------------------------------------------------------*/
76 /* Set Bit */
_nbu2ss_bitset(void __iomem * address,u32 udata)77 static inline void _nbu2ss_bitset(void __iomem *address, u32 udata)
78 {
79 u32 reg_dt = __raw_readl(address) | (udata);
80
81 __raw_writel(reg_dt, address);
82 }
83
84 /*-------------------------------------------------------------------------*/
85 /* Clear Bit */
_nbu2ss_bitclr(void __iomem * address,u32 udata)86 static inline void _nbu2ss_bitclr(void __iomem *address, u32 udata)
87 {
88 u32 reg_dt = __raw_readl(address) & ~(udata);
89
90 __raw_writel(reg_dt, address);
91 }
92
93 #ifdef UDC_DEBUG_DUMP
94 /*-------------------------------------------------------------------------*/
_nbu2ss_dump_register(struct nbu2ss_udc * udc)95 static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
96 {
97 int i;
98 u32 reg_data;
99
100 pr_info("=== %s()\n", __func__);
101
102 if (!udc) {
103 pr_err("%s udc == NULL\n", __func__);
104 return;
105 }
106
107 spin_unlock(&udc->lock);
108
109 dev_dbg(&udc->dev, "\n-USB REG-\n");
110 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
111 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i));
112 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
113
114 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
115 dev_dbg(&udc->dev, " %08x", (int)reg_data);
116
117 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
118 dev_dbg(&udc->dev, " %08x", (int)reg_data);
119
120 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
121 dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
122 }
123
124 spin_lock(&udc->lock);
125 }
126 #endif /* UDC_DEBUG_DUMP */
127
128 /*-------------------------------------------------------------------------*/
129 /* Endpoint 0 Callback (Complete) */
_nbu2ss_ep0_complete(struct usb_ep * _ep,struct usb_request * _req)130 static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
131 {
132 u8 recipient;
133 u16 selector;
134 u16 wIndex;
135 u32 test_mode;
136 struct usb_ctrlrequest *p_ctrl;
137 struct nbu2ss_udc *udc;
138
139 if (!_ep || !_req)
140 return;
141
142 udc = (struct nbu2ss_udc *)_req->context;
143 p_ctrl = &udc->ctrl;
144 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
145 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
146 /*-------------------------------------------------*/
147 /* SET_FEATURE */
148 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
149 selector = le16_to_cpu(p_ctrl->wValue);
150 if ((recipient == USB_RECIP_DEVICE) &&
151 (selector == USB_DEVICE_TEST_MODE)) {
152 wIndex = le16_to_cpu(p_ctrl->wIndex);
153 test_mode = (u32)(wIndex >> 8);
154 _nbu2ss_set_test_mode(udc, test_mode);
155 }
156 }
157 }
158 }
159
160 /*-------------------------------------------------------------------------*/
161 /* Initialization usb_request */
_nbu2ss_create_ep0_packet(struct nbu2ss_udc * udc,void * p_buf,unsigned int length)162 static void _nbu2ss_create_ep0_packet(struct nbu2ss_udc *udc,
163 void *p_buf, unsigned int length)
164 {
165 udc->ep0_req.req.buf = p_buf;
166 udc->ep0_req.req.length = length;
167 udc->ep0_req.req.dma = 0;
168 udc->ep0_req.req.zero = true;
169 udc->ep0_req.req.complete = _nbu2ss_ep0_complete;
170 udc->ep0_req.req.status = -EINPROGRESS;
171 udc->ep0_req.req.context = udc;
172 udc->ep0_req.req.actual = 0;
173 }
174
175 /*-------------------------------------------------------------------------*/
176 /* Acquisition of the first address of RAM(FIFO) */
_nbu2ss_get_begin_ram_address(struct nbu2ss_udc * udc)177 static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
178 {
179 u32 num, buf_type;
180 u32 data, last_ram_adr, use_ram_size;
181
182 struct ep_regs __iomem *p_ep_regs;
183
184 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
185 use_ram_size = 0;
186
187 for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
188 p_ep_regs = &udc->p_regs->EP_REGS[num];
189 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
190 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE;
191 if (buf_type == 0) {
192 /* Single Buffer */
193 use_ram_size += (data & EPN_MPKT) / sizeof(u32);
194 } else {
195 /* Double Buffer */
196 use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2;
197 }
198
199 if ((data >> 16) > last_ram_adr)
200 last_ram_adr = data >> 16;
201 }
202
203 return last_ram_adr + use_ram_size;
204 }
205
206 /*-------------------------------------------------------------------------*/
207 /* Construction of Endpoint */
_nbu2ss_ep_init(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)208 static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
209 {
210 u32 num;
211 u32 data;
212 u32 begin_adrs;
213
214 if (ep->epnum == 0)
215 return -EINVAL;
216
217 num = ep->epnum - 1;
218
219 /*-------------------------------------------------------------*/
220 /* RAM Transfer Address */
221 begin_adrs = _nbu2ss_get_begin_ram_address(udc);
222 data = (begin_adrs << 16) | ep->ep.maxpacket;
223 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
224
225 /*-------------------------------------------------------------*/
226 /* Interrupt Enable */
227 data = 1 << (ep->epnum + 8);
228 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
229
230 /*-------------------------------------------------------------*/
231 /* Endpoint Type(Mode) */
232 /* Bulk, Interrupt, ISO */
233 switch (ep->ep_type) {
234 case USB_ENDPOINT_XFER_BULK:
235 data = EPN_BULK;
236 break;
237
238 case USB_ENDPOINT_XFER_INT:
239 data = EPN_BUF_SINGLE | EPN_INTERRUPT;
240 break;
241
242 case USB_ENDPOINT_XFER_ISOC:
243 data = EPN_ISO;
244 break;
245
246 default:
247 data = 0;
248 break;
249 }
250
251 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
252 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum | ep->direct));
253
254 if (ep->direct == USB_DIR_OUT) {
255 /*---------------------------------------------------------*/
256 /* OUT */
257 data = EPN_EN | EPN_BCLR | EPN_DIR0;
258 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
259
260 data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL;
261 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
262
263 data = EPN_OUT_EN | EPN_OUT_END_EN;
264 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
265 } else {
266 /*---------------------------------------------------------*/
267 /* IN */
268 data = EPN_EN | EPN_BCLR | EPN_AUTO;
269 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
270
271 data = EPN_ISTL;
272 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
273
274 data = EPN_IN_EN | EPN_IN_END_EN;
275 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
276 }
277
278 return 0;
279 }
280
281 /*-------------------------------------------------------------------------*/
282 /* Release of Endpoint */
_nbu2ss_epn_exit(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)283 static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
284 {
285 u32 num;
286 u32 data;
287
288 if ((ep->epnum == 0) || (udc->vbus_active == 0))
289 return -EINVAL;
290
291 num = ep->epnum - 1;
292
293 /*-------------------------------------------------------------*/
294 /* RAM Transfer Address */
295 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
296
297 /*-------------------------------------------------------------*/
298 /* Interrupt Disable */
299 data = 1 << (ep->epnum + 8);
300 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
301
302 if (ep->direct == USB_DIR_OUT) {
303 /*---------------------------------------------------------*/
304 /* OUT */
305 data = EPN_ONAK | EPN_BCLR;
306 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
307
308 data = EPN_EN | EPN_DIR0;
309 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
310
311 data = EPN_OUT_EN | EPN_OUT_END_EN;
312 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
313 } else {
314 /*---------------------------------------------------------*/
315 /* IN */
316 data = EPN_BCLR;
317 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
318
319 data = EPN_EN | EPN_AUTO;
320 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
321
322 data = EPN_IN_EN | EPN_IN_END_EN;
323 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
324 }
325
326 return 0;
327 }
328
329 /*-------------------------------------------------------------------------*/
330 /* DMA setting (without Endpoint 0) */
_nbu2ss_ep_dma_init(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)331 static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
332 {
333 u32 num;
334 u32 data;
335
336 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
337 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
338 return; /* Not Support DMA */
339
340 num = ep->epnum - 1;
341
342 if (ep->direct == USB_DIR_OUT) {
343 /*---------------------------------------------------------*/
344 /* OUT */
345 data = ep->ep.maxpacket;
346 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
347
348 /*---------------------------------------------------------*/
349 /* Transfer Direct */
350 data = DCR1_EPN_DIR0;
351 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
352
353 /*---------------------------------------------------------*/
354 /* DMA Mode etc. */
355 data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0;
356 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
357 } else {
358 /*---------------------------------------------------------*/
359 /* IN */
360 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO);
361
362 /*---------------------------------------------------------*/
363 /* DMA Mode etc. */
364 data = EPN_BURST_SET | EPN_DMAMODE0;
365 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
366 }
367 }
368
369 /*-------------------------------------------------------------------------*/
370 /* DMA setting release */
_nbu2ss_ep_dma_exit(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)371 static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
372 {
373 u32 num;
374 u32 data;
375 struct fc_regs __iomem *preg = udc->p_regs;
376
377 if (udc->vbus_active == 0)
378 return; /* VBUS OFF */
379
380 data = _nbu2ss_readl(&preg->USBSSCONF);
381 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
382 return; /* Not Support DMA */
383
384 num = ep->epnum - 1;
385
386 _nbu2ss_ep_dma_abort(udc, ep);
387
388 if (ep->direct == USB_DIR_OUT) {
389 /*---------------------------------------------------------*/
390 /* OUT */
391 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
392 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0);
393 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
394 } else {
395 /*---------------------------------------------------------*/
396 /* IN */
397 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
398 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
399 }
400 }
401
402 /*-------------------------------------------------------------------------*/
403 /* Abort DMA */
_nbu2ss_ep_dma_abort(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)404 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
405 {
406 struct fc_regs __iomem *preg = udc->p_regs;
407
408 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN);
409 mdelay(DMA_DISABLE_TIME); /* DCR1_EPN_REQEN Clear */
410 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN);
411 }
412
413 /*-------------------------------------------------------------------------*/
414 /* Start IN Transfer */
_nbu2ss_ep_in_end(struct nbu2ss_udc * udc,u32 epnum,u32 data32,u32 length)415 static void _nbu2ss_ep_in_end(struct nbu2ss_udc *udc,
416 u32 epnum, u32 data32, u32 length)
417 {
418 u32 data;
419 u32 num;
420 struct fc_regs __iomem *preg = udc->p_regs;
421
422 if (length >= sizeof(u32))
423 return;
424
425 if (epnum == 0) {
426 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
427
428 /* Writing of 1-4 bytes */
429 if (length)
430 _nbu2ss_writel(&preg->EP0_WRITE, data32);
431
432 data = ((length << 5) & EP0_DW) | EP0_DEND;
433 _nbu2ss_writel(&preg->EP0_CONTROL, data);
434
435 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
436 } else {
437 num = epnum - 1;
438
439 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
440
441 /* Writing of 1-4 bytes */
442 if (length)
443 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
444
445 data = (((length) << 5) & EPN_DW) | EPN_DEND;
446 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
447
448 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
449 }
450 }
451
452 #ifdef USE_DMA
453 /*-------------------------------------------------------------------------*/
_nbu2ss_dma_map_single(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u8 direct)454 static void _nbu2ss_dma_map_single(struct nbu2ss_udc *udc,
455 struct nbu2ss_ep *ep,
456 struct nbu2ss_req *req, u8 direct)
457 {
458 if (req->req.dma == DMA_ADDR_INVALID) {
459 if (req->unaligned) {
460 req->req.dma = ep->phys_buf;
461 } else {
462 req->req.dma = dma_map_single(udc->gadget.dev.parent,
463 req->req.buf,
464 req->req.length,
465 (direct == USB_DIR_IN)
466 ? DMA_TO_DEVICE
467 : DMA_FROM_DEVICE);
468 }
469 req->mapped = 1;
470 } else {
471 if (!req->unaligned)
472 dma_sync_single_for_device(udc->gadget.dev.parent,
473 req->req.dma,
474 req->req.length,
475 (direct == USB_DIR_IN)
476 ? DMA_TO_DEVICE
477 : DMA_FROM_DEVICE);
478
479 req->mapped = 0;
480 }
481 }
482
483 /*-------------------------------------------------------------------------*/
_nbu2ss_dma_unmap_single(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u8 direct)484 static void _nbu2ss_dma_unmap_single(struct nbu2ss_udc *udc,
485 struct nbu2ss_ep *ep,
486 struct nbu2ss_req *req, u8 direct)
487 {
488 u8 data[4];
489 u8 *p;
490 u32 count = 0;
491
492 if (direct == USB_DIR_OUT) {
493 count = req->req.actual % 4;
494 if (count) {
495 p = req->req.buf;
496 p += (req->req.actual - count);
497 memcpy(data, p, count);
498 }
499 }
500
501 if (req->mapped) {
502 if (req->unaligned) {
503 if (direct == USB_DIR_OUT)
504 memcpy(req->req.buf, ep->virt_buf,
505 req->req.actual & 0xfffffffc);
506 } else {
507 dma_unmap_single(udc->gadget.dev.parent,
508 req->req.dma, req->req.length,
509 (direct == USB_DIR_IN)
510 ? DMA_TO_DEVICE
511 : DMA_FROM_DEVICE);
512 }
513 req->req.dma = DMA_ADDR_INVALID;
514 req->mapped = 0;
515 } else {
516 if (!req->unaligned)
517 dma_sync_single_for_cpu(udc->gadget.dev.parent,
518 req->req.dma, req->req.length,
519 (direct == USB_DIR_IN)
520 ? DMA_TO_DEVICE
521 : DMA_FROM_DEVICE);
522 }
523
524 if (count) {
525 p = req->req.buf;
526 p += (req->req.actual - count);
527 memcpy(p, data, count);
528 }
529 }
530 #endif
531
532 /*-------------------------------------------------------------------------*/
533 /* Endpoint 0 OUT Transfer (PIO) */
ep0_out_pio(struct nbu2ss_udc * udc,u8 * buf,u32 length)534 static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length)
535 {
536 u32 i;
537 u32 numreads = length / sizeof(u32);
538 union usb_reg_access *buf32 = (union usb_reg_access *)buf;
539
540 if (!numreads)
541 return 0;
542
543 /* PIO Read */
544 for (i = 0; i < numreads; i++) {
545 buf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
546 buf32++;
547 }
548
549 return numreads * sizeof(u32);
550 }
551
552 /*-------------------------------------------------------------------------*/
553 /* Endpoint 0 OUT Transfer (PIO, OverBytes) */
ep0_out_overbytes(struct nbu2ss_udc * udc,u8 * p_buf,u32 length)554 static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
555 {
556 u32 i;
557 u32 i_read_size = 0;
558 union usb_reg_access temp_32;
559 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
560
561 if ((length > 0) && (length < sizeof(u32))) {
562 temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
563 for (i = 0 ; i < length ; i++)
564 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
565 i_read_size += length;
566 }
567
568 return i_read_size;
569 }
570
571 /*-------------------------------------------------------------------------*/
572 /* Endpoint 0 IN Transfer (PIO) */
EP0_in_PIO(struct nbu2ss_udc * udc,u8 * p_buf,u32 length)573 static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
574 {
575 u32 i;
576 u32 i_max_length = EP0_PACKETSIZE;
577 u32 i_word_length = 0;
578 u32 i_write_length = 0;
579 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
580
581 /*------------------------------------------------------------*/
582 /* Transfer Length */
583 if (i_max_length < length)
584 i_word_length = i_max_length / sizeof(u32);
585 else
586 i_word_length = length / sizeof(u32);
587
588 /*------------------------------------------------------------*/
589 /* PIO */
590 for (i = 0; i < i_word_length; i++) {
591 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw);
592 p_buf_32++;
593 i_write_length += sizeof(u32);
594 }
595
596 return i_write_length;
597 }
598
599 /*-------------------------------------------------------------------------*/
600 /* Endpoint 0 IN Transfer (PIO, OverBytes) */
ep0_in_overbytes(struct nbu2ss_udc * udc,u8 * p_buf,u32 i_remain_size)601 static int ep0_in_overbytes(struct nbu2ss_udc *udc,
602 u8 *p_buf,
603 u32 i_remain_size)
604 {
605 u32 i;
606 union usb_reg_access temp_32;
607 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
608
609 if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) {
610 for (i = 0 ; i < i_remain_size ; i++)
611 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
612 _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size);
613
614 return i_remain_size;
615 }
616
617 return 0;
618 }
619
620 /*-------------------------------------------------------------------------*/
621 /* Transfer NULL Packet (Epndoint 0) */
EP0_send_NULL(struct nbu2ss_udc * udc,bool pid_flag)622 static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
623 {
624 u32 data;
625
626 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
627 data &= ~(u32)EP0_INAK;
628
629 if (pid_flag)
630 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
631 else
632 data |= (EP0_INAK_EN | EP0_DEND);
633
634 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
635
636 return 0;
637 }
638
639 /*-------------------------------------------------------------------------*/
640 /* Receive NULL Packet (Endpoint 0) */
EP0_receive_NULL(struct nbu2ss_udc * udc,bool pid_flag)641 static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
642 {
643 u32 data;
644
645 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
646 data &= ~(u32)EP0_ONAK;
647
648 if (pid_flag)
649 data |= EP0_PIDCLR;
650
651 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
652
653 return 0;
654 }
655
656 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_in_transfer(struct nbu2ss_udc * udc,struct nbu2ss_req * req)657 static int _nbu2ss_ep0_in_transfer(struct nbu2ss_udc *udc,
658 struct nbu2ss_req *req)
659 {
660 u8 *p_buffer; /* IN Data Buffer */
661 u32 data;
662 u32 i_remain_size = 0;
663 int result = 0;
664
665 /*-------------------------------------------------------------*/
666 /* End confirmation */
667 if (req->req.actual == req->req.length) {
668 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
669 if (req->zero) {
670 req->zero = false;
671 EP0_send_NULL(udc, false);
672 return 1;
673 }
674 }
675
676 return 0; /* Transfer End */
677 }
678
679 /*-------------------------------------------------------------*/
680 /* NAK release */
681 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
682 data |= EP0_INAK_EN;
683 data &= ~(u32)EP0_INAK;
684 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
685
686 i_remain_size = req->req.length - req->req.actual;
687 p_buffer = (u8 *)req->req.buf;
688 p_buffer += req->req.actual;
689
690 /*-------------------------------------------------------------*/
691 /* Data transfer */
692 result = EP0_in_PIO(udc, p_buffer, i_remain_size);
693
694 req->div_len = result;
695 i_remain_size -= result;
696
697 if (i_remain_size == 0) {
698 EP0_send_NULL(udc, false);
699 return result;
700 }
701
702 if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
703 p_buffer += result;
704 result += ep0_in_overbytes(udc, p_buffer, i_remain_size);
705 req->div_len = result;
706 }
707
708 return result;
709 }
710
711 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_out_transfer(struct nbu2ss_udc * udc,struct nbu2ss_req * req)712 static int _nbu2ss_ep0_out_transfer(struct nbu2ss_udc *udc,
713 struct nbu2ss_req *req)
714 {
715 u8 *p_buffer;
716 u32 i_remain_size;
717 u32 i_recv_length;
718 int result = 0;
719 int f_rcv_zero;
720
721 /*-------------------------------------------------------------*/
722 /* Receive data confirmation */
723 i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
724 if (i_recv_length != 0) {
725 f_rcv_zero = 0;
726
727 i_remain_size = req->req.length - req->req.actual;
728 p_buffer = (u8 *)req->req.buf;
729 p_buffer += req->req.actual;
730
731 result = ep0_out_pio(udc, p_buffer
732 , min(i_remain_size, i_recv_length));
733 if (result < 0)
734 return result;
735
736 req->req.actual += result;
737 i_recv_length -= result;
738
739 if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) {
740 p_buffer += result;
741 i_remain_size -= result;
742
743 result = ep0_out_overbytes(udc, p_buffer
744 , min(i_remain_size, i_recv_length));
745 req->req.actual += result;
746 }
747 } else {
748 f_rcv_zero = 1;
749 }
750
751 /*-------------------------------------------------------------*/
752 /* End confirmation */
753 if (req->req.actual == req->req.length) {
754 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
755 if (req->zero) {
756 req->zero = false;
757 EP0_receive_NULL(udc, false);
758 return 1;
759 }
760 }
761
762 return 0; /* Transfer End */
763 }
764
765 if ((req->req.actual % EP0_PACKETSIZE) != 0)
766 return 0; /* Short Packet Transfer End */
767
768 if (req->req.actual > req->req.length) {
769 dev_err(udc->dev, " *** Overrun Error\n");
770 return -EOVERFLOW;
771 }
772
773 if (f_rcv_zero != 0) {
774 i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
775 if (i_remain_size & EP0_ONAK) {
776 /*---------------------------------------------------*/
777 /* NACK release */
778 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
779 }
780 result = 1;
781 }
782
783 return result;
784 }
785
786 /*-------------------------------------------------------------------------*/
_nbu2ss_out_dma(struct nbu2ss_udc * udc,struct nbu2ss_req * req,u32 num,u32 length)787 static int _nbu2ss_out_dma(struct nbu2ss_udc *udc, struct nbu2ss_req *req,
788 u32 num, u32 length)
789 {
790 dma_addr_t p_buffer;
791 u32 mpkt;
792 u32 lmpkt;
793 u32 dmacnt;
794 u32 burst = 1;
795 u32 data;
796 int result = -EINVAL;
797 struct fc_regs __iomem *preg = udc->p_regs;
798
799 if (req->dma_flag)
800 return 1; /* DMA is forwarded */
801
802 req->dma_flag = true;
803 p_buffer = req->req.dma;
804 p_buffer += req->req.actual;
805
806 /* DMA Address */
807 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
808
809 /* Number of transfer packets */
810 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
811 dmacnt = length / mpkt;
812 lmpkt = (length % mpkt) & ~(u32)0x03;
813
814 if (dmacnt > DMA_MAX_COUNT) {
815 dmacnt = DMA_MAX_COUNT;
816 lmpkt = 0;
817 } else if (lmpkt != 0) {
818 if (dmacnt == 0)
819 burst = 0; /* Burst OFF */
820 dmacnt++;
821 }
822
823 data = mpkt | (lmpkt << 16);
824 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
825
826 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN;
827 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
828
829 if (burst == 0) {
830 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
831 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
832 } else {
833 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
834 , (dmacnt << 16));
835 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
836 }
837 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
838
839 result = length & ~(u32)0x03;
840 req->div_len = result;
841
842 return result;
843 }
844
845 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_pio(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 length)846 static int _nbu2ss_epn_out_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
847 struct nbu2ss_req *req, u32 length)
848 {
849 u8 *p_buffer;
850 u32 i;
851 u32 data;
852 u32 i_word_length;
853 union usb_reg_access temp_32;
854 union usb_reg_access *p_buf_32;
855 int result = 0;
856 struct fc_regs __iomem *preg = udc->p_regs;
857
858 if (req->dma_flag)
859 return 1; /* DMA is forwarded */
860
861 if (length == 0)
862 return 0;
863
864 p_buffer = (u8 *)req->req.buf;
865 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
866
867 i_word_length = length / sizeof(u32);
868 if (i_word_length > 0) {
869 /*---------------------------------------------------------*/
870 /* Copy of every four bytes */
871 for (i = 0; i < i_word_length; i++) {
872 p_buf_32->dw =
873 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
874 p_buf_32++;
875 }
876 result = i_word_length * sizeof(u32);
877 }
878
879 data = length - result;
880 if (data > 0) {
881 /*---------------------------------------------------------*/
882 /* Copy of fraction byte */
883 temp_32.dw =
884 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
885 for (i = 0 ; i < data ; i++)
886 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
887 result += data;
888 }
889
890 req->req.actual += result;
891
892 if ((req->req.actual == req->req.length) ||
893 ((req->req.actual % ep->ep.maxpacket) != 0)) {
894 result = 0;
895 }
896
897 return result;
898 }
899
900 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_data(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 data_size)901 static int _nbu2ss_epn_out_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
902 struct nbu2ss_req *req, u32 data_size)
903 {
904 u32 num;
905 u32 i_buf_size;
906 int nret = 1;
907
908 if (ep->epnum == 0)
909 return -EINVAL;
910
911 num = ep->epnum - 1;
912
913 i_buf_size = min((req->req.length - req->req.actual), data_size);
914
915 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
916 (i_buf_size >= sizeof(u32))) {
917 nret = _nbu2ss_out_dma(udc, req, num, i_buf_size);
918 } else {
919 i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket);
920 nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size);
921 }
922
923 return nret;
924 }
925
926 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)927 static int _nbu2ss_epn_out_transfer(struct nbu2ss_udc *udc,
928 struct nbu2ss_ep *ep,
929 struct nbu2ss_req *req)
930 {
931 u32 num;
932 u32 i_recv_length;
933 int result = 1;
934 struct fc_regs __iomem *preg = udc->p_regs;
935
936 if (ep->epnum == 0)
937 return -EINVAL;
938
939 num = ep->epnum - 1;
940
941 /*-------------------------------------------------------------*/
942 /* Receive Length */
943 i_recv_length =
944 _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA;
945
946 if (i_recv_length != 0) {
947 result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length);
948 if (i_recv_length < ep->ep.maxpacket) {
949 if (i_recv_length == result) {
950 req->req.actual += result;
951 result = 0;
952 }
953 }
954 } else {
955 if ((req->req.actual == req->req.length) ||
956 ((req->req.actual % ep->ep.maxpacket) != 0)) {
957 result = 0;
958 }
959 }
960
961 if (result == 0) {
962 if ((req->req.actual % ep->ep.maxpacket) == 0) {
963 if (req->zero) {
964 req->zero = false;
965 return 1;
966 }
967 }
968 }
969
970 if (req->req.actual > req->req.length) {
971 dev_err(udc->dev, " Overrun Error\n");
972 dev_err(udc->dev, " actual = %d, length = %d\n",
973 req->req.actual, req->req.length);
974 result = -EOVERFLOW;
975 }
976
977 return result;
978 }
979
980 /*-------------------------------------------------------------------------*/
_nbu2ss_in_dma(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 num,u32 length)981 static int _nbu2ss_in_dma(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
982 struct nbu2ss_req *req, u32 num, u32 length)
983 {
984 dma_addr_t p_buffer;
985 u32 mpkt; /* MaxPacketSize */
986 u32 lmpkt; /* Last Packet Data Size */
987 u32 dmacnt; /* IN Data Size */
988 u32 i_write_length;
989 u32 data;
990 int result = -EINVAL;
991 struct fc_regs __iomem *preg = udc->p_regs;
992
993 if (req->dma_flag)
994 return 1; /* DMA is forwarded */
995
996 #ifdef USE_DMA
997 if (req->req.actual == 0)
998 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
999 #endif
1000 req->dma_flag = true;
1001
1002 /* MAX Packet Size */
1003 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
1004
1005 if ((DMA_MAX_COUNT * mpkt) < length)
1006 i_write_length = DMA_MAX_COUNT * mpkt;
1007 else
1008 i_write_length = length;
1009
1010 /*------------------------------------------------------------*/
1011 /* Number of transmission packets */
1012 if (mpkt < i_write_length) {
1013 dmacnt = i_write_length / mpkt;
1014 lmpkt = (i_write_length % mpkt) & ~(u32)0x3;
1015 if (lmpkt != 0)
1016 dmacnt++;
1017 else
1018 lmpkt = mpkt & ~(u32)0x3;
1019
1020 } else {
1021 dmacnt = 1;
1022 lmpkt = i_write_length & ~(u32)0x3;
1023 }
1024
1025 /* Packet setting */
1026 data = mpkt | (lmpkt << 16);
1027 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1028
1029 /* Address setting */
1030 p_buffer = req->req.dma;
1031 p_buffer += req->req.actual;
1032 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
1033
1034 /* Packet and DMA setting */
1035 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN;
1036 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1037
1038 /* Packet setting of EPC */
1039 data = dmacnt << 16;
1040 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1041
1042 /*DMA setting of EPC */
1043 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
1044
1045 result = i_write_length & ~(u32)0x3;
1046 req->div_len = result;
1047
1048 return result;
1049 }
1050
1051 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_pio(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 length)1052 static int _nbu2ss_epn_in_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1053 struct nbu2ss_req *req, u32 length)
1054 {
1055 u8 *p_buffer;
1056 u32 i;
1057 u32 data;
1058 u32 i_word_length;
1059 union usb_reg_access temp_32;
1060 union usb_reg_access *p_buf_32 = NULL;
1061 int result = 0;
1062 struct fc_regs __iomem *preg = udc->p_regs;
1063
1064 if (req->dma_flag)
1065 return 1; /* DMA is forwarded */
1066
1067 if (length > 0) {
1068 p_buffer = (u8 *)req->req.buf;
1069 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
1070
1071 i_word_length = length / sizeof(u32);
1072 if (i_word_length > 0) {
1073 for (i = 0; i < i_word_length; i++) {
1074 _nbu2ss_writel(
1075 &preg->EP_REGS[ep->epnum - 1].EP_WRITE
1076 , p_buf_32->dw
1077 );
1078
1079 p_buf_32++;
1080 }
1081 result = i_word_length * sizeof(u32);
1082 }
1083 }
1084
1085 if (result != ep->ep.maxpacket) {
1086 data = length - result;
1087 temp_32.dw = 0;
1088 for (i = 0 ; i < data ; i++)
1089 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
1090
1091 _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data);
1092 result += data;
1093 }
1094
1095 req->div_len = result;
1096
1097 return result;
1098 }
1099
1100 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_data(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,u32 data_size)1101 static int _nbu2ss_epn_in_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1102 struct nbu2ss_req *req, u32 data_size)
1103 {
1104 u32 num;
1105 int nret = 1;
1106
1107 if (ep->epnum == 0)
1108 return -EINVAL;
1109
1110 num = ep->epnum - 1;
1111
1112 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
1113 (data_size >= sizeof(u32))) {
1114 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1115 } else {
1116 data_size = min_t(u32, data_size, ep->ep.maxpacket);
1117 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1118 }
1119
1120 return nret;
1121 }
1122
1123 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1124 static int _nbu2ss_epn_in_transfer(struct nbu2ss_udc *udc,
1125 struct nbu2ss_ep *ep, struct nbu2ss_req *req)
1126 {
1127 u32 num;
1128 u32 i_buf_size;
1129 int result = 0;
1130 u32 status;
1131
1132 if (ep->epnum == 0)
1133 return -EINVAL;
1134
1135 num = ep->epnum - 1;
1136
1137 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1138
1139 /*-------------------------------------------------------------*/
1140 /* State confirmation of FIFO */
1141 if (req->req.actual == 0) {
1142 if ((status & EPN_IN_EMPTY) == 0)
1143 return 1; /* Not Empty */
1144
1145 } else {
1146 if ((status & EPN_IN_FULL) != 0)
1147 return 1; /* Not Empty */
1148 }
1149
1150 /*-------------------------------------------------------------*/
1151 /* Start transfer */
1152 i_buf_size = req->req.length - req->req.actual;
1153 if (i_buf_size > 0)
1154 result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size);
1155 else if (req->req.length == 0)
1156 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1157
1158 return result;
1159 }
1160
1161 /*-------------------------------------------------------------------------*/
_nbu2ss_start_transfer(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req,bool bflag)1162 static int _nbu2ss_start_transfer(struct nbu2ss_udc *udc,
1163 struct nbu2ss_ep *ep,
1164 struct nbu2ss_req *req,
1165 bool bflag)
1166 {
1167 int nret = -EINVAL;
1168
1169 req->dma_flag = false;
1170 req->div_len = 0;
1171
1172 if (req->req.length == 0) {
1173 req->zero = false;
1174 } else {
1175 if ((req->req.length % ep->ep.maxpacket) == 0)
1176 req->zero = req->req.zero;
1177 else
1178 req->zero = false;
1179 }
1180
1181 if (ep->epnum == 0) {
1182 /* EP0 */
1183 switch (udc->ep0state) {
1184 case EP0_IN_DATA_PHASE:
1185 nret = _nbu2ss_ep0_in_transfer(udc, req);
1186 break;
1187
1188 case EP0_OUT_DATA_PHASE:
1189 nret = _nbu2ss_ep0_out_transfer(udc, req);
1190 break;
1191
1192 case EP0_IN_STATUS_PHASE:
1193 nret = EP0_send_NULL(udc, true);
1194 break;
1195
1196 default:
1197 break;
1198 }
1199
1200 } else {
1201 /* EPN */
1202 if (ep->direct == USB_DIR_OUT) {
1203 /* OUT */
1204 if (!bflag)
1205 nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1206 } else {
1207 /* IN */
1208 nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1209 }
1210 }
1211
1212 return nret;
1213 }
1214
1215 /*-------------------------------------------------------------------------*/
_nbu2ss_restert_transfer(struct nbu2ss_ep * ep)1216 static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1217 {
1218 u32 length;
1219 bool bflag = false;
1220 struct nbu2ss_req *req;
1221
1222 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1223 if (!req)
1224 return;
1225
1226 if (ep->epnum > 0) {
1227 length = _nbu2ss_readl(
1228 &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT);
1229
1230 length &= EPN_LDATA;
1231 if (length < ep->ep.maxpacket)
1232 bflag = true;
1233 }
1234
1235 _nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1236 }
1237
1238 /*-------------------------------------------------------------------------*/
1239 /* Endpoint Toggle Reset */
_nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc * udc,u8 ep_adrs)1240 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs)
1241 {
1242 u8 num;
1243 u32 data;
1244
1245 if ((ep_adrs == 0) || (ep_adrs == 0x80))
1246 return;
1247
1248 num = (ep_adrs & 0x7F) - 1;
1249
1250 if (ep_adrs & USB_DIR_IN)
1251 data = EPN_IPIDCLR;
1252 else
1253 data = EPN_BCLR | EPN_OPIDCLR;
1254
1255 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1256 }
1257
1258 /*-------------------------------------------------------------------------*/
1259 /* Endpoint STALL set */
_nbu2ss_set_endpoint_stall(struct nbu2ss_udc * udc,u8 ep_adrs,bool bstall)1260 static void _nbu2ss_set_endpoint_stall(struct nbu2ss_udc *udc,
1261 u8 ep_adrs, bool bstall)
1262 {
1263 u8 num, epnum;
1264 u32 data;
1265 struct nbu2ss_ep *ep;
1266 struct fc_regs __iomem *preg = udc->p_regs;
1267
1268 if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1269 if (bstall) {
1270 /* Set STALL */
1271 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1272 } else {
1273 /* Clear STALL */
1274 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1275 }
1276 } else {
1277 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1278 num = epnum - 1;
1279 ep = &udc->ep[epnum];
1280
1281 if (bstall) {
1282 /* Set STALL */
1283 ep->halted = true;
1284
1285 if (ep_adrs & USB_DIR_IN)
1286 data = EPN_BCLR | EPN_ISTL;
1287 else
1288 data = EPN_OSTL_EN | EPN_OSTL;
1289
1290 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1291 } else {
1292 /* Clear STALL */
1293 ep->stalled = false;
1294 if (ep_adrs & USB_DIR_IN) {
1295 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1296 , EPN_ISTL);
1297 } else {
1298 data =
1299 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1300
1301 data &= ~EPN_OSTL;
1302 data |= EPN_OSTL_EN;
1303
1304 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1305 , data);
1306 }
1307
1308 ep->stalled = false;
1309 if (ep->halted) {
1310 ep->halted = false;
1311 _nbu2ss_restert_transfer(ep);
1312 }
1313 }
1314 }
1315 }
1316
1317 /*-------------------------------------------------------------------------*/
_nbu2ss_set_test_mode(struct nbu2ss_udc * udc,u32 mode)1318 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1319 {
1320 u32 data;
1321
1322 if (mode > MAX_TEST_MODE_NUM)
1323 return;
1324
1325 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
1326
1327 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1328 data &= ~TEST_FORCE_ENABLE;
1329 data |= mode << TEST_MODE_SHIFT;
1330
1331 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1332 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1333 }
1334
1335 /*-------------------------------------------------------------------------*/
_nbu2ss_set_feature_device(struct nbu2ss_udc * udc,u16 selector,u16 wIndex)1336 static int _nbu2ss_set_feature_device(struct nbu2ss_udc *udc,
1337 u16 selector, u16 wIndex)
1338 {
1339 int result = -EOPNOTSUPP;
1340
1341 switch (selector) {
1342 case USB_DEVICE_REMOTE_WAKEUP:
1343 if (wIndex == 0x0000) {
1344 udc->remote_wakeup = U2F_ENABLE;
1345 result = 0;
1346 }
1347 break;
1348
1349 case USB_DEVICE_TEST_MODE:
1350 wIndex >>= 8;
1351 if (wIndex <= MAX_TEST_MODE_NUM)
1352 result = 0;
1353 break;
1354
1355 default:
1356 break;
1357 }
1358
1359 return result;
1360 }
1361
1362 /*-------------------------------------------------------------------------*/
_nbu2ss_get_ep_stall(struct nbu2ss_udc * udc,u8 ep_adrs)1363 static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1364 {
1365 u8 epnum;
1366 u32 data = 0, bit_data;
1367 struct fc_regs __iomem *preg = udc->p_regs;
1368
1369 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1370 if (epnum == 0) {
1371 data = _nbu2ss_readl(&preg->EP0_CONTROL);
1372 bit_data = EP0_STL;
1373
1374 } else {
1375 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL);
1376 if ((data & EPN_EN) == 0)
1377 return -1;
1378
1379 if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1380 bit_data = EPN_ISTL;
1381 else
1382 bit_data = EPN_OSTL;
1383 }
1384
1385 if ((data & bit_data) == 0)
1386 return 0;
1387 return 1;
1388 }
1389
1390 /*-------------------------------------------------------------------------*/
_nbu2ss_req_feature(struct nbu2ss_udc * udc,bool bset)1391 static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1392 {
1393 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1394 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1395 u16 selector = le16_to_cpu(udc->ctrl.wValue);
1396 u16 wIndex = le16_to_cpu(udc->ctrl.wIndex);
1397 u8 ep_adrs;
1398 int result = -EOPNOTSUPP;
1399
1400 if ((udc->ctrl.wLength != 0x0000) ||
1401 (direction != USB_DIR_OUT)) {
1402 return -EINVAL;
1403 }
1404
1405 switch (recipient) {
1406 case USB_RECIP_DEVICE:
1407 if (bset)
1408 result =
1409 _nbu2ss_set_feature_device(udc, selector, wIndex);
1410 break;
1411
1412 case USB_RECIP_ENDPOINT:
1413 if (0x0000 == (wIndex & 0xFF70)) {
1414 if (selector == USB_ENDPOINT_HALT) {
1415 ep_adrs = wIndex & 0xFF;
1416 if (!bset) {
1417 _nbu2ss_endpoint_toggle_reset(udc,
1418 ep_adrs);
1419 }
1420
1421 _nbu2ss_set_endpoint_stall(udc, ep_adrs, bset);
1422
1423 result = 0;
1424 }
1425 }
1426 break;
1427
1428 default:
1429 break;
1430 }
1431
1432 if (result >= 0)
1433 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1434
1435 return result;
1436 }
1437
1438 /*-------------------------------------------------------------------------*/
_nbu2ss_get_speed(struct nbu2ss_udc * udc)1439 static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1440 {
1441 u32 data;
1442 enum usb_device_speed speed = USB_SPEED_FULL;
1443
1444 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1445 if (data & HIGH_SPEED)
1446 speed = USB_SPEED_HIGH;
1447
1448 return speed;
1449 }
1450
1451 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_set_stall(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)1452 static void _nbu2ss_epn_set_stall(struct nbu2ss_udc *udc,
1453 struct nbu2ss_ep *ep)
1454 {
1455 u8 ep_adrs;
1456 u32 regdata;
1457 int limit_cnt = 0;
1458
1459 struct fc_regs __iomem *preg = udc->p_regs;
1460
1461 if (ep->direct == USB_DIR_IN) {
1462 for (limit_cnt = 0
1463 ; limit_cnt < IN_DATA_EMPTY_COUNT
1464 ; limit_cnt++) {
1465 regdata = _nbu2ss_readl(
1466 &preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1467
1468 if ((regdata & EPN_IN_DATA) == 0)
1469 break;
1470
1471 mdelay(1);
1472 }
1473 }
1474
1475 ep_adrs = ep->epnum | ep->direct;
1476 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1477 }
1478
1479 /*-------------------------------------------------------------------------*/
std_req_get_status(struct nbu2ss_udc * udc)1480 static int std_req_get_status(struct nbu2ss_udc *udc)
1481 {
1482 u32 length;
1483 u16 status_data = 0;
1484 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1485 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1486 u8 ep_adrs;
1487 int result = -EINVAL;
1488
1489 if ((udc->ctrl.wValue != 0x0000) || (direction != USB_DIR_IN))
1490 return result;
1491
1492 length =
1493 min_t(u16, le16_to_cpu(udc->ctrl.wLength), sizeof(status_data));
1494 switch (recipient) {
1495 case USB_RECIP_DEVICE:
1496 if (udc->ctrl.wIndex == 0x0000) {
1497 if (udc->gadget.is_selfpowered)
1498 status_data |= BIT(USB_DEVICE_SELF_POWERED);
1499
1500 if (udc->remote_wakeup)
1501 status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP);
1502
1503 result = 0;
1504 }
1505 break;
1506
1507 case USB_RECIP_ENDPOINT:
1508 if (0x0000 == (le16_to_cpu(udc->ctrl.wIndex) & 0xFF70)) {
1509 ep_adrs = (u8)(le16_to_cpu(udc->ctrl.wIndex) & 0xFF);
1510 result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1511
1512 if (result > 0)
1513 status_data |= BIT(USB_ENDPOINT_HALT);
1514 }
1515 break;
1516
1517 default:
1518 break;
1519 }
1520
1521 if (result >= 0) {
1522 memcpy(udc->ep0_buf, &status_data, length);
1523 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
1524 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
1525
1526 } else {
1527 dev_err(udc->dev, " Error GET_STATUS\n");
1528 }
1529
1530 return result;
1531 }
1532
1533 /*-------------------------------------------------------------------------*/
std_req_clear_feature(struct nbu2ss_udc * udc)1534 static int std_req_clear_feature(struct nbu2ss_udc *udc)
1535 {
1536 return _nbu2ss_req_feature(udc, false);
1537 }
1538
1539 /*-------------------------------------------------------------------------*/
std_req_set_feature(struct nbu2ss_udc * udc)1540 static int std_req_set_feature(struct nbu2ss_udc *udc)
1541 {
1542 return _nbu2ss_req_feature(udc, true);
1543 }
1544
1545 /*-------------------------------------------------------------------------*/
std_req_set_address(struct nbu2ss_udc * udc)1546 static int std_req_set_address(struct nbu2ss_udc *udc)
1547 {
1548 int result = 0;
1549 u32 wValue = le16_to_cpu(udc->ctrl.wValue);
1550
1551 if ((udc->ctrl.bRequestType != 0x00) ||
1552 (udc->ctrl.wIndex != 0x0000) ||
1553 (udc->ctrl.wLength != 0x0000)) {
1554 return -EINVAL;
1555 }
1556
1557 if (wValue != (wValue & 0x007F))
1558 return -EINVAL;
1559
1560 wValue <<= USB_ADRS_SHIFT;
1561
1562 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1563 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1564
1565 return result;
1566 }
1567
1568 /*-------------------------------------------------------------------------*/
std_req_set_configuration(struct nbu2ss_udc * udc)1569 static int std_req_set_configuration(struct nbu2ss_udc *udc)
1570 {
1571 u32 config_value = (u32)(le16_to_cpu(udc->ctrl.wValue) & 0x00ff);
1572
1573 if ((udc->ctrl.wIndex != 0x0000) ||
1574 (udc->ctrl.wLength != 0x0000) ||
1575 (udc->ctrl.bRequestType != 0x00)) {
1576 return -EINVAL;
1577 }
1578
1579 udc->curr_config = config_value;
1580
1581 if (config_value > 0) {
1582 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1583 udc->devstate = USB_STATE_CONFIGURED;
1584
1585 } else {
1586 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1587 udc->devstate = USB_STATE_ADDRESS;
1588 }
1589
1590 return 0;
1591 }
1592
1593 /*-------------------------------------------------------------------------*/
_nbu2ss_read_request_data(struct nbu2ss_udc * udc,u32 * pdata)1594 static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1595 {
1596 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1597 pdata++;
1598 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1599 }
1600
1601 /*-------------------------------------------------------------------------*/
_nbu2ss_decode_request(struct nbu2ss_udc * udc)1602 static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1603 {
1604 bool bcall_back = true;
1605 int nret = -EINVAL;
1606 struct usb_ctrlrequest *p_ctrl;
1607
1608 p_ctrl = &udc->ctrl;
1609 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1610
1611 /* ep0 state control */
1612 if (p_ctrl->wLength == 0) {
1613 udc->ep0state = EP0_IN_STATUS_PHASE;
1614
1615 } else {
1616 if (p_ctrl->bRequestType & USB_DIR_IN)
1617 udc->ep0state = EP0_IN_DATA_PHASE;
1618 else
1619 udc->ep0state = EP0_OUT_DATA_PHASE;
1620 }
1621
1622 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1623 switch (p_ctrl->bRequest) {
1624 case USB_REQ_GET_STATUS:
1625 nret = std_req_get_status(udc);
1626 bcall_back = false;
1627 break;
1628
1629 case USB_REQ_CLEAR_FEATURE:
1630 nret = std_req_clear_feature(udc);
1631 bcall_back = false;
1632 break;
1633
1634 case USB_REQ_SET_FEATURE:
1635 nret = std_req_set_feature(udc);
1636 bcall_back = false;
1637 break;
1638
1639 case USB_REQ_SET_ADDRESS:
1640 nret = std_req_set_address(udc);
1641 bcall_back = false;
1642 break;
1643
1644 case USB_REQ_SET_CONFIGURATION:
1645 nret = std_req_set_configuration(udc);
1646 break;
1647
1648 default:
1649 break;
1650 }
1651 }
1652
1653 if (!bcall_back) {
1654 if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1655 if (nret >= 0) {
1656 /*--------------------------------------*/
1657 /* Status Stage */
1658 nret = EP0_send_NULL(udc, true);
1659 }
1660 }
1661
1662 } else {
1663 spin_unlock(&udc->lock);
1664 nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1665 spin_lock(&udc->lock);
1666 }
1667
1668 if (nret < 0)
1669 udc->ep0state = EP0_IDLE;
1670
1671 return nret;
1672 }
1673
1674 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_in_data_stage(struct nbu2ss_udc * udc)1675 static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1676 {
1677 int nret;
1678 struct nbu2ss_req *req;
1679 struct nbu2ss_ep *ep = &udc->ep[0];
1680
1681 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1682 if (!req)
1683 req = &udc->ep0_req;
1684
1685 req->req.actual += req->div_len;
1686 req->div_len = 0;
1687
1688 nret = _nbu2ss_ep0_in_transfer(udc, req);
1689 if (nret == 0) {
1690 udc->ep0state = EP0_OUT_STATUS_PAHSE;
1691 EP0_receive_NULL(udc, true);
1692 }
1693
1694 return 0;
1695 }
1696
1697 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_out_data_stage(struct nbu2ss_udc * udc)1698 static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1699 {
1700 int nret;
1701 struct nbu2ss_req *req;
1702 struct nbu2ss_ep *ep = &udc->ep[0];
1703
1704 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1705 if (!req)
1706 req = &udc->ep0_req;
1707
1708 nret = _nbu2ss_ep0_out_transfer(udc, req);
1709 if (nret == 0) {
1710 udc->ep0state = EP0_IN_STATUS_PHASE;
1711 EP0_send_NULL(udc, true);
1712
1713 } else if (nret < 0) {
1714 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1715 req->req.status = nret;
1716 }
1717
1718 return 0;
1719 }
1720
1721 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_status_stage(struct nbu2ss_udc * udc)1722 static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1723 {
1724 struct nbu2ss_req *req;
1725 struct nbu2ss_ep *ep = &udc->ep[0];
1726
1727 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1728 if (!req) {
1729 req = &udc->ep0_req;
1730 if (req->req.complete)
1731 req->req.complete(&ep->ep, &req->req);
1732
1733 } else {
1734 if (req->req.complete)
1735 _nbu2ss_ep_done(ep, req, 0);
1736 }
1737
1738 udc->ep0state = EP0_IDLE;
1739
1740 return 0;
1741 }
1742
1743 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_int(struct nbu2ss_udc * udc)1744 static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1745 {
1746 int i;
1747 u32 status;
1748 u32 intr;
1749 int nret = -1;
1750
1751 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1752 intr = status & EP0_STATUS_RW_BIT;
1753 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~intr);
1754
1755 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1756 | STG_END_INT | EP0_OUT_NULL_INT);
1757
1758 if (status == 0) {
1759 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1760 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
1761 return;
1762 }
1763
1764 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1765 udc->gadget.speed = _nbu2ss_get_speed(udc);
1766
1767 for (i = 0; i < EP0_END_XFER; i++) {
1768 switch (udc->ep0state) {
1769 case EP0_IDLE:
1770 if (status & SETUP_INT) {
1771 status = 0;
1772 nret = _nbu2ss_decode_request(udc);
1773 }
1774 break;
1775
1776 case EP0_IN_DATA_PHASE:
1777 if (status & EP0_IN_INT) {
1778 status &= ~EP0_IN_INT;
1779 nret = _nbu2ss_ep0_in_data_stage(udc);
1780 }
1781 break;
1782
1783 case EP0_OUT_DATA_PHASE:
1784 if (status & EP0_OUT_INT) {
1785 status &= ~EP0_OUT_INT;
1786 nret = _nbu2ss_ep0_out_data_stage(udc);
1787 }
1788 break;
1789
1790 case EP0_IN_STATUS_PHASE:
1791 if ((status & STG_END_INT) || (status & SETUP_INT)) {
1792 status &= ~(STG_END_INT | EP0_IN_INT);
1793 nret = _nbu2ss_ep0_status_stage(udc);
1794 }
1795 break;
1796
1797 case EP0_OUT_STATUS_PAHSE:
1798 if ((status & STG_END_INT) || (status & SETUP_INT) ||
1799 (status & EP0_OUT_NULL_INT)) {
1800 status &= ~(STG_END_INT
1801 | EP0_OUT_INT
1802 | EP0_OUT_NULL_INT);
1803
1804 nret = _nbu2ss_ep0_status_stage(udc);
1805 }
1806
1807 break;
1808
1809 default:
1810 status = 0;
1811 break;
1812 }
1813
1814 if (status == 0)
1815 break;
1816 }
1817
1818 if (nret < 0) {
1819 /* Send Stall */
1820 _nbu2ss_set_endpoint_stall(udc, 0, true);
1821 }
1822 }
1823
1824 /*-------------------------------------------------------------------------*/
_nbu2ss_ep_done(struct nbu2ss_ep * ep,struct nbu2ss_req * req,int status)1825 static void _nbu2ss_ep_done(struct nbu2ss_ep *ep,
1826 struct nbu2ss_req *req,
1827 int status)
1828 {
1829 struct nbu2ss_udc *udc = ep->udc;
1830
1831 list_del_init(&req->queue);
1832
1833 if (status == -ECONNRESET)
1834 _nbu2ss_fifo_flush(udc, ep);
1835
1836 if (likely(req->req.status == -EINPROGRESS))
1837 req->req.status = status;
1838
1839 if (ep->stalled) {
1840 _nbu2ss_epn_set_stall(udc, ep);
1841 } else {
1842 if (!list_empty(&ep->queue))
1843 _nbu2ss_restert_transfer(ep);
1844 }
1845
1846 #ifdef USE_DMA
1847 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
1848 (req->req.dma != 0))
1849 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1850 #endif
1851
1852 spin_unlock(&udc->lock);
1853 req->req.complete(&ep->ep, &req->req);
1854 spin_lock(&udc->lock);
1855 }
1856
1857 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1858 static inline void _nbu2ss_epn_in_int(struct nbu2ss_udc *udc,
1859 struct nbu2ss_ep *ep,
1860 struct nbu2ss_req *req)
1861 {
1862 int result = 0;
1863 u32 status;
1864
1865 struct fc_regs __iomem *preg = udc->p_regs;
1866
1867 if (req->dma_flag)
1868 return; /* DMA is forwarded */
1869
1870 req->req.actual += req->div_len;
1871 req->div_len = 0;
1872
1873 if (req->req.actual != req->req.length) {
1874 /*---------------------------------------------------------*/
1875 /* remainder of data */
1876 result = _nbu2ss_epn_in_transfer(udc, ep, req);
1877
1878 } else {
1879 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
1880 status =
1881 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1882
1883 if ((status & EPN_IN_FULL) == 0) {
1884 /*-----------------------------------------*/
1885 /* 0 Length Packet */
1886 req->zero = false;
1887 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1888 }
1889 return;
1890 }
1891 }
1892
1893 if (result <= 0) {
1894 /*---------------------------------------------------------*/
1895 /* Complete */
1896 _nbu2ss_ep_done(ep, req, result);
1897 }
1898 }
1899
1900 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1901 static inline void _nbu2ss_epn_out_int(struct nbu2ss_udc *udc,
1902 struct nbu2ss_ep *ep,
1903 struct nbu2ss_req *req)
1904 {
1905 int result;
1906
1907 result = _nbu2ss_epn_out_transfer(udc, ep, req);
1908 if (result <= 0)
1909 _nbu2ss_ep_done(ep, req, result);
1910 }
1911
1912 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_in_dma_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1913 static inline void _nbu2ss_epn_in_dma_int(struct nbu2ss_udc *udc,
1914 struct nbu2ss_ep *ep,
1915 struct nbu2ss_req *req)
1916 {
1917 u32 mpkt;
1918 u32 size;
1919 struct usb_request *preq;
1920
1921 preq = &req->req;
1922
1923 if (!req->dma_flag)
1924 return;
1925
1926 preq->actual += req->div_len;
1927 req->div_len = 0;
1928 req->dma_flag = false;
1929
1930 #ifdef USE_DMA
1931 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
1932 #endif
1933
1934 if (preq->actual != preq->length) {
1935 _nbu2ss_epn_in_transfer(udc, ep, req);
1936 } else {
1937 mpkt = ep->ep.maxpacket;
1938 size = preq->actual % mpkt;
1939 if (size > 0) {
1940 if (((preq->actual & 0x03) == 0) && (size < mpkt))
1941 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
1942 } else {
1943 _nbu2ss_epn_in_int(udc, ep, req);
1944 }
1945 }
1946 }
1947
1948 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_out_dma_int(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,struct nbu2ss_req * req)1949 static inline void _nbu2ss_epn_out_dma_int(struct nbu2ss_udc *udc,
1950 struct nbu2ss_ep *ep,
1951 struct nbu2ss_req *req)
1952 {
1953 int i;
1954 u32 num;
1955 u32 dmacnt, ep_dmacnt;
1956 u32 mpkt;
1957 struct fc_regs __iomem *preg = udc->p_regs;
1958
1959 num = ep->epnum - 1;
1960
1961 if (req->req.actual == req->req.length) {
1962 if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
1963 req->div_len = 0;
1964 req->dma_flag = false;
1965 _nbu2ss_ep_done(ep, req, 0);
1966 return;
1967 }
1968 }
1969
1970 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
1971 & EPN_DMACNT;
1972 ep_dmacnt >>= 16;
1973
1974 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
1975 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
1976 & DCR1_EPN_DMACNT;
1977 dmacnt >>= 16;
1978 if (ep_dmacnt == dmacnt)
1979 break;
1980 }
1981
1982 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN);
1983
1984 if (dmacnt != 0) {
1985 mpkt = ep->ep.maxpacket;
1986 if ((req->div_len % mpkt) == 0)
1987 req->div_len -= mpkt * dmacnt;
1988 }
1989
1990 if ((req->req.actual % ep->ep.maxpacket) > 0) {
1991 if (req->req.actual == req->div_len) {
1992 req->div_len = 0;
1993 req->dma_flag = false;
1994 _nbu2ss_ep_done(ep, req, 0);
1995 return;
1996 }
1997 }
1998
1999 req->req.actual += req->div_len;
2000 req->div_len = 0;
2001 req->dma_flag = false;
2002
2003 _nbu2ss_epn_out_int(udc, ep, req);
2004 }
2005
2006 /*-------------------------------------------------------------------------*/
_nbu2ss_epn_int(struct nbu2ss_udc * udc,u32 epnum)2007 static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2008 {
2009 u32 num;
2010 u32 status;
2011
2012 struct nbu2ss_req *req;
2013 struct nbu2ss_ep *ep = &udc->ep[epnum];
2014
2015 num = epnum - 1;
2016
2017 /* Interrupt Status */
2018 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2019
2020 /* Interrupt Clear */
2021 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~status);
2022
2023 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
2024 if (!req) {
2025 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */
2026 return;
2027 }
2028
2029 if (status & EPN_OUT_END_INT) {
2030 status &= ~EPN_OUT_INT;
2031 _nbu2ss_epn_out_dma_int(udc, ep, req);
2032 }
2033
2034 if (status & EPN_OUT_INT)
2035 _nbu2ss_epn_out_int(udc, ep, req);
2036
2037 if (status & EPN_IN_END_INT) {
2038 status &= ~EPN_IN_INT;
2039 _nbu2ss_epn_in_dma_int(udc, ep, req);
2040 }
2041
2042 if (status & EPN_IN_INT)
2043 _nbu2ss_epn_in_int(udc, ep, req);
2044 }
2045
2046 /*-------------------------------------------------------------------------*/
_nbu2ss_ep_int(struct nbu2ss_udc * udc,u32 epnum)2047 static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2048 {
2049 if (epnum == 0)
2050 _nbu2ss_ep0_int(udc);
2051 else
2052 _nbu2ss_epn_int(udc, epnum);
2053 }
2054
2055 /*-------------------------------------------------------------------------*/
_nbu2ss_ep0_enable(struct nbu2ss_udc * udc)2056 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2057 {
2058 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2059 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
2060 }
2061
2062 /*-------------------------------------------------------------------------*/
_nbu2ss_nuke(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep,int status)2063 static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2064 struct nbu2ss_ep *ep,
2065 int status)
2066 {
2067 struct nbu2ss_req *req, *n;
2068
2069 /* Endpoint Disable */
2070 _nbu2ss_epn_exit(udc, ep);
2071
2072 /* DMA Disable */
2073 _nbu2ss_ep_dma_exit(udc, ep);
2074
2075 if (list_empty(&ep->queue))
2076 return 0;
2077
2078 /* called with irqs blocked */
2079 list_for_each_entry_safe(req, n, &ep->queue, queue) {
2080 _nbu2ss_ep_done(ep, req, status);
2081 }
2082
2083 return 0;
2084 }
2085
2086 /*-------------------------------------------------------------------------*/
_nbu2ss_quiesce(struct nbu2ss_udc * udc)2087 static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2088 {
2089 struct nbu2ss_ep *ep;
2090
2091 udc->gadget.speed = USB_SPEED_UNKNOWN;
2092
2093 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2094
2095 /* Endpoint n */
2096 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2097 _nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2098 }
2099 }
2100
2101 /*-------------------------------------------------------------------------*/
_nbu2ss_pullup(struct nbu2ss_udc * udc,int is_on)2102 static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2103 {
2104 u32 reg_dt;
2105
2106 if (udc->vbus_active == 0)
2107 return -ESHUTDOWN;
2108
2109 if (is_on) {
2110 /* D+ Pullup */
2111 if (udc->driver) {
2112 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2113 | PUE2) & ~(u32)CONNECTB;
2114
2115 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2116 }
2117
2118 } else {
2119 /* D+ Pulldown */
2120 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2121 & ~(u32)PUE2;
2122
2123 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2124 udc->gadget.speed = USB_SPEED_UNKNOWN;
2125 }
2126
2127 return 0;
2128 }
2129
2130 /*-------------------------------------------------------------------------*/
_nbu2ss_fifo_flush(struct nbu2ss_udc * udc,struct nbu2ss_ep * ep)2131 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2132 {
2133 struct fc_regs __iomem *p = udc->p_regs;
2134
2135 if (udc->vbus_active == 0)
2136 return;
2137
2138 if (ep->epnum == 0) {
2139 /* EP0 */
2140 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2141
2142 } else {
2143 /* EPN */
2144 _nbu2ss_ep_dma_abort(udc, ep);
2145 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR);
2146 }
2147 }
2148
2149 /*-------------------------------------------------------------------------*/
_nbu2ss_enable_controller(struct nbu2ss_udc * udc)2150 static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2151 {
2152 int waitcnt = 0;
2153
2154 if (udc->udc_enabled)
2155 return 0;
2156
2157 /* Reset */
2158 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2159 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */
2160
2161 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2162 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */
2163
2164 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2165
2166 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2167
2168 _nbu2ss_writel(&udc->p_regs->AHBMCTR,
2169 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
2170
2171 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2172 waitcnt++;
2173 udelay(1); /* 1us wait */
2174 if (waitcnt == EPC_PLL_LOCK_COUNT) {
2175 dev_err(udc->dev, "*** Reset Cancel failed\n");
2176 return -EINVAL;
2177 }
2178 }
2179
2180 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2181
2182 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2183
2184 /* EP0 */
2185 _nbu2ss_ep0_enable(udc);
2186
2187 /* USB Interrupt Enable */
2188 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2189
2190 udc->udc_enabled = true;
2191
2192 return 0;
2193 }
2194
2195 /*-------------------------------------------------------------------------*/
_nbu2ss_reset_controller(struct nbu2ss_udc * udc)2196 static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2197 {
2198 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2199 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2200 }
2201
2202 /*-------------------------------------------------------------------------*/
_nbu2ss_disable_controller(struct nbu2ss_udc * udc)2203 static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2204 {
2205 if (udc->udc_enabled) {
2206 udc->udc_enabled = false;
2207 _nbu2ss_reset_controller(udc);
2208 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2209 }
2210 }
2211
2212 /*-------------------------------------------------------------------------*/
_nbu2ss_check_vbus(struct nbu2ss_udc * udc)2213 static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2214 {
2215 int nret;
2216 u32 reg_dt;
2217
2218 /* chattering */
2219 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */
2220
2221 /* VBUS ON Check*/
2222 reg_dt = gpiod_get_value(vbus_gpio);
2223 if (reg_dt == 0) {
2224 udc->linux_suspended = 0;
2225
2226 _nbu2ss_reset_controller(udc);
2227 dev_info(udc->dev, " ----- VBUS OFF\n");
2228
2229 if (udc->vbus_active == 1) {
2230 /* VBUS OFF */
2231 udc->vbus_active = 0;
2232 if (udc->usb_suspended) {
2233 udc->usb_suspended = 0;
2234 /* _nbu2ss_reset_controller(udc); */
2235 }
2236 udc->devstate = USB_STATE_NOTATTACHED;
2237
2238 _nbu2ss_quiesce(udc);
2239 if (udc->driver) {
2240 spin_unlock(&udc->lock);
2241 udc->driver->disconnect(&udc->gadget);
2242 spin_lock(&udc->lock);
2243 }
2244
2245 _nbu2ss_disable_controller(udc);
2246 }
2247 } else {
2248 mdelay(5); /* wait (5ms) */
2249 reg_dt = gpiod_get_value(vbus_gpio);
2250 if (reg_dt == 0)
2251 return;
2252
2253 dev_info(udc->dev, " ----- VBUS ON\n");
2254
2255 if (udc->linux_suspended)
2256 return;
2257
2258 if (udc->vbus_active == 0) {
2259 /* VBUS ON */
2260 udc->vbus_active = 1;
2261 udc->devstate = USB_STATE_POWERED;
2262
2263 nret = _nbu2ss_enable_controller(udc);
2264 if (nret < 0) {
2265 _nbu2ss_disable_controller(udc);
2266 udc->vbus_active = 0;
2267 return;
2268 }
2269
2270 _nbu2ss_pullup(udc, 1);
2271
2272 #ifdef UDC_DEBUG_DUMP
2273 _nbu2ss_dump_register(udc);
2274 #endif /* UDC_DEBUG_DUMP */
2275
2276 } else {
2277 if (udc->devstate == USB_STATE_POWERED)
2278 _nbu2ss_pullup(udc, 1);
2279 }
2280 }
2281 }
2282
2283 /*-------------------------------------------------------------------------*/
_nbu2ss_int_bus_reset(struct nbu2ss_udc * udc)2284 static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2285 {
2286 udc->devstate = USB_STATE_DEFAULT;
2287 udc->remote_wakeup = 0;
2288
2289 _nbu2ss_quiesce(udc);
2290
2291 udc->ep0state = EP0_IDLE;
2292 }
2293
2294 /*-------------------------------------------------------------------------*/
_nbu2ss_int_usb_resume(struct nbu2ss_udc * udc)2295 static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2296 {
2297 if (udc->usb_suspended == 1) {
2298 udc->usb_suspended = 0;
2299 if (udc->driver && udc->driver->resume) {
2300 spin_unlock(&udc->lock);
2301 udc->driver->resume(&udc->gadget);
2302 spin_lock(&udc->lock);
2303 }
2304 }
2305 }
2306
2307 /*-------------------------------------------------------------------------*/
_nbu2ss_int_usb_suspend(struct nbu2ss_udc * udc)2308 static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2309 {
2310 u32 reg_dt;
2311
2312 if (udc->usb_suspended == 0) {
2313 reg_dt = gpiod_get_value(vbus_gpio);
2314
2315 if (reg_dt == 0)
2316 return;
2317
2318 udc->usb_suspended = 1;
2319 if (udc->driver && udc->driver->suspend) {
2320 spin_unlock(&udc->lock);
2321 udc->driver->suspend(&udc->gadget);
2322 spin_lock(&udc->lock);
2323 }
2324
2325 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2326 }
2327 }
2328
2329 /*-------------------------------------------------------------------------*/
2330 /* VBUS (GPIO153) Interrupt */
_nbu2ss_vbus_irq(int irq,void * _udc)2331 static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2332 {
2333 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2334
2335 spin_lock(&udc->lock);
2336 _nbu2ss_check_vbus(udc);
2337 spin_unlock(&udc->lock);
2338
2339 return IRQ_HANDLED;
2340 }
2341
2342 /*-------------------------------------------------------------------------*/
2343 /* Interrupt (udc) */
_nbu2ss_udc_irq(int irq,void * _udc)2344 static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2345 {
2346 u8 suspend_flag = 0;
2347 u32 status;
2348 u32 epnum, int_bit;
2349
2350 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2351 struct fc_regs __iomem *preg = udc->p_regs;
2352
2353 if (gpiod_get_value(vbus_gpio) == 0) {
2354 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2355 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2356 return IRQ_HANDLED;
2357 }
2358
2359 spin_lock(&udc->lock);
2360
2361 for (;;) {
2362 if (gpiod_get_value(vbus_gpio) == 0) {
2363 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2364 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2365 status = 0;
2366 } else {
2367 status = _nbu2ss_readl(&preg->USB_INT_STA);
2368 }
2369
2370 if (status == 0)
2371 break;
2372
2373 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2374
2375 if (status & USB_RST_INT) {
2376 /* USB Reset */
2377 _nbu2ss_int_bus_reset(udc);
2378 }
2379
2380 if (status & RSUM_INT) {
2381 /* Resume */
2382 _nbu2ss_int_usb_resume(udc);
2383 }
2384
2385 if (status & SPND_INT) {
2386 /* Suspend */
2387 suspend_flag = 1;
2388 }
2389
2390 if (status & EPN_INT) {
2391 /* EP INT */
2392 int_bit = status >> 8;
2393
2394 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2395 if (0x01 & int_bit)
2396 _nbu2ss_ep_int(udc, epnum);
2397
2398 int_bit >>= 1;
2399
2400 if (int_bit == 0)
2401 break;
2402 }
2403 }
2404 }
2405
2406 if (suspend_flag)
2407 _nbu2ss_int_usb_suspend(udc);
2408
2409 spin_unlock(&udc->lock);
2410
2411 return IRQ_HANDLED;
2412 }
2413
2414 /*-------------------------------------------------------------------------*/
2415 /* usb_ep_ops */
nbu2ss_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)2416 static int nbu2ss_ep_enable(struct usb_ep *_ep,
2417 const struct usb_endpoint_descriptor *desc)
2418 {
2419 u8 ep_type;
2420 unsigned long flags;
2421
2422 struct nbu2ss_ep *ep;
2423 struct nbu2ss_udc *udc;
2424
2425 if (!_ep || !desc) {
2426 pr_err(" *** %s, bad param\n", __func__);
2427 return -EINVAL;
2428 }
2429
2430 ep = container_of(_ep, struct nbu2ss_ep, ep);
2431 if (!ep->udc) {
2432 pr_err(" *** %s, ep == NULL !!\n", __func__);
2433 return -EINVAL;
2434 }
2435
2436 ep_type = usb_endpoint_type(desc);
2437 if ((ep_type == USB_ENDPOINT_XFER_CONTROL) ||
2438 (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2439 pr_err(" *** %s, bat bmAttributes\n", __func__);
2440 return -EINVAL;
2441 }
2442
2443 udc = ep->udc;
2444 if (udc->vbus_active == 0)
2445 return -ESHUTDOWN;
2446
2447 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2448 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
2449 return -ESHUTDOWN;
2450 }
2451
2452 spin_lock_irqsave(&udc->lock, flags);
2453
2454 ep->desc = desc;
2455 ep->epnum = usb_endpoint_num(desc);
2456 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2457 ep->ep_type = ep_type;
2458 ep->wedged = 0;
2459 ep->halted = false;
2460 ep->stalled = false;
2461
2462 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2463
2464 /* DMA setting */
2465 _nbu2ss_ep_dma_init(udc, ep);
2466
2467 /* Endpoint setting */
2468 _nbu2ss_ep_init(udc, ep);
2469
2470 spin_unlock_irqrestore(&udc->lock, flags);
2471
2472 return 0;
2473 }
2474
2475 /*-------------------------------------------------------------------------*/
nbu2ss_ep_disable(struct usb_ep * _ep)2476 static int nbu2ss_ep_disable(struct usb_ep *_ep)
2477 {
2478 struct nbu2ss_ep *ep;
2479 struct nbu2ss_udc *udc;
2480 unsigned long flags;
2481
2482 if (!_ep) {
2483 pr_err(" *** %s, bad param\n", __func__);
2484 return -EINVAL;
2485 }
2486
2487 ep = container_of(_ep, struct nbu2ss_ep, ep);
2488 if (!ep->udc) {
2489 pr_err("udc: *** %s, ep == NULL !!\n", __func__);
2490 return -EINVAL;
2491 }
2492
2493 udc = ep->udc;
2494 if (udc->vbus_active == 0)
2495 return -ESHUTDOWN;
2496
2497 spin_lock_irqsave(&udc->lock, flags);
2498 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */
2499 spin_unlock_irqrestore(&udc->lock, flags);
2500
2501 return 0;
2502 }
2503
2504 /*-------------------------------------------------------------------------*/
nbu2ss_ep_alloc_request(struct usb_ep * ep,gfp_t gfp_flags)2505 static struct usb_request *nbu2ss_ep_alloc_request(struct usb_ep *ep,
2506 gfp_t gfp_flags)
2507 {
2508 struct nbu2ss_req *req;
2509
2510 req = kzalloc(sizeof(*req), gfp_flags);
2511 if (!req)
2512 return NULL;
2513
2514 #ifdef USE_DMA
2515 req->req.dma = DMA_ADDR_INVALID;
2516 #endif
2517 INIT_LIST_HEAD(&req->queue);
2518
2519 return &req->req;
2520 }
2521
2522 /*-------------------------------------------------------------------------*/
nbu2ss_ep_free_request(struct usb_ep * _ep,struct usb_request * _req)2523 static void nbu2ss_ep_free_request(struct usb_ep *_ep,
2524 struct usb_request *_req)
2525 {
2526 struct nbu2ss_req *req;
2527
2528 if (_req) {
2529 req = container_of(_req, struct nbu2ss_req, req);
2530
2531 kfree(req);
2532 }
2533 }
2534
2535 /*-------------------------------------------------------------------------*/
nbu2ss_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)2536 static int nbu2ss_ep_queue(struct usb_ep *_ep,
2537 struct usb_request *_req, gfp_t gfp_flags)
2538 {
2539 struct nbu2ss_req *req;
2540 struct nbu2ss_ep *ep;
2541 struct nbu2ss_udc *udc;
2542 unsigned long flags;
2543 bool bflag;
2544 int result = -EINVAL;
2545
2546 /* catch various bogus parameters */
2547 if (!_ep || !_req) {
2548 if (!_ep)
2549 pr_err("udc: %s --- _ep == NULL\n", __func__);
2550
2551 if (!_req)
2552 pr_err("udc: %s --- _req == NULL\n", __func__);
2553
2554 return -EINVAL;
2555 }
2556
2557 req = container_of(_req, struct nbu2ss_req, req);
2558 if (unlikely(!_req->complete ||
2559 !_req->buf ||
2560 !list_empty(&req->queue))) {
2561 if (!_req->complete)
2562 pr_err("udc: %s --- !_req->complete\n", __func__);
2563
2564 if (!_req->buf)
2565 pr_err("udc:%s --- !_req->buf\n", __func__);
2566
2567 if (!list_empty(&req->queue))
2568 pr_err("%s --- !list_empty(&req->queue)\n", __func__);
2569
2570 return -EINVAL;
2571 }
2572
2573 ep = container_of(_ep, struct nbu2ss_ep, ep);
2574 udc = ep->udc;
2575
2576 if (udc->vbus_active == 0) {
2577 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
2578 return -ESHUTDOWN;
2579 }
2580
2581 if (unlikely(!udc->driver)) {
2582 dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
2583 udc->driver);
2584 return -ESHUTDOWN;
2585 }
2586
2587 spin_lock_irqsave(&udc->lock, flags);
2588
2589 #ifdef USE_DMA
2590 if ((uintptr_t)req->req.buf & 0x3)
2591 req->unaligned = true;
2592 else
2593 req->unaligned = false;
2594
2595 if (req->unaligned) {
2596 if (!ep->virt_buf) {
2597 ep->virt_buf = dma_alloc_coherent(udc->dev, PAGE_SIZE,
2598 &ep->phys_buf,
2599 GFP_ATOMIC | GFP_DMA);
2600 if (!ep->virt_buf) {
2601 spin_unlock_irqrestore(&udc->lock, flags);
2602 return -ENOMEM;
2603 }
2604 }
2605 if (ep->epnum > 0) {
2606 if (ep->direct == USB_DIR_IN)
2607 memcpy(ep->virt_buf, req->req.buf,
2608 req->req.length);
2609 }
2610 }
2611
2612 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
2613 (req->req.dma != 0))
2614 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2615 #endif
2616
2617 _req->status = -EINPROGRESS;
2618 _req->actual = 0;
2619
2620 bflag = list_empty(&ep->queue);
2621 list_add_tail(&req->queue, &ep->queue);
2622
2623 if (bflag && !ep->stalled) {
2624 result = _nbu2ss_start_transfer(udc, ep, req, false);
2625 if (result < 0) {
2626 dev_err(udc->dev, " *** %s, result = %d\n", __func__,
2627 result);
2628 list_del(&req->queue);
2629 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2630 #ifdef USE_DMA
2631 if (req->req.length < 4 &&
2632 req->req.length == req->req.actual)
2633 #else
2634 if (req->req.length == req->req.actual)
2635 #endif
2636 _nbu2ss_ep_done(ep, req, result);
2637 }
2638 }
2639
2640 spin_unlock_irqrestore(&udc->lock, flags);
2641
2642 return 0;
2643 }
2644
2645 /*-------------------------------------------------------------------------*/
nbu2ss_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)2646 static int nbu2ss_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
2647 {
2648 struct nbu2ss_req *req;
2649 struct nbu2ss_ep *ep;
2650 struct nbu2ss_udc *udc;
2651 unsigned long flags;
2652
2653 /* catch various bogus parameters */
2654 if (!_ep || !_req) {
2655 /* pr_err("%s, bad param(1)\n", __func__); */
2656 return -EINVAL;
2657 }
2658
2659 ep = container_of(_ep, struct nbu2ss_ep, ep);
2660
2661 udc = ep->udc;
2662 if (!udc)
2663 return -EINVAL;
2664
2665 spin_lock_irqsave(&udc->lock, flags);
2666
2667 /* make sure it's actually queued on this endpoint */
2668 list_for_each_entry(req, &ep->queue, queue) {
2669 if (&req->req == _req)
2670 break;
2671 }
2672 if (&req->req != _req) {
2673 spin_unlock_irqrestore(&udc->lock, flags);
2674 pr_debug("%s no queue(EINVAL)\n", __func__);
2675 return -EINVAL;
2676 }
2677
2678 _nbu2ss_ep_done(ep, req, -ECONNRESET);
2679
2680 spin_unlock_irqrestore(&udc->lock, flags);
2681
2682 return 0;
2683 }
2684
2685 /*-------------------------------------------------------------------------*/
nbu2ss_ep_set_halt(struct usb_ep * _ep,int value)2686 static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2687 {
2688 u8 ep_adrs;
2689 unsigned long flags;
2690
2691 struct nbu2ss_ep *ep;
2692 struct nbu2ss_udc *udc;
2693
2694 if (!_ep) {
2695 pr_err("%s, bad param\n", __func__);
2696 return -EINVAL;
2697 }
2698
2699 ep = container_of(_ep, struct nbu2ss_ep, ep);
2700
2701 udc = ep->udc;
2702 if (!udc) {
2703 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
2704 return -EINVAL;
2705 }
2706
2707 spin_lock_irqsave(&udc->lock, flags);
2708
2709 ep_adrs = ep->epnum | ep->direct;
2710 if (value == 0) {
2711 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2712 ep->stalled = false;
2713 } else {
2714 if (list_empty(&ep->queue))
2715 _nbu2ss_epn_set_stall(udc, ep);
2716 else
2717 ep->stalled = true;
2718 }
2719
2720 if (value == 0)
2721 ep->wedged = 0;
2722
2723 spin_unlock_irqrestore(&udc->lock, flags);
2724
2725 return 0;
2726 }
2727
nbu2ss_ep_set_wedge(struct usb_ep * _ep)2728 static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2729 {
2730 return nbu2ss_ep_set_halt(_ep, 1);
2731 }
2732
2733 /*-------------------------------------------------------------------------*/
nbu2ss_ep_fifo_status(struct usb_ep * _ep)2734 static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2735 {
2736 u32 data;
2737 struct nbu2ss_ep *ep;
2738 struct nbu2ss_udc *udc;
2739 unsigned long flags;
2740 struct fc_regs __iomem *preg;
2741
2742 if (!_ep) {
2743 pr_err("%s, bad param\n", __func__);
2744 return -EINVAL;
2745 }
2746
2747 ep = container_of(_ep, struct nbu2ss_ep, ep);
2748
2749 udc = ep->udc;
2750 if (!udc) {
2751 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2752 return -EINVAL;
2753 }
2754
2755 preg = udc->p_regs;
2756
2757 data = gpiod_get_value(vbus_gpio);
2758 if (data == 0)
2759 return -EINVAL;
2760
2761 spin_lock_irqsave(&udc->lock, flags);
2762
2763 if (ep->epnum == 0) {
2764 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2765
2766 } else {
2767 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT)
2768 & EPN_LDATA;
2769 }
2770
2771 spin_unlock_irqrestore(&udc->lock, flags);
2772
2773 return 0;
2774 }
2775
2776 /*-------------------------------------------------------------------------*/
nbu2ss_ep_fifo_flush(struct usb_ep * _ep)2777 static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2778 {
2779 u32 data;
2780 struct nbu2ss_ep *ep;
2781 struct nbu2ss_udc *udc;
2782 unsigned long flags;
2783
2784 if (!_ep) {
2785 pr_err("udc: %s, bad param\n", __func__);
2786 return;
2787 }
2788
2789 ep = container_of(_ep, struct nbu2ss_ep, ep);
2790
2791 udc = ep->udc;
2792 if (!udc) {
2793 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2794 return;
2795 }
2796
2797 data = gpiod_get_value(vbus_gpio);
2798 if (data == 0)
2799 return;
2800
2801 spin_lock_irqsave(&udc->lock, flags);
2802 _nbu2ss_fifo_flush(udc, ep);
2803 spin_unlock_irqrestore(&udc->lock, flags);
2804 }
2805
2806 /*-------------------------------------------------------------------------*/
2807 static const struct usb_ep_ops nbu2ss_ep_ops = {
2808 .enable = nbu2ss_ep_enable,
2809 .disable = nbu2ss_ep_disable,
2810
2811 .alloc_request = nbu2ss_ep_alloc_request,
2812 .free_request = nbu2ss_ep_free_request,
2813
2814 .queue = nbu2ss_ep_queue,
2815 .dequeue = nbu2ss_ep_dequeue,
2816
2817 .set_halt = nbu2ss_ep_set_halt,
2818 .set_wedge = nbu2ss_ep_set_wedge,
2819
2820 .fifo_status = nbu2ss_ep_fifo_status,
2821 .fifo_flush = nbu2ss_ep_fifo_flush,
2822 };
2823
2824 /*-------------------------------------------------------------------------*/
2825 /* usb_gadget_ops */
2826
2827 /*-------------------------------------------------------------------------*/
nbu2ss_gad_get_frame(struct usb_gadget * pgadget)2828 static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2829 {
2830 u32 data;
2831 struct nbu2ss_udc *udc;
2832
2833 if (!pgadget) {
2834 pr_err("udc: %s, bad param\n", __func__);
2835 return -EINVAL;
2836 }
2837
2838 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2839 data = gpiod_get_value(vbus_gpio);
2840 if (data == 0)
2841 return -EINVAL;
2842
2843 return _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
2844 }
2845
2846 /*-------------------------------------------------------------------------*/
nbu2ss_gad_wakeup(struct usb_gadget * pgadget)2847 static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
2848 {
2849 int i;
2850 u32 data;
2851
2852 struct nbu2ss_udc *udc;
2853
2854 if (!pgadget) {
2855 pr_err("%s, bad param\n", __func__);
2856 return -EINVAL;
2857 }
2858
2859 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2860
2861 data = gpiod_get_value(vbus_gpio);
2862 if (data == 0) {
2863 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
2864 return -EINVAL;
2865 }
2866
2867 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
2868
2869 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2870 data = _nbu2ss_readl(&udc->p_regs->EPCTR);
2871
2872 if (data & PLL_LOCK)
2873 break;
2874 }
2875
2876 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
2877
2878 return 0;
2879 }
2880
2881 /*-------------------------------------------------------------------------*/
nbu2ss_gad_set_selfpowered(struct usb_gadget * pgadget,int is_selfpowered)2882 static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
2883 int is_selfpowered)
2884 {
2885 struct nbu2ss_udc *udc;
2886 unsigned long flags;
2887
2888 if (!pgadget) {
2889 pr_err("%s, bad param\n", __func__);
2890 return -EINVAL;
2891 }
2892
2893 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2894
2895 spin_lock_irqsave(&udc->lock, flags);
2896 pgadget->is_selfpowered = (is_selfpowered != 0);
2897 spin_unlock_irqrestore(&udc->lock, flags);
2898
2899 return 0;
2900 }
2901
2902 /*-------------------------------------------------------------------------*/
nbu2ss_gad_vbus_session(struct usb_gadget * pgadget,int is_active)2903 static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
2904 {
2905 return 0;
2906 }
2907
2908 /*-------------------------------------------------------------------------*/
nbu2ss_gad_vbus_draw(struct usb_gadget * pgadget,unsigned int mA)2909 static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA)
2910 {
2911 struct nbu2ss_udc *udc;
2912 unsigned long flags;
2913
2914 if (!pgadget) {
2915 pr_err("%s, bad param\n", __func__);
2916 return -EINVAL;
2917 }
2918
2919 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2920
2921 spin_lock_irqsave(&udc->lock, flags);
2922 udc->mA = mA;
2923 spin_unlock_irqrestore(&udc->lock, flags);
2924
2925 return 0;
2926 }
2927
2928 /*-------------------------------------------------------------------------*/
nbu2ss_gad_pullup(struct usb_gadget * pgadget,int is_on)2929 static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
2930 {
2931 struct nbu2ss_udc *udc;
2932 unsigned long flags;
2933
2934 if (!pgadget) {
2935 pr_err("%s, bad param\n", __func__);
2936 return -EINVAL;
2937 }
2938
2939 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2940
2941 if (!udc->driver) {
2942 pr_warn("%s, Not Regist Driver\n", __func__);
2943 return -EINVAL;
2944 }
2945
2946 if (udc->vbus_active == 0)
2947 return -ESHUTDOWN;
2948
2949 spin_lock_irqsave(&udc->lock, flags);
2950 _nbu2ss_pullup(udc, is_on);
2951 spin_unlock_irqrestore(&udc->lock, flags);
2952
2953 return 0;
2954 }
2955
2956 /*-------------------------------------------------------------------------*/
nbu2ss_gad_ioctl(struct usb_gadget * pgadget,unsigned int code,unsigned long param)2957 static int nbu2ss_gad_ioctl(struct usb_gadget *pgadget,
2958 unsigned int code, unsigned long param)
2959 {
2960 return 0;
2961 }
2962
2963 static const struct usb_gadget_ops nbu2ss_gadget_ops = {
2964 .get_frame = nbu2ss_gad_get_frame,
2965 .wakeup = nbu2ss_gad_wakeup,
2966 .set_selfpowered = nbu2ss_gad_set_selfpowered,
2967 .vbus_session = nbu2ss_gad_vbus_session,
2968 .vbus_draw = nbu2ss_gad_vbus_draw,
2969 .pullup = nbu2ss_gad_pullup,
2970 .ioctl = nbu2ss_gad_ioctl,
2971 };
2972
2973 static const struct {
2974 const char *name;
2975 const struct usb_ep_caps caps;
2976 } ep_info[NUM_ENDPOINTS] = {
2977 #define EP_INFO(_name, _caps) \
2978 { \
2979 .name = _name, \
2980 .caps = _caps, \
2981 }
2982
2983 EP_INFO("ep0",
2984 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
2985 EP_INFO("ep1-bulk",
2986 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2987 EP_INFO("ep2-bulk",
2988 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2989 EP_INFO("ep3in-int",
2990 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2991 EP_INFO("ep4-iso",
2992 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2993 EP_INFO("ep5-iso",
2994 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2995 EP_INFO("ep6-bulk",
2996 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2997 EP_INFO("ep7-bulk",
2998 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2999 EP_INFO("ep8in-int",
3000 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3001 EP_INFO("ep9-iso",
3002 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3003 EP_INFO("epa-iso",
3004 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3005 EP_INFO("epb-bulk",
3006 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3007 EP_INFO("epc-bulk",
3008 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3009 EP_INFO("epdin-int",
3010 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3011
3012 #undef EP_INFO
3013 };
3014
3015 /*-------------------------------------------------------------------------*/
nbu2ss_drv_ep_init(struct nbu2ss_udc * udc)3016 static void nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3017 {
3018 int i;
3019
3020 INIT_LIST_HEAD(&udc->gadget.ep_list);
3021 udc->gadget.ep0 = &udc->ep[0].ep;
3022
3023 for (i = 0; i < NUM_ENDPOINTS; i++) {
3024 struct nbu2ss_ep *ep = &udc->ep[i];
3025
3026 ep->udc = udc;
3027 ep->desc = NULL;
3028
3029 ep->ep.driver_data = NULL;
3030 ep->ep.name = ep_info[i].name;
3031 ep->ep.caps = ep_info[i].caps;
3032 ep->ep.ops = &nbu2ss_ep_ops;
3033
3034 usb_ep_set_maxpacket_limit(&ep->ep,
3035 i == 0 ? EP0_PACKETSIZE
3036 : EP_PACKETSIZE);
3037
3038 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3039 INIT_LIST_HEAD(&ep->queue);
3040 }
3041
3042 list_del_init(&udc->ep[0].ep.ep_list);
3043 }
3044
3045 /*-------------------------------------------------------------------------*/
3046 /* platform_driver */
nbu2ss_drv_contest_init(struct platform_device * pdev,struct nbu2ss_udc * udc)3047 static int nbu2ss_drv_contest_init(struct platform_device *pdev,
3048 struct nbu2ss_udc *udc)
3049 {
3050 spin_lock_init(&udc->lock);
3051 udc->dev = &pdev->dev;
3052
3053 udc->gadget.is_selfpowered = 1;
3054 udc->devstate = USB_STATE_NOTATTACHED;
3055 udc->pdev = pdev;
3056 udc->mA = 0;
3057
3058 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3059
3060 /* init Endpoint */
3061 nbu2ss_drv_ep_init(udc);
3062
3063 /* init Gadget */
3064 udc->gadget.ops = &nbu2ss_gadget_ops;
3065 udc->gadget.ep0 = &udc->ep[0].ep;
3066 udc->gadget.speed = USB_SPEED_UNKNOWN;
3067 udc->gadget.name = driver_name;
3068 /* udc->gadget.is_dualspeed = 1; */
3069
3070 device_initialize(&udc->gadget.dev);
3071
3072 dev_set_name(&udc->gadget.dev, "gadget");
3073 udc->gadget.dev.parent = &pdev->dev;
3074 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3075
3076 return 0;
3077 }
3078
3079 /*
3080 * probe - binds to the platform device
3081 */
nbu2ss_drv_probe(struct platform_device * pdev)3082 static int nbu2ss_drv_probe(struct platform_device *pdev)
3083 {
3084 int status = -ENODEV;
3085 struct nbu2ss_udc *udc;
3086 struct resource *r;
3087 int irq;
3088 void __iomem *mmio_base;
3089
3090 udc = &udc_controller;
3091 memset(udc, 0, sizeof(struct nbu2ss_udc));
3092
3093 platform_set_drvdata(pdev, udc);
3094
3095 /* require I/O memory and IRQ to be provided as resources */
3096 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3097 mmio_base = devm_ioremap_resource(&pdev->dev, r);
3098 if (IS_ERR(mmio_base))
3099 return PTR_ERR(mmio_base);
3100
3101 irq = platform_get_irq(pdev, 0);
3102 if (irq < 0)
3103 return irq;
3104 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3105 0, driver_name, udc);
3106
3107 /* IO Memory */
3108 udc->p_regs = (struct fc_regs __iomem *)mmio_base;
3109
3110 /* USB Function Controller Interrupt */
3111 if (status != 0) {
3112 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
3113 return status;
3114 }
3115
3116 /* Driver Initialization */
3117 status = nbu2ss_drv_contest_init(pdev, udc);
3118 if (status < 0) {
3119 /* Error */
3120 return status;
3121 }
3122
3123 /* VBUS Interrupt */
3124 vbus_irq = gpiod_to_irq(vbus_gpio);
3125 irq_set_irq_type(vbus_irq, IRQ_TYPE_EDGE_BOTH);
3126 status = request_irq(vbus_irq,
3127 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc);
3128
3129 if (status != 0) {
3130 dev_err(udc->dev, "request_irq(vbus_irq) failed\n");
3131 return status;
3132 }
3133
3134 return status;
3135 }
3136
3137 /*-------------------------------------------------------------------------*/
nbu2ss_drv_shutdown(struct platform_device * pdev)3138 static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3139 {
3140 struct nbu2ss_udc *udc;
3141
3142 udc = platform_get_drvdata(pdev);
3143 if (!udc)
3144 return;
3145
3146 _nbu2ss_disable_controller(udc);
3147 }
3148
3149 /*-------------------------------------------------------------------------*/
nbu2ss_drv_remove(struct platform_device * pdev)3150 static int nbu2ss_drv_remove(struct platform_device *pdev)
3151 {
3152 struct nbu2ss_udc *udc;
3153 struct nbu2ss_ep *ep;
3154 int i;
3155
3156 udc = &udc_controller;
3157
3158 for (i = 0; i < NUM_ENDPOINTS; i++) {
3159 ep = &udc->ep[i];
3160 if (ep->virt_buf)
3161 dma_free_coherent(udc->dev, PAGE_SIZE, (void *)ep->virt_buf,
3162 ep->phys_buf);
3163 }
3164
3165 /* Interrupt Handler - Release */
3166 free_irq(vbus_irq, udc);
3167
3168 return 0;
3169 }
3170
3171 /*-------------------------------------------------------------------------*/
nbu2ss_drv_suspend(struct platform_device * pdev,pm_message_t state)3172 static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3173 {
3174 struct nbu2ss_udc *udc;
3175
3176 udc = platform_get_drvdata(pdev);
3177 if (!udc)
3178 return 0;
3179
3180 if (udc->vbus_active) {
3181 udc->vbus_active = 0;
3182 udc->devstate = USB_STATE_NOTATTACHED;
3183 udc->linux_suspended = 1;
3184
3185 if (udc->usb_suspended) {
3186 udc->usb_suspended = 0;
3187 _nbu2ss_reset_controller(udc);
3188 }
3189
3190 _nbu2ss_quiesce(udc);
3191 }
3192 _nbu2ss_disable_controller(udc);
3193
3194 return 0;
3195 }
3196
3197 /*-------------------------------------------------------------------------*/
nbu2ss_drv_resume(struct platform_device * pdev)3198 static int nbu2ss_drv_resume(struct platform_device *pdev)
3199 {
3200 u32 data;
3201 struct nbu2ss_udc *udc;
3202
3203 udc = platform_get_drvdata(pdev);
3204 if (!udc)
3205 return 0;
3206
3207 data = gpiod_get_value(vbus_gpio);
3208 if (data) {
3209 udc->vbus_active = 1;
3210 udc->devstate = USB_STATE_POWERED;
3211 _nbu2ss_enable_controller(udc);
3212 _nbu2ss_pullup(udc, 1);
3213 }
3214
3215 udc->linux_suspended = 0;
3216
3217 return 0;
3218 }
3219
3220 static struct platform_driver udc_driver = {
3221 .probe = nbu2ss_drv_probe,
3222 .shutdown = nbu2ss_drv_shutdown,
3223 .remove = nbu2ss_drv_remove,
3224 .suspend = nbu2ss_drv_suspend,
3225 .resume = nbu2ss_drv_resume,
3226 .driver = {
3227 .name = driver_name,
3228 },
3229 };
3230
3231 module_platform_driver(udc_driver);
3232
3233 MODULE_DESCRIPTION(DRIVER_DESC);
3234 MODULE_AUTHOR("Renesas Electronics Corporation");
3235 MODULE_LICENSE("GPL");
3236