1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * FB driver for the ILI9320 LCD Controller
4 *
5 * Copyright (C) 2013 Noralf Tronnes
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/spi/spi.h>
12 #include <linux/delay.h>
13
14 #include "fbtft.h"
15
16 #define DRVNAME "fb_ili9320"
17 #define WIDTH 240
18 #define HEIGHT 320
19 #define DEFAULT_GAMMA "07 07 6 0 0 0 5 5 4 0\n" \
20 "07 08 4 7 5 1 2 0 7 7"
21
read_devicecode(struct fbtft_par * par)22 static unsigned int read_devicecode(struct fbtft_par *par)
23 {
24 int ret;
25 u8 rxbuf[8] = {0, };
26
27 write_reg(par, 0x0000);
28 ret = par->fbtftops.read(par, rxbuf, 4);
29 return (rxbuf[2] << 8) | rxbuf[3];
30 }
31
init_display(struct fbtft_par * par)32 static int init_display(struct fbtft_par *par)
33 {
34 unsigned int devcode;
35
36 par->fbtftops.reset(par);
37
38 devcode = read_devicecode(par);
39 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n",
40 devcode);
41 if ((devcode != 0x0000) && (devcode != 0x9320))
42 dev_warn(par->info->device,
43 "Unrecognized Device code: 0x%04X (expected 0x9320)\n",
44 devcode);
45
46 /* Initialization sequence from ILI9320 Application Notes */
47
48 /* *********** Start Initial Sequence ********* */
49 /* Set the Vcore voltage and this setting is must. */
50 write_reg(par, 0x00E5, 0x8000);
51
52 /* Start internal OSC. */
53 write_reg(par, 0x0000, 0x0001);
54
55 /* set SS and SM bit */
56 write_reg(par, 0x0001, 0x0100);
57
58 /* set 1 line inversion */
59 write_reg(par, 0x0002, 0x0700);
60
61 /* Resize register */
62 write_reg(par, 0x0004, 0x0000);
63
64 /* set the back and front porch */
65 write_reg(par, 0x0008, 0x0202);
66
67 /* set non-display area refresh cycle */
68 write_reg(par, 0x0009, 0x0000);
69
70 /* FMARK function */
71 write_reg(par, 0x000A, 0x0000);
72
73 /* RGB interface setting */
74 write_reg(par, 0x000C, 0x0000);
75
76 /* Frame marker Position */
77 write_reg(par, 0x000D, 0x0000);
78
79 /* RGB interface polarity */
80 write_reg(par, 0x000F, 0x0000);
81
82 /* ***********Power On sequence *************** */
83 /* SAP, BT[3:0], AP, DSTB, SLP, STB */
84 write_reg(par, 0x0010, 0x0000);
85
86 /* DC1[2:0], DC0[2:0], VC[2:0] */
87 write_reg(par, 0x0011, 0x0007);
88
89 /* VREG1OUT voltage */
90 write_reg(par, 0x0012, 0x0000);
91
92 /* VDV[4:0] for VCOM amplitude */
93 write_reg(par, 0x0013, 0x0000);
94
95 /* Dis-charge capacitor power voltage */
96 mdelay(200);
97
98 /* SAP, BT[3:0], AP, DSTB, SLP, STB */
99 write_reg(par, 0x0010, 0x17B0);
100
101 /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */
102 write_reg(par, 0x0011, 0x0031);
103 mdelay(50);
104
105 /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */
106 write_reg(par, 0x0012, 0x0138);
107 mdelay(50);
108
109 /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */
110 write_reg(par, 0x0013, 0x1800);
111
112 /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */
113 write_reg(par, 0x0029, 0x0008);
114 mdelay(50);
115
116 /* GRAM horizontal Address */
117 write_reg(par, 0x0020, 0x0000);
118
119 /* GRAM Vertical Address */
120 write_reg(par, 0x0021, 0x0000);
121
122 /* ------------------ Set GRAM area --------------- */
123 /* Horizontal GRAM Start Address */
124 write_reg(par, 0x0050, 0x0000);
125
126 /* Horizontal GRAM End Address */
127 write_reg(par, 0x0051, 0x00EF);
128
129 /* Vertical GRAM Start Address */
130 write_reg(par, 0x0052, 0x0000);
131
132 /* Vertical GRAM End Address */
133 write_reg(par, 0x0053, 0x013F);
134
135 /* Gate Scan Line */
136 write_reg(par, 0x0060, 0x2700);
137
138 /* NDL,VLE, REV */
139 write_reg(par, 0x0061, 0x0001);
140
141 /* set scrolling line */
142 write_reg(par, 0x006A, 0x0000);
143
144 /* -------------- Partial Display Control --------- */
145 write_reg(par, 0x0080, 0x0000);
146 write_reg(par, 0x0081, 0x0000);
147 write_reg(par, 0x0082, 0x0000);
148 write_reg(par, 0x0083, 0x0000);
149 write_reg(par, 0x0084, 0x0000);
150 write_reg(par, 0x0085, 0x0000);
151
152 /* -------------- Panel Control ------------------- */
153 write_reg(par, 0x0090, 0x0010);
154 write_reg(par, 0x0092, 0x0000);
155 write_reg(par, 0x0093, 0x0003);
156 write_reg(par, 0x0095, 0x0110);
157 write_reg(par, 0x0097, 0x0000);
158 write_reg(par, 0x0098, 0x0000);
159 write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */
160
161 return 0;
162 }
163
set_addr_win(struct fbtft_par * par,int xs,int ys,int xe,int ye)164 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
165 {
166 switch (par->info->var.rotate) {
167 /* R20h = Horizontal GRAM Start Address */
168 /* R21h = Vertical GRAM Start Address */
169 case 0:
170 write_reg(par, 0x0020, xs);
171 write_reg(par, 0x0021, ys);
172 break;
173 case 180:
174 write_reg(par, 0x0020, WIDTH - 1 - xs);
175 write_reg(par, 0x0021, HEIGHT - 1 - ys);
176 break;
177 case 270:
178 write_reg(par, 0x0020, WIDTH - 1 - ys);
179 write_reg(par, 0x0021, xs);
180 break;
181 case 90:
182 write_reg(par, 0x0020, ys);
183 write_reg(par, 0x0021, HEIGHT - 1 - xs);
184 break;
185 }
186 write_reg(par, 0x0022); /* Write Data to GRAM */
187 }
188
set_var(struct fbtft_par * par)189 static int set_var(struct fbtft_par *par)
190 {
191 switch (par->info->var.rotate) {
192 case 0:
193 write_reg(par, 0x3, (par->bgr << 12) | 0x30);
194 break;
195 case 270:
196 write_reg(par, 0x3, (par->bgr << 12) | 0x28);
197 break;
198 case 180:
199 write_reg(par, 0x3, (par->bgr << 12) | 0x00);
200 break;
201 case 90:
202 write_reg(par, 0x3, (par->bgr << 12) | 0x18);
203 break;
204 }
205 return 0;
206 }
207
208 /*
209 * Gamma string format:
210 * VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
211 * VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
212 */
213 #define CURVE(num, idx) curves[(num) * par->gamma.num_values + (idx)]
set_gamma(struct fbtft_par * par,u32 * curves)214 static int set_gamma(struct fbtft_par *par, u32 *curves)
215 {
216 static const unsigned long mask[] = {
217 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
218 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
219 };
220 int i, j;
221
222 /* apply mask */
223 for (i = 0; i < 2; i++)
224 for (j = 0; j < 10; j++)
225 CURVE(i, j) &= mask[i * par->gamma.num_values + j];
226
227 write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
228 write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
229 write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
230 write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
231 write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
232
233 write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
234 write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
235 write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
236 write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
237 write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));
238
239 return 0;
240 }
241
242 #undef CURVE
243
244 static struct fbtft_display display = {
245 .regwidth = 16,
246 .width = WIDTH,
247 .height = HEIGHT,
248 .gamma_num = 2,
249 .gamma_len = 10,
250 .gamma = DEFAULT_GAMMA,
251 .fbtftops = {
252 .init_display = init_display,
253 .set_addr_win = set_addr_win,
254 .set_var = set_var,
255 .set_gamma = set_gamma,
256 },
257 };
258
259 FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);
260
261 MODULE_ALIAS("spi:" DRVNAME);
262 MODULE_ALIAS("platform:" DRVNAME);
263 MODULE_ALIAS("spi:ili9320");
264 MODULE_ALIAS("platform:ili9320");
265
266 MODULE_DESCRIPTION("FB driver for the ILI9320 LCD Controller");
267 MODULE_AUTHOR("Noralf Tronnes");
268 MODULE_LICENSE("GPL");
269